base_dyn_inst.hh revision 11097:da477ae38907
1/* 2 * Copyright (c) 2011,2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * Copyright (c) 2009 The University of Edinburgh 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Timothy M. Jones 44 */ 45 46#ifndef __CPU_BASE_DYN_INST_HH__ 47#define __CPU_BASE_DYN_INST_HH__ 48 49#include <array> 50#include <bitset> 51#include <list> 52#include <string> 53#include <queue> 54 55#include "arch/generic/tlb.hh" 56#include "arch/utility.hh" 57#include "base/trace.hh" 58#include "config/the_isa.hh" 59#include "cpu/checker/cpu.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/exec_context.hh" 62#include "cpu/exetrace.hh" 63#include "cpu/inst_seq.hh" 64#include "cpu/op_class.hh" 65#include "cpu/static_inst.hh" 66#include "cpu/translation.hh" 67#include "mem/packet.hh" 68#include "sim/byteswap.hh" 69#include "sim/system.hh" 70 71/** 72 * @file 73 * Defines a dynamic instruction context. 74 */ 75 76template <class Impl> 77class BaseDynInst : public ExecContext, public RefCounted 78{ 79 public: 80 // Typedef for the CPU. 81 typedef typename Impl::CPUType ImplCPU; 82 typedef typename ImplCPU::ImplState ImplState; 83 84 // Logical register index type. 85 typedef TheISA::RegIndex RegIndex; 86 87 // The DynInstPtr type. 88 typedef typename Impl::DynInstPtr DynInstPtr; 89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 90 91 // The list of instructions iterator type. 92 typedef typename std::list<DynInstPtr>::iterator ListIt; 93 94 enum { 95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 97 }; 98 99 union Result { 100 uint64_t integer; 101 double dbl; 102 void set(uint64_t i) { integer = i; } 103 void set(double d) { dbl = d; } 104 void get(uint64_t& i) { i = integer; } 105 void get(double& d) { d = dbl; } 106 }; 107 108 protected: 109 enum Status { 110 IqEntry, /// Instruction is in the IQ 111 RobEntry, /// Instruction is in the ROB 112 LsqEntry, /// Instruction is in the LSQ 113 Completed, /// Instruction has completed 114 ResultReady, /// Instruction has its result 115 CanIssue, /// Instruction can issue and execute 116 Issued, /// Instruction has issued 117 Executed, /// Instruction has executed 118 CanCommit, /// Instruction can commit 119 AtCommit, /// Instruction has reached commit 120 Committed, /// Instruction has committed 121 Squashed, /// Instruction is squashed 122 SquashedInIQ, /// Instruction is squashed in the IQ 123 SquashedInLSQ, /// Instruction is squashed in the LSQ 124 SquashedInROB, /// Instruction is squashed in the ROB 125 RecoverInst, /// Is a recover instruction 126 BlockingInst, /// Is a blocking instruction 127 ThreadsyncWait, /// Is a thread synchronization instruction 128 SerializeBefore, /// Needs to serialize on 129 /// instructions ahead of it 130 SerializeAfter, /// Needs to serialize instructions behind it 131 SerializeHandled, /// Serialization has been handled 132 NumStatus 133 }; 134 135 enum Flags { 136 TranslationStarted, 137 TranslationCompleted, 138 PossibleLoadViolation, 139 HitExternalSnoop, 140 EffAddrValid, 141 RecordResult, 142 Predicate, 143 PredTaken, 144 /** Whether or not the effective address calculation is completed. 145 * @todo: Consider if this is necessary or not. 146 */ 147 EACalcDone, 148 IsStrictlyOrdered, 149 ReqMade, 150 MemOpDone, 151 MaxFlags 152 }; 153 154 public: 155 /** The sequence number of the instruction. */ 156 InstSeqNum seqNum; 157 158 /** The StaticInst used by this BaseDynInst. */ 159 const StaticInstPtr staticInst; 160 161 /** Pointer to the Impl's CPU object. */ 162 ImplCPU *cpu; 163 164 BaseCPU *getCpuPtr() { return cpu; } 165 166 /** Pointer to the thread state. */ 167 ImplState *thread; 168 169 /** The kind of fault this instruction has generated. */ 170 Fault fault; 171 172 /** InstRecord that tracks this instructions. */ 173 Trace::InstRecord *traceData; 174 175 protected: 176 /** The result of the instruction; assumes an instruction can have many 177 * destination registers. 178 */ 179 std::queue<Result> instResult; 180 181 /** PC state for this instruction. */ 182 TheISA::PCState pc; 183 184 /* An amalgamation of a lot of boolean values into one */ 185 std::bitset<MaxFlags> instFlags; 186 187 /** The status of this BaseDynInst. Several bits can be set. */ 188 std::bitset<NumStatus> status; 189 190 /** Whether or not the source register is ready. 191 * @todo: Not sure this should be here vs the derived class. 192 */ 193 std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 194 195 public: 196 /** The thread this instruction is from. */ 197 ThreadID threadNumber; 198 199 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 200 ListIt instListIt; 201 202 ////////////////////// Branch Data /////////////// 203 /** Predicted PC state after this instruction. */ 204 TheISA::PCState predPC; 205 206 /** The Macroop if one exists */ 207 const StaticInstPtr macroop; 208 209 /** How many source registers are ready. */ 210 uint8_t readyRegs; 211 212 public: 213 /////////////////////// Load Store Data ////////////////////// 214 /** The effective virtual address (lds & stores only). */ 215 Addr effAddr; 216 217 /** The effective physical address. */ 218 Addr physEffAddrLow; 219 220 /** The effective physical address 221 * of the second request for a split request 222 */ 223 Addr physEffAddrHigh; 224 225 /** The memory request flags (from translation). */ 226 unsigned memReqFlags; 227 228 /** data address space ID, for loads & stores. */ 229 short asid; 230 231 /** The size of the request */ 232 uint8_t effSize; 233 234 /** Pointer to the data for the memory access. */ 235 uint8_t *memData; 236 237 /** Load queue index. */ 238 int16_t lqIdx; 239 240 /** Store queue index. */ 241 int16_t sqIdx; 242 243 244 /////////////////////// TLB Miss ////////////////////// 245 /** 246 * Saved memory requests (needed when the DTB address translation is 247 * delayed due to a hw page table walk). 248 */ 249 RequestPtr savedReq; 250 RequestPtr savedSreqLow; 251 RequestPtr savedSreqHigh; 252 253 /////////////////////// Checker ////////////////////// 254 // Need a copy of main request pointer to verify on writes. 255 RequestPtr reqToVerify; 256 257 private: 258 /** Instruction effective address. 259 * @todo: Consider if this is necessary or not. 260 */ 261 Addr instEffAddr; 262 263 protected: 264 /** Flattened register index of the destination registers of this 265 * instruction. 266 */ 267 std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx; 268 269 /** Physical register index of the destination registers of this 270 * instruction. 271 */ 272 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx; 273 274 /** Physical register index of the source registers of this 275 * instruction. 276 */ 277 std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx; 278 279 /** Physical register index of the previous producers of the 280 * architected destinations. 281 */ 282 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx; 283 284 285 public: 286 /** Records changes to result? */ 287 void recordResult(bool f) { instFlags[RecordResult] = f; } 288 289 /** Is the effective virtual address valid. */ 290 bool effAddrValid() const { return instFlags[EffAddrValid]; } 291 292 /** Whether or not the memory operation is done. */ 293 bool memOpDone() const { return instFlags[MemOpDone]; } 294 void memOpDone(bool f) { instFlags[MemOpDone] = f; } 295 296 297 //////////////////////////////////////////// 298 // 299 // INSTRUCTION EXECUTION 300 // 301 //////////////////////////////////////////// 302 303 void demapPage(Addr vaddr, uint64_t asn) 304 { 305 cpu->demapPage(vaddr, asn); 306 } 307 void demapInstPage(Addr vaddr, uint64_t asn) 308 { 309 cpu->demapPage(vaddr, asn); 310 } 311 void demapDataPage(Addr vaddr, uint64_t asn) 312 { 313 cpu->demapPage(vaddr, asn); 314 } 315 316 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 317 318 Fault writeMem(uint8_t *data, unsigned size, 319 Addr addr, unsigned flags, uint64_t *res); 320 321 /** Splits a request in two if it crosses a dcache block. */ 322 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 323 RequestPtr &sreqHigh); 324 325 /** Initiate a DTB address translation. */ 326 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 327 RequestPtr sreqHigh, uint64_t *res, 328 BaseTLB::Mode mode); 329 330 /** Finish a DTB address translation. */ 331 void finishTranslation(WholeTranslationState *state); 332 333 /** True if the DTB address translation has started. */ 334 bool translationStarted() const { return instFlags[TranslationStarted]; } 335 void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 336 337 /** True if the DTB address translation has completed. */ 338 bool translationCompleted() const { return instFlags[TranslationCompleted]; } 339 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 340 341 /** True if this address was found to match a previous load and they issued 342 * out of order. If that happend, then it's only a problem if an incoming 343 * snoop invalidate modifies the line, in which case we need to squash. 344 * If nothing modified the line the order doesn't matter. 345 */ 346 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 347 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 348 349 /** True if the address hit a external snoop while sitting in the LSQ. 350 * If this is true and a older instruction sees it, this instruction must 351 * reexecute 352 */ 353 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 354 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 355 356 /** 357 * Returns true if the DTB address translation is being delayed due to a hw 358 * page table walk. 359 */ 360 bool isTranslationDelayed() const 361 { 362 return (translationStarted() && !translationCompleted()); 363 } 364 365 public: 366#ifdef DEBUG 367 void dumpSNList(); 368#endif 369 370 /** Returns the physical register index of the i'th destination 371 * register. 372 */ 373 PhysRegIndex renamedDestRegIdx(int idx) const 374 { 375 return _destRegIdx[idx]; 376 } 377 378 /** Returns the physical register index of the i'th source register. */ 379 PhysRegIndex renamedSrcRegIdx(int idx) const 380 { 381 assert(TheISA::MaxInstSrcRegs > idx); 382 return _srcRegIdx[idx]; 383 } 384 385 /** Returns the flattened register index of the i'th destination 386 * register. 387 */ 388 TheISA::RegIndex flattenedDestRegIdx(int idx) const 389 { 390 return _flatDestRegIdx[idx]; 391 } 392 393 /** Returns the physical register index of the previous physical register 394 * that remapped to the same logical register index. 395 */ 396 PhysRegIndex prevDestRegIdx(int idx) const 397 { 398 return _prevDestRegIdx[idx]; 399 } 400 401 /** Renames a destination register to a physical register. Also records 402 * the previous physical register that the logical register mapped to. 403 */ 404 void renameDestReg(int idx, 405 PhysRegIndex renamed_dest, 406 PhysRegIndex previous_rename) 407 { 408 _destRegIdx[idx] = renamed_dest; 409 _prevDestRegIdx[idx] = previous_rename; 410 } 411 412 /** Renames a source logical register to the physical register which 413 * has/will produce that logical register's result. 414 * @todo: add in whether or not the source register is ready. 415 */ 416 void renameSrcReg(int idx, PhysRegIndex renamed_src) 417 { 418 _srcRegIdx[idx] = renamed_src; 419 } 420 421 /** Flattens a destination architectural register index into a logical 422 * index. 423 */ 424 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 425 { 426 _flatDestRegIdx[idx] = flattened_dest; 427 } 428 /** BaseDynInst constructor given a binary instruction. 429 * @param staticInst A StaticInstPtr to the underlying instruction. 430 * @param pc The PC state for the instruction. 431 * @param predPC The predicted next PC state for the instruction. 432 * @param seq_num The sequence number of the instruction. 433 * @param cpu Pointer to the instruction's CPU. 434 */ 435 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 436 TheISA::PCState pc, TheISA::PCState predPC, 437 InstSeqNum seq_num, ImplCPU *cpu); 438 439 /** BaseDynInst constructor given a StaticInst pointer. 440 * @param _staticInst The StaticInst for this BaseDynInst. 441 */ 442 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 443 444 /** BaseDynInst destructor. */ 445 ~BaseDynInst(); 446 447 private: 448 /** Function to initialize variables in the constructors. */ 449 void initVars(); 450 451 public: 452 /** Dumps out contents of this BaseDynInst. */ 453 void dump(); 454 455 /** Dumps out contents of this BaseDynInst into given string. */ 456 void dump(std::string &outstring); 457 458 /** Read this CPU's ID. */ 459 int cpuId() const { return cpu->cpuId(); } 460 461 /** Read this CPU's Socket ID. */ 462 uint32_t socketId() const { return cpu->socketId(); } 463 464 /** Read this CPU's data requestor ID */ 465 MasterID masterId() const { return cpu->dataMasterId(); } 466 467 /** Read this context's system-wide ID **/ 468 ContextID contextId() const { return thread->contextId(); } 469 470 /** Returns the fault type. */ 471 Fault getFault() const { return fault; } 472 473 /** Checks whether or not this instruction has had its branch target 474 * calculated yet. For now it is not utilized and is hacked to be 475 * always false. 476 * @todo: Actually use this instruction. 477 */ 478 bool doneTargCalc() { return false; } 479 480 /** Set the predicted target of this current instruction. */ 481 void setPredTarg(const TheISA::PCState &_predPC) 482 { 483 predPC = _predPC; 484 } 485 486 const TheISA::PCState &readPredTarg() { return predPC; } 487 488 /** Returns the predicted PC immediately after the branch. */ 489 Addr predInstAddr() { return predPC.instAddr(); } 490 491 /** Returns the predicted PC two instructions after the branch */ 492 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 493 494 /** Returns the predicted micro PC after the branch */ 495 Addr predMicroPC() { return predPC.microPC(); } 496 497 /** Returns whether the instruction was predicted taken or not. */ 498 bool readPredTaken() 499 { 500 return instFlags[PredTaken]; 501 } 502 503 void setPredTaken(bool predicted_taken) 504 { 505 instFlags[PredTaken] = predicted_taken; 506 } 507 508 /** Returns whether the instruction mispredicted. */ 509 bool mispredicted() 510 { 511 TheISA::PCState tempPC = pc; 512 TheISA::advancePC(tempPC, staticInst); 513 return !(tempPC == predPC); 514 } 515 516 // 517 // Instruction types. Forward checks to StaticInst object. 518 // 519 bool isNop() const { return staticInst->isNop(); } 520 bool isMemRef() const { return staticInst->isMemRef(); } 521 bool isLoad() const { return staticInst->isLoad(); } 522 bool isStore() const { return staticInst->isStore(); } 523 bool isStoreConditional() const 524 { return staticInst->isStoreConditional(); } 525 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 526 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 527 bool isInteger() const { return staticInst->isInteger(); } 528 bool isFloating() const { return staticInst->isFloating(); } 529 bool isControl() const { return staticInst->isControl(); } 530 bool isCall() const { return staticInst->isCall(); } 531 bool isReturn() const { return staticInst->isReturn(); } 532 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 533 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 534 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 535 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 536 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 537 bool isThreadSync() const { return staticInst->isThreadSync(); } 538 bool isSerializing() const { return staticInst->isSerializing(); } 539 bool isSerializeBefore() const 540 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 541 bool isSerializeAfter() const 542 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 543 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 544 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 545 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 546 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 547 bool isQuiesce() const { return staticInst->isQuiesce(); } 548 bool isIprAccess() const { return staticInst->isIprAccess(); } 549 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 550 bool isSyscall() const { return staticInst->isSyscall(); } 551 bool isMacroop() const { return staticInst->isMacroop(); } 552 bool isMicroop() const { return staticInst->isMicroop(); } 553 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 554 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 555 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 556 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 557 558 /** Temporarily sets this instruction as a serialize before instruction. */ 559 void setSerializeBefore() { status.set(SerializeBefore); } 560 561 /** Clears the serializeBefore part of this instruction. */ 562 void clearSerializeBefore() { status.reset(SerializeBefore); } 563 564 /** Checks if this serializeBefore is only temporarily set. */ 565 bool isTempSerializeBefore() { return status[SerializeBefore]; } 566 567 /** Temporarily sets this instruction as a serialize after instruction. */ 568 void setSerializeAfter() { status.set(SerializeAfter); } 569 570 /** Clears the serializeAfter part of this instruction.*/ 571 void clearSerializeAfter() { status.reset(SerializeAfter); } 572 573 /** Checks if this serializeAfter is only temporarily set. */ 574 bool isTempSerializeAfter() { return status[SerializeAfter]; } 575 576 /** Sets the serialization part of this instruction as handled. */ 577 void setSerializeHandled() { status.set(SerializeHandled); } 578 579 /** Checks if the serialization part of this instruction has been 580 * handled. This does not apply to the temporary serializing 581 * state; it only applies to this instruction's own permanent 582 * serializing state. 583 */ 584 bool isSerializeHandled() { return status[SerializeHandled]; } 585 586 /** Returns the opclass of this instruction. */ 587 OpClass opClass() const { return staticInst->opClass(); } 588 589 /** Returns the branch target address. */ 590 TheISA::PCState branchTarget() const 591 { return staticInst->branchTarget(pc); } 592 593 /** Returns the number of source registers. */ 594 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 595 596 /** Returns the number of destination registers. */ 597 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 598 599 // the following are used to track physical register usage 600 // for machines with separate int & FP reg files 601 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 602 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 603 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 604 605 /** Returns the logical register index of the i'th destination register. */ 606 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 607 608 /** Returns the logical register index of the i'th source register. */ 609 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 610 611 /** Pops a result off the instResult queue */ 612 template <class T> 613 void popResult(T& t) 614 { 615 if (!instResult.empty()) { 616 instResult.front().get(t); 617 instResult.pop(); 618 } 619 } 620 621 /** Read the most recent result stored by this instruction */ 622 template <class T> 623 void readResult(T& t) 624 { 625 instResult.back().get(t); 626 } 627 628 /** Pushes a result onto the instResult queue */ 629 template <class T> 630 void setResult(T t) 631 { 632 if (instFlags[RecordResult]) { 633 Result instRes; 634 instRes.set(t); 635 instResult.push(instRes); 636 } 637 } 638 639 /** Records an integer register being set to a value. */ 640 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 641 { 642 setResult<uint64_t>(val); 643 } 644 645 /** Records a CC register being set to a value. */ 646 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 647 { 648 setResult<uint64_t>(val); 649 } 650 651 /** Records an fp register being set to a value. */ 652 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 653 { 654 setResult<double>(val); 655 } 656 657 /** Records an fp register being set to an integer value. */ 658 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 659 { 660 setResult<uint64_t>(val); 661 } 662 663 /** Records that one of the source registers is ready. */ 664 void markSrcRegReady(); 665 666 /** Marks a specific register as ready. */ 667 void markSrcRegReady(RegIndex src_idx); 668 669 /** Returns if a source register is ready. */ 670 bool isReadySrcRegIdx(int idx) const 671 { 672 return this->_readySrcRegIdx[idx]; 673 } 674 675 /** Sets this instruction as completed. */ 676 void setCompleted() { status.set(Completed); } 677 678 /** Returns whether or not this instruction is completed. */ 679 bool isCompleted() const { return status[Completed]; } 680 681 /** Marks the result as ready. */ 682 void setResultReady() { status.set(ResultReady); } 683 684 /** Returns whether or not the result is ready. */ 685 bool isResultReady() const { return status[ResultReady]; } 686 687 /** Sets this instruction as ready to issue. */ 688 void setCanIssue() { status.set(CanIssue); } 689 690 /** Returns whether or not this instruction is ready to issue. */ 691 bool readyToIssue() const { return status[CanIssue]; } 692 693 /** Clears this instruction being able to issue. */ 694 void clearCanIssue() { status.reset(CanIssue); } 695 696 /** Sets this instruction as issued from the IQ. */ 697 void setIssued() { status.set(Issued); } 698 699 /** Returns whether or not this instruction has issued. */ 700 bool isIssued() const { return status[Issued]; } 701 702 /** Clears this instruction as being issued. */ 703 void clearIssued() { status.reset(Issued); } 704 705 /** Sets this instruction as executed. */ 706 void setExecuted() { status.set(Executed); } 707 708 /** Returns whether or not this instruction has executed. */ 709 bool isExecuted() const { return status[Executed]; } 710 711 /** Sets this instruction as ready to commit. */ 712 void setCanCommit() { status.set(CanCommit); } 713 714 /** Clears this instruction as being ready to commit. */ 715 void clearCanCommit() { status.reset(CanCommit); } 716 717 /** Returns whether or not this instruction is ready to commit. */ 718 bool readyToCommit() const { return status[CanCommit]; } 719 720 void setAtCommit() { status.set(AtCommit); } 721 722 bool isAtCommit() { return status[AtCommit]; } 723 724 /** Sets this instruction as committed. */ 725 void setCommitted() { status.set(Committed); } 726 727 /** Returns whether or not this instruction is committed. */ 728 bool isCommitted() const { return status[Committed]; } 729 730 /** Sets this instruction as squashed. */ 731 void setSquashed() { status.set(Squashed); } 732 733 /** Returns whether or not this instruction is squashed. */ 734 bool isSquashed() const { return status[Squashed]; } 735 736 //Instruction Queue Entry 737 //----------------------- 738 /** Sets this instruction as a entry the IQ. */ 739 void setInIQ() { status.set(IqEntry); } 740 741 /** Sets this instruction as a entry the IQ. */ 742 void clearInIQ() { status.reset(IqEntry); } 743 744 /** Returns whether or not this instruction has issued. */ 745 bool isInIQ() const { return status[IqEntry]; } 746 747 /** Sets this instruction as squashed in the IQ. */ 748 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 749 750 /** Returns whether or not this instruction is squashed in the IQ. */ 751 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 752 753 754 //Load / Store Queue Functions 755 //----------------------- 756 /** Sets this instruction as a entry the LSQ. */ 757 void setInLSQ() { status.set(LsqEntry); } 758 759 /** Sets this instruction as a entry the LSQ. */ 760 void removeInLSQ() { status.reset(LsqEntry); } 761 762 /** Returns whether or not this instruction is in the LSQ. */ 763 bool isInLSQ() const { return status[LsqEntry]; } 764 765 /** Sets this instruction as squashed in the LSQ. */ 766 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 767 768 /** Returns whether or not this instruction is squashed in the LSQ. */ 769 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 770 771 772 //Reorder Buffer Functions 773 //----------------------- 774 /** Sets this instruction as a entry the ROB. */ 775 void setInROB() { status.set(RobEntry); } 776 777 /** Sets this instruction as a entry the ROB. */ 778 void clearInROB() { status.reset(RobEntry); } 779 780 /** Returns whether or not this instruction is in the ROB. */ 781 bool isInROB() const { return status[RobEntry]; } 782 783 /** Sets this instruction as squashed in the ROB. */ 784 void setSquashedInROB() { status.set(SquashedInROB); } 785 786 /** Returns whether or not this instruction is squashed in the ROB. */ 787 bool isSquashedInROB() const { return status[SquashedInROB]; } 788 789 /** Read the PC state of this instruction. */ 790 TheISA::PCState pcState() const { return pc; } 791 792 /** Set the PC state of this instruction. */ 793 void pcState(const TheISA::PCState &val) { pc = val; } 794 795 /** Read the PC of this instruction. */ 796 const Addr instAddr() const { return pc.instAddr(); } 797 798 /** Read the PC of the next instruction. */ 799 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 800 801 /**Read the micro PC of this instruction. */ 802 const Addr microPC() const { return pc.microPC(); } 803 804 bool readPredicate() 805 { 806 return instFlags[Predicate]; 807 } 808 809 void setPredicate(bool val) 810 { 811 instFlags[Predicate] = val; 812 813 if (traceData) { 814 traceData->setPredicate(val); 815 } 816 } 817 818 /** Sets the ASID. */ 819 void setASID(short addr_space_id) { asid = addr_space_id; } 820 821 /** Sets the thread id. */ 822 void setTid(ThreadID tid) { threadNumber = tid; } 823 824 /** Sets the pointer to the thread state. */ 825 void setThreadState(ImplState *state) { thread = state; } 826 827 /** Returns the thread context. */ 828 ThreadContext *tcBase() { return thread->getTC(); } 829 830 public: 831 /** Sets the effective address. */ 832 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 833 834 /** Returns the effective address. */ 835 Addr getEA() const { return instEffAddr; } 836 837 /** Returns whether or not the eff. addr. calculation has been completed. */ 838 bool doneEACalc() { return instFlags[EACalcDone]; } 839 840 /** Returns whether or not the eff. addr. source registers are ready. */ 841 bool eaSrcsReady(); 842 843 /** Is this instruction's memory access strictly ordered? */ 844 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 845 846 /** Has this instruction generated a memory request. */ 847 bool hasRequest() { return instFlags[ReqMade]; } 848 849 /** Returns iterator to this instruction in the list of all insts. */ 850 ListIt &getInstListIt() { return instListIt; } 851 852 /** Sets iterator for this instruction in the list of all insts. */ 853 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 854 855 public: 856 /** Returns the number of consecutive store conditional failures. */ 857 unsigned int readStCondFailures() const 858 { return thread->storeCondFailures; } 859 860 /** Sets the number of consecutive store conditional failures. */ 861 void setStCondFailures(unsigned int sc_failures) 862 { thread->storeCondFailures = sc_failures; } 863 864 public: 865 // monitor/mwait funtions 866 void armMonitor(Addr address) { cpu->armMonitor(address); } 867 bool mwait(PacketPtr pkt) { return cpu->mwait(pkt); } 868 void mwaitAtomic(ThreadContext *tc) 869 { return cpu->mwaitAtomic(tc, cpu->dtb); } 870 AddressMonitor *getAddrMonitor() { return cpu->getCpuAddrMonitor(); } 871}; 872 873template<class Impl> 874Fault 875BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 876 unsigned size, unsigned flags) 877{ 878 instFlags[ReqMade] = true; 879 Request *req = NULL; 880 Request *sreqLow = NULL; 881 Request *sreqHigh = NULL; 882 883 if (instFlags[ReqMade] && translationStarted()) { 884 req = savedReq; 885 sreqLow = savedSreqLow; 886 sreqHigh = savedSreqHigh; 887 } else { 888 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 889 thread->contextId(), threadNumber); 890 891 req->taskId(cpu->taskId()); 892 893 // Only split the request if the ISA supports unaligned accesses. 894 if (TheISA::HasUnalignedMemAcc) { 895 splitRequest(req, sreqLow, sreqHigh); 896 } 897 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 898 } 899 900 if (translationCompleted()) { 901 if (fault == NoFault) { 902 effAddr = req->getVaddr(); 903 effSize = size; 904 instFlags[EffAddrValid] = true; 905 906 if (cpu->checker) { 907 if (reqToVerify != NULL) { 908 delete reqToVerify; 909 } 910 reqToVerify = new Request(*req); 911 } 912 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 913 } else { 914 // Commit will have to clean up whatever happened. Set this 915 // instruction as executed. 916 this->setExecuted(); 917 } 918 919 if (fault != NoFault) { 920 // Return a fixed value to keep simulation deterministic even 921 // along misspeculated paths. 922 if (data) 923 bzero(data, size); 924 } 925 } 926 927 if (traceData) 928 traceData->setMem(addr, size, flags); 929 930 return fault; 931} 932 933template<class Impl> 934Fault 935BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 936 Addr addr, unsigned flags, uint64_t *res) 937{ 938 if (traceData) 939 traceData->setMem(addr, size, flags); 940 941 instFlags[ReqMade] = true; 942 Request *req = NULL; 943 Request *sreqLow = NULL; 944 Request *sreqHigh = NULL; 945 946 if (instFlags[ReqMade] && translationStarted()) { 947 req = savedReq; 948 sreqLow = savedSreqLow; 949 sreqHigh = savedSreqHigh; 950 } else { 951 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 952 thread->contextId(), threadNumber); 953 954 req->taskId(cpu->taskId()); 955 956 // Only split the request if the ISA supports unaligned accesses. 957 if (TheISA::HasUnalignedMemAcc) { 958 splitRequest(req, sreqLow, sreqHigh); 959 } 960 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 961 } 962 963 if (fault == NoFault && translationCompleted()) { 964 effAddr = req->getVaddr(); 965 effSize = size; 966 instFlags[EffAddrValid] = true; 967 968 if (cpu->checker) { 969 if (reqToVerify != NULL) { 970 delete reqToVerify; 971 } 972 reqToVerify = new Request(*req); 973 } 974 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 975 } 976 977 return fault; 978} 979 980template<class Impl> 981inline void 982BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 983 RequestPtr &sreqHigh) 984{ 985 // Check to see if the request crosses the next level block boundary. 986 unsigned block_size = cpu->cacheLineSize(); 987 Addr addr = req->getVaddr(); 988 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 989 assert(split_addr <= addr || split_addr - addr < block_size); 990 991 // Spans two blocks. 992 if (split_addr > addr) { 993 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 994 } 995} 996 997template<class Impl> 998inline void 999BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1000 RequestPtr sreqHigh, uint64_t *res, 1001 BaseTLB::Mode mode) 1002{ 1003 translationStarted(true); 1004 1005 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 1006 WholeTranslationState *state = 1007 new WholeTranslationState(req, NULL, res, mode); 1008 1009 // One translation if the request isn't split. 1010 DataTranslation<BaseDynInstPtr> *trans = 1011 new DataTranslation<BaseDynInstPtr>(this, state); 1012 1013 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1014 1015 if (!translationCompleted()) { 1016 // The translation isn't yet complete, so we can't possibly have a 1017 // fault. Overwrite any existing fault we might have from a previous 1018 // execution of this instruction (e.g. an uncachable load that 1019 // couldn't execute because it wasn't at the head of the ROB). 1020 fault = NoFault; 1021 1022 // Save memory requests. 1023 savedReq = state->mainReq; 1024 savedSreqLow = state->sreqLow; 1025 savedSreqHigh = state->sreqHigh; 1026 } 1027 } else { 1028 WholeTranslationState *state = 1029 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1030 1031 // Two translations when the request is split. 1032 DataTranslation<BaseDynInstPtr> *stransLow = 1033 new DataTranslation<BaseDynInstPtr>(this, state, 0); 1034 DataTranslation<BaseDynInstPtr> *stransHigh = 1035 new DataTranslation<BaseDynInstPtr>(this, state, 1); 1036 1037 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1038 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1039 1040 if (!translationCompleted()) { 1041 // The translation isn't yet complete, so we can't possibly have a 1042 // fault. Overwrite any existing fault we might have from a previous 1043 // execution of this instruction (e.g. an uncachable load that 1044 // couldn't execute because it wasn't at the head of the ROB). 1045 fault = NoFault; 1046 1047 // Save memory requests. 1048 savedReq = state->mainReq; 1049 savedSreqLow = state->sreqLow; 1050 savedSreqHigh = state->sreqHigh; 1051 } 1052 } 1053} 1054 1055template<class Impl> 1056inline void 1057BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1058{ 1059 fault = state->getFault(); 1060 1061 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 1062 1063 if (fault == NoFault) { 1064 // save Paddr for a single req 1065 physEffAddrLow = state->getPaddr(); 1066 1067 // case for the request that has been split 1068 if (state->isSplit) { 1069 physEffAddrLow = state->sreqLow->getPaddr(); 1070 physEffAddrHigh = state->sreqHigh->getPaddr(); 1071 } 1072 1073 memReqFlags = state->getFlags(); 1074 1075 if (state->mainReq->isCondSwap()) { 1076 assert(state->res); 1077 state->mainReq->setExtraData(*state->res); 1078 } 1079 1080 } else { 1081 state->deleteReqs(); 1082 } 1083 delete state; 1084 1085 translationCompleted(true); 1086} 1087 1088#endif // __CPU_BASE_DYN_INST_HH__ 1089