base_dyn_inst.hh revision 8486
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 161060SN/A * All rights reserved. 171060SN/A * 181060SN/A * Redistribution and use in source and binary forms, with or without 191060SN/A * modification, are permitted provided that the following conditions are 201060SN/A * met: redistributions of source code must retain the above copyright 211060SN/A * notice, this list of conditions and the following disclaimer; 221060SN/A * redistributions in binary form must reproduce the above copyright 231060SN/A * notice, this list of conditions and the following disclaimer in the 241060SN/A * documentation and/or other materials provided with the distribution; 251060SN/A * neither the name of the copyright holders nor the names of its 261060SN/A * contributors may be used to endorse or promote products derived from 271060SN/A * this software without specific prior written permission. 281060SN/A * 291060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 426973Stjones1@inf.ed.ac.uk * Timothy M. Jones 431060SN/A */ 441060SN/A 451464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 461464SN/A#define __CPU_BASE_DYN_INST_HH__ 471060SN/A 482731Sktlim@umich.edu#include <bitset> 492292SN/A#include <list> 501464SN/A#include <string> 511060SN/A 522669Sktlim@umich.edu#include "arch/faults.hh" 537720Sgblack@eecs.umich.edu#include "arch/utility.hh" 541060SN/A#include "base/fast_alloc.hh" 551060SN/A#include "base/trace.hh" 561858SN/A#include "config/full_system.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 583770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 591464SN/A#include "cpu/exetrace.hh" 601464SN/A#include "cpu/inst_seq.hh" 612669Sktlim@umich.edu#include "cpu/op_class.hh" 621060SN/A#include "cpu/static_inst.hh" 636973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 642669Sktlim@umich.edu#include "mem/packet.hh" 657678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 662292SN/A#include "sim/system.hh" 676023Snate@binkert.org#include "sim/tlb.hh" 681060SN/A 691060SN/A/** 701060SN/A * @file 711060SN/A * Defines a dynamic instruction context. 721060SN/A */ 731060SN/A 741061SN/A// Forward declaration. 751061SN/Aclass StaticInstPtr; 761060SN/A 771060SN/Atemplate <class Impl> 781061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 791060SN/A{ 801060SN/A public: 811060SN/A // Typedef for the CPU. 822733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 832733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 841060SN/A 852292SN/A // Logical register index type. 862107SN/A typedef TheISA::RegIndex RegIndex; 872690Sktlim@umich.edu // Integer register type. 882107SN/A typedef TheISA::IntReg IntReg; 892690Sktlim@umich.edu // Floating point register type. 902690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 911060SN/A 922292SN/A // The DynInstPtr type. 932292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 948486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 952292SN/A 962292SN/A // The list of instructions iterator type. 972292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 982292SN/A 991060SN/A enum { 1005543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 1015543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 1021060SN/A }; 1031060SN/A 1042292SN/A /** The StaticInst used by this BaseDynInst. */ 1052107SN/A StaticInstPtr staticInst; 1061060SN/A 1071060SN/A //////////////////////////////////////////// 1081060SN/A // 1091060SN/A // INSTRUCTION EXECUTION 1101060SN/A // 1111060SN/A //////////////////////////////////////////// 1122292SN/A /** InstRecord that tracks this instructions. */ 1131060SN/A Trace::InstRecord *traceData; 1141060SN/A 1155358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1165358Sgblack@eecs.umich.edu { 1175358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1185358Sgblack@eecs.umich.edu } 1195358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1205358Sgblack@eecs.umich.edu { 1215358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1225358Sgblack@eecs.umich.edu } 1235358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1245358Sgblack@eecs.umich.edu { 1255358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1265358Sgblack@eecs.umich.edu } 1275358Sgblack@eecs.umich.edu 1288444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1297520Sgblack@eecs.umich.edu 1308444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 1318444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1327520Sgblack@eecs.umich.edu 1336974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1346974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1356974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1366974Stjones1@inf.ed.ac.uk 1376973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1386974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1396974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1406973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1416973Stjones1@inf.ed.ac.uk 1426973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1436973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1441060SN/A 1457944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 1467944SGiacomo.Gabrielli@arm.com bool translationStarted; 1477944SGiacomo.Gabrielli@arm.com 1487944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 1497944SGiacomo.Gabrielli@arm.com bool translationCompleted; 1507944SGiacomo.Gabrielli@arm.com 1517944SGiacomo.Gabrielli@arm.com /** 1527944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 1537944SGiacomo.Gabrielli@arm.com * page table walk. 1547944SGiacomo.Gabrielli@arm.com */ 1557944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 1567944SGiacomo.Gabrielli@arm.com { 1577944SGiacomo.Gabrielli@arm.com return (translationStarted && !translationCompleted); 1587944SGiacomo.Gabrielli@arm.com } 1597944SGiacomo.Gabrielli@arm.com 1607944SGiacomo.Gabrielli@arm.com /** 1617944SGiacomo.Gabrielli@arm.com * Saved memory requests (needed when the DTB address translation is 1627944SGiacomo.Gabrielli@arm.com * delayed due to a hw page table walk). 1637944SGiacomo.Gabrielli@arm.com */ 1647944SGiacomo.Gabrielli@arm.com RequestPtr savedReq; 1657944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqLow; 1667944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqHigh; 1677944SGiacomo.Gabrielli@arm.com 1681684SN/A /** @todo: Consider making this private. */ 1691060SN/A public: 1701060SN/A /** The sequence number of the instruction. */ 1711060SN/A InstSeqNum seqNum; 1721060SN/A 1732731Sktlim@umich.edu enum Status { 1742731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1752731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1762731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1772731Sktlim@umich.edu Completed, /// Instruction has completed 1782731Sktlim@umich.edu ResultReady, /// Instruction has its result 1792731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1802731Sktlim@umich.edu Issued, /// Instruction has issued 1812731Sktlim@umich.edu Executed, /// Instruction has executed 1822731Sktlim@umich.edu CanCommit, /// Instruction can commit 1832731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1842731Sktlim@umich.edu Committed, /// Instruction has committed 1852731Sktlim@umich.edu Squashed, /// Instruction is squashed 1862731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1872731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1882731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1892731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1902731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1912731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1922731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1932731Sktlim@umich.edu /// instructions ahead of it 1942731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1952731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1962731Sktlim@umich.edu NumStatus 1972731Sktlim@umich.edu }; 1982292SN/A 1992731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 2002731Sktlim@umich.edu std::bitset<NumStatus> status; 2011060SN/A 2021060SN/A /** The thread this instruction is from. */ 2036221Snate@binkert.org ThreadID threadNumber; 2041060SN/A 2051060SN/A /** data address space ID, for loads & stores. */ 2061060SN/A short asid; 2071060SN/A 2082292SN/A /** How many source registers are ready. */ 2092292SN/A unsigned readyRegs; 2102292SN/A 2112733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2122733Sktlim@umich.edu ImplCPU *cpu; 2131060SN/A 2142680Sktlim@umich.edu /** Pointer to the thread state. */ 2152292SN/A ImplState *thread; 2161060SN/A 2171060SN/A /** The kind of fault this instruction has generated. */ 2182132SN/A Fault fault; 2191060SN/A 2202702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2212669Sktlim@umich.edu uint8_t *memData; 2222292SN/A 2231060SN/A /** The effective virtual address (lds & stores only). */ 2241060SN/A Addr effAddr; 2251060SN/A 2268199SAli.Saidi@ARM.com /** The size of the request */ 2278199SAli.Saidi@ARM.com Addr effSize; 2288199SAli.Saidi@ARM.com 2294032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2304032Sktlim@umich.edu bool effAddrValid; 2314032Sktlim@umich.edu 2321060SN/A /** The effective physical address. */ 2331060SN/A Addr physEffAddr; 2341060SN/A 2351060SN/A /** The memory request flags (from translation). */ 2361060SN/A unsigned memReqFlags; 2371060SN/A 2381464SN/A union Result { 2391464SN/A uint64_t integer; 2402356SN/A// float fp; 2411464SN/A double dbl; 2421464SN/A }; 2431060SN/A 2441464SN/A /** The result of the instruction; assumes for now that there's only one 2451464SN/A * destination register. 2461464SN/A */ 2471464SN/A Result instResult; 2481060SN/A 2493326Sktlim@umich.edu /** Records changes to result? */ 2503326Sktlim@umich.edu bool recordResult; 2513326Sktlim@umich.edu 2527597Sminkyu.jeong@arm.com /** Did this instruction execute, or is it predicated false */ 2537597Sminkyu.jeong@arm.com bool predicate; 2547597Sminkyu.jeong@arm.com 2553965Sgblack@eecs.umich.edu protected: 2567720Sgblack@eecs.umich.edu /** PC state for this instruction. */ 2577720Sgblack@eecs.umich.edu TheISA::PCState pc; 2581060SN/A 2597720Sgblack@eecs.umich.edu /** Predicted PC state after this instruction. */ 2607720Sgblack@eecs.umich.edu TheISA::PCState predPC; 2614636Sgblack@eecs.umich.edu 2623794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2633794Sgblack@eecs.umich.edu bool predTaken; 2643794Sgblack@eecs.umich.edu 2653965Sgblack@eecs.umich.edu public: 2663965Sgblack@eecs.umich.edu 2672292SN/A#ifdef DEBUG 2682292SN/A void dumpSNList(); 2692292SN/A#endif 2702292SN/A 2712292SN/A /** Whether or not the source register is ready. 2722292SN/A * @todo: Not sure this should be here vs the derived class. 2731060SN/A */ 2741060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2751060SN/A 2763770Sgblack@eecs.umich.edu protected: 2773770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2783770Sgblack@eecs.umich.edu * instruction. 2793770Sgblack@eecs.umich.edu */ 2803770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2813770Sgblack@eecs.umich.edu 2823770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2833770Sgblack@eecs.umich.edu * instruction. 2843770Sgblack@eecs.umich.edu */ 2853770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2863770Sgblack@eecs.umich.edu 2873770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2883770Sgblack@eecs.umich.edu * instruction. 2893770Sgblack@eecs.umich.edu */ 2903770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2913770Sgblack@eecs.umich.edu 2923770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2933770Sgblack@eecs.umich.edu * instruction. 2943770Sgblack@eecs.umich.edu */ 2953770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2963770Sgblack@eecs.umich.edu 2973770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2983770Sgblack@eecs.umich.edu * architected destinations. 2993770Sgblack@eecs.umich.edu */ 3003770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3013770Sgblack@eecs.umich.edu 3021060SN/A public: 3033770Sgblack@eecs.umich.edu 3043770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3053770Sgblack@eecs.umich.edu * register. 3063770Sgblack@eecs.umich.edu */ 3073770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3083770Sgblack@eecs.umich.edu { 3093770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3103770Sgblack@eecs.umich.edu } 3113770Sgblack@eecs.umich.edu 3123770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3133770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3143770Sgblack@eecs.umich.edu { 3153770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3163770Sgblack@eecs.umich.edu } 3173770Sgblack@eecs.umich.edu 3183770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3193770Sgblack@eecs.umich.edu * register. 3203770Sgblack@eecs.umich.edu */ 3213770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3223770Sgblack@eecs.umich.edu { 3233770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3243770Sgblack@eecs.umich.edu } 3253770Sgblack@eecs.umich.edu 3263770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3273770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3283770Sgblack@eecs.umich.edu { 3293770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3303770Sgblack@eecs.umich.edu } 3313770Sgblack@eecs.umich.edu 3323770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3333770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3343770Sgblack@eecs.umich.edu */ 3353770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3363770Sgblack@eecs.umich.edu { 3373770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3383770Sgblack@eecs.umich.edu } 3393770Sgblack@eecs.umich.edu 3403770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3413770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3423770Sgblack@eecs.umich.edu */ 3433770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3443770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3453770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3463770Sgblack@eecs.umich.edu { 3473770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3483770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3493770Sgblack@eecs.umich.edu } 3503770Sgblack@eecs.umich.edu 3513770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3523770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3533770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3543770Sgblack@eecs.umich.edu */ 3553770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3563770Sgblack@eecs.umich.edu { 3573770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3583770Sgblack@eecs.umich.edu } 3593770Sgblack@eecs.umich.edu 3603770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3613770Sgblack@eecs.umich.edu */ 3623770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3633770Sgblack@eecs.umich.edu { 3643770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3653770Sgblack@eecs.umich.edu } 3663770Sgblack@eecs.umich.edu 3673770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3683770Sgblack@eecs.umich.edu * index. 3693770Sgblack@eecs.umich.edu */ 3703770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3713770Sgblack@eecs.umich.edu { 3723770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3733770Sgblack@eecs.umich.edu } 3744636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3754636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3767720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 3777720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 3784636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3794636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3804636Sgblack@eecs.umich.edu */ 3817720Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 3827720Sgblack@eecs.umich.edu TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 3833770Sgblack@eecs.umich.edu 3842292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3852292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3862292SN/A */ 3872107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3881060SN/A 3891060SN/A /** BaseDynInst destructor. */ 3901060SN/A ~BaseDynInst(); 3911060SN/A 3921464SN/A private: 3931684SN/A /** Function to initialize variables in the constructors. */ 3941464SN/A void initVars(); 3951060SN/A 3961464SN/A public: 3971060SN/A /** Dumps out contents of this BaseDynInst. */ 3981060SN/A void dump(); 3991060SN/A 4001060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4011060SN/A void dump(std::string &outstring); 4021060SN/A 4033326Sktlim@umich.edu /** Read this CPU's ID. */ 4045712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4053326Sktlim@umich.edu 4065714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4075714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4085714Shsul@eecs.umich.edu 4091060SN/A /** Returns the fault type. */ 4102132SN/A Fault getFault() { return fault; } 4111060SN/A 4121060SN/A /** Checks whether or not this instruction has had its branch target 4131060SN/A * calculated yet. For now it is not utilized and is hacked to be 4141060SN/A * always false. 4152292SN/A * @todo: Actually use this instruction. 4161060SN/A */ 4171060SN/A bool doneTargCalc() { return false; } 4181060SN/A 4197720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4207720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4213965Sgblack@eecs.umich.edu { 4227720Sgblack@eecs.umich.edu predPC = _predPC; 4233965Sgblack@eecs.umich.edu } 4242935Sksewell@umich.edu 4257720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4261060SN/A 4273794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4287720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4293794Sgblack@eecs.umich.edu 4303794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4317720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4321060SN/A 4334636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4347720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4354636Sgblack@eecs.umich.edu 4361060SN/A /** Returns whether the instruction was predicted taken or not. */ 4373794Sgblack@eecs.umich.edu bool readPredTaken() 4383794Sgblack@eecs.umich.edu { 4393794Sgblack@eecs.umich.edu return predTaken; 4403794Sgblack@eecs.umich.edu } 4413794Sgblack@eecs.umich.edu 4423794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4433794Sgblack@eecs.umich.edu { 4443794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4453794Sgblack@eecs.umich.edu } 4461060SN/A 4471060SN/A /** Returns whether the instruction mispredicted. */ 4482935Sksewell@umich.edu bool mispredicted() 4493794Sgblack@eecs.umich.edu { 4507720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4517720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4527720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4533794Sgblack@eecs.umich.edu } 4543794Sgblack@eecs.umich.edu 4551060SN/A // 4561060SN/A // Instruction types. Forward checks to StaticInst object. 4571060SN/A // 4585543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4595543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4605543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4615543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4622336SN/A bool isStoreConditional() const 4632336SN/A { return staticInst->isStoreConditional(); } 4641060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4651060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4665543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 4675543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 4685543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 4695543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 4705543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 4715543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4721060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4735543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4745543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4752935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4761060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4771060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4782292SN/A bool isSerializeBefore() const 4792731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4802292SN/A bool isSerializeAfter() const 4812731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 4827784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 4831060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 4841060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 4851060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 4862292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 4872336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 4882308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 4894828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 4904654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 4914654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 4924636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 4934654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 4944654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 4954636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 4962292SN/A 4972292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 4982731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 4992292SN/A 5002292SN/A /** Clears the serializeBefore part of this instruction. */ 5012731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5022292SN/A 5032292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5042731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5052292SN/A 5062292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5072731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5082292SN/A 5092292SN/A /** Clears the serializeAfter part of this instruction.*/ 5102731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5112292SN/A 5122292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5132731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5142292SN/A 5152731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5162731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5172292SN/A 5182292SN/A /** Checks if the serialization part of this instruction has been 5192292SN/A * handled. This does not apply to the temporary serializing 5202292SN/A * state; it only applies to this instruction's own permanent 5212292SN/A * serializing state. 5222292SN/A */ 5232731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5241060SN/A 5251464SN/A /** Returns the opclass of this instruction. */ 5261464SN/A OpClass opClass() const { return staticInst->opClass(); } 5271464SN/A 5281464SN/A /** Returns the branch target address. */ 5297720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5307720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5311464SN/A 5322292SN/A /** Returns the number of source registers. */ 5335543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5341684SN/A 5352292SN/A /** Returns the number of destination registers. */ 5361060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5371060SN/A 5381060SN/A // the following are used to track physical register usage 5391060SN/A // for machines with separate int & FP reg files 5401060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5411060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5421060SN/A 5431060SN/A /** Returns the logical register index of the i'th destination register. */ 5442292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5451060SN/A 5461060SN/A /** Returns the logical register index of the i'th source register. */ 5472292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5481060SN/A 5491684SN/A /** Returns the result of an integer instruction. */ 5501464SN/A uint64_t readIntResult() { return instResult.integer; } 5511684SN/A 5521684SN/A /** Returns the result of a floating point instruction. */ 5532356SN/A float readFloatResult() { return (float)instResult.dbl; } 5541684SN/A 5551684SN/A /** Returns the result of a floating point (double) instruction. */ 5561464SN/A double readDoubleResult() { return instResult.dbl; } 5571060SN/A 5582702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5593735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5601060SN/A { 5613326Sktlim@umich.edu if (recordResult) 5623326Sktlim@umich.edu instResult.integer = val; 5631060SN/A } 5641060SN/A 5652702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5663735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5673735Sstever@eecs.umich.edu int width) 5682690Sktlim@umich.edu { 5693326Sktlim@umich.edu if (recordResult) { 5703326Sktlim@umich.edu if (width == 32) 5713326Sktlim@umich.edu instResult.dbl = (double)val; 5723326Sktlim@umich.edu else if (width == 64) 5733326Sktlim@umich.edu instResult.dbl = val; 5743326Sktlim@umich.edu else 5753326Sktlim@umich.edu panic("Unsupported width!"); 5763326Sktlim@umich.edu } 5772690Sktlim@umich.edu } 5782690Sktlim@umich.edu 5792702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5803735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5811060SN/A { 5823326Sktlim@umich.edu if (recordResult) 5833326Sktlim@umich.edu instResult.dbl = (double)val; 5842308SN/A } 5851060SN/A 5862702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5873735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 5883735Sstever@eecs.umich.edu int width) 5892308SN/A { 5903326Sktlim@umich.edu if (recordResult) 5913326Sktlim@umich.edu instResult.integer = val; 5922308SN/A } 5931060SN/A 5942702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5953735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 5962308SN/A { 5973326Sktlim@umich.edu if (recordResult) 5983326Sktlim@umich.edu instResult.integer = val; 5991060SN/A } 6001060SN/A 6012190SN/A /** Records that one of the source registers is ready. */ 6022292SN/A void markSrcRegReady(); 6032190SN/A 6042331SN/A /** Marks a specific register as ready. */ 6052292SN/A void markSrcRegReady(RegIndex src_idx); 6062190SN/A 6071684SN/A /** Returns if a source register is ready. */ 6081464SN/A bool isReadySrcRegIdx(int idx) const 6091464SN/A { 6101464SN/A return this->_readySrcRegIdx[idx]; 6111464SN/A } 6121464SN/A 6131684SN/A /** Sets this instruction as completed. */ 6142731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6151464SN/A 6162292SN/A /** Returns whether or not this instruction is completed. */ 6172731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6181464SN/A 6192731Sktlim@umich.edu /** Marks the result as ready. */ 6202731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6212308SN/A 6222731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6232731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6242308SN/A 6251060SN/A /** Sets this instruction as ready to issue. */ 6262731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6271060SN/A 6281060SN/A /** Returns whether or not this instruction is ready to issue. */ 6292731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6301060SN/A 6314032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6324032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6334032Sktlim@umich.edu 6341060SN/A /** Sets this instruction as issued from the IQ. */ 6352731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6361060SN/A 6371060SN/A /** Returns whether or not this instruction has issued. */ 6382731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6391060SN/A 6404032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6414032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6424032Sktlim@umich.edu 6431060SN/A /** Sets this instruction as executed. */ 6442731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6451060SN/A 6461060SN/A /** Returns whether or not this instruction has executed. */ 6472731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6481060SN/A 6491060SN/A /** Sets this instruction as ready to commit. */ 6502731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6511060SN/A 6521061SN/A /** Clears this instruction as being ready to commit. */ 6532731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6541061SN/A 6551060SN/A /** Returns whether or not this instruction is ready to commit. */ 6562731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6572731Sktlim@umich.edu 6582731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6592731Sktlim@umich.edu 6602731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6611060SN/A 6622292SN/A /** Sets this instruction as committed. */ 6632731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6642292SN/A 6652292SN/A /** Returns whether or not this instruction is committed. */ 6662731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6672292SN/A 6681060SN/A /** Sets this instruction as squashed. */ 6692731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6701060SN/A 6711060SN/A /** Returns whether or not this instruction is squashed. */ 6722731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6731060SN/A 6742292SN/A //Instruction Queue Entry 6752292SN/A //----------------------- 6762292SN/A /** Sets this instruction as a entry the IQ. */ 6772731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6782292SN/A 6792292SN/A /** Sets this instruction as a entry the IQ. */ 6802731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6812731Sktlim@umich.edu 6822731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 6832731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 6842292SN/A 6851060SN/A /** Sets this instruction as squashed in the IQ. */ 6862731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 6871060SN/A 6881060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 6892731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 6902292SN/A 6912292SN/A 6922292SN/A //Load / Store Queue Functions 6932292SN/A //----------------------- 6942292SN/A /** Sets this instruction as a entry the LSQ. */ 6952731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 6962292SN/A 6972292SN/A /** Sets this instruction as a entry the LSQ. */ 6982731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 6992731Sktlim@umich.edu 7002731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7012731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7022292SN/A 7032292SN/A /** Sets this instruction as squashed in the LSQ. */ 7042731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7052292SN/A 7062292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7072731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7082292SN/A 7092292SN/A 7102292SN/A //Reorder Buffer Functions 7112292SN/A //----------------------- 7122292SN/A /** Sets this instruction as a entry the ROB. */ 7132731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7142292SN/A 7152292SN/A /** Sets this instruction as a entry the ROB. */ 7162731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7172731Sktlim@umich.edu 7182731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7192731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7202292SN/A 7212292SN/A /** Sets this instruction as squashed in the ROB. */ 7222731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7232292SN/A 7242292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7252731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7262292SN/A 7277720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 7287720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 7297720Sgblack@eecs.umich.edu 7307720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 7317720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 7327720Sgblack@eecs.umich.edu 7331060SN/A /** Read the PC of this instruction. */ 7347720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 7357720Sgblack@eecs.umich.edu 7367720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 7377720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 7381060SN/A 7394636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7407720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 7414636Sgblack@eecs.umich.edu 7427597Sminkyu.jeong@arm.com bool readPredicate() 7437597Sminkyu.jeong@arm.com { 7447597Sminkyu.jeong@arm.com return predicate; 7457597Sminkyu.jeong@arm.com } 7467597Sminkyu.jeong@arm.com 7477597Sminkyu.jeong@arm.com void setPredicate(bool val) 7487597Sminkyu.jeong@arm.com { 7497597Sminkyu.jeong@arm.com predicate = val; 7507600Sminkyu.jeong@arm.com 7517600Sminkyu.jeong@arm.com if (traceData) { 7527600Sminkyu.jeong@arm.com traceData->setPredicate(val); 7537600Sminkyu.jeong@arm.com } 7547597Sminkyu.jeong@arm.com } 7557597Sminkyu.jeong@arm.com 7562702Sktlim@umich.edu /** Sets the ASID. */ 7572292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7582292SN/A 7592702Sktlim@umich.edu /** Sets the thread id. */ 7606221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 7612292SN/A 7622731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7632702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7641060SN/A 7652731Sktlim@umich.edu /** Returns the thread context. */ 7662680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7671464SN/A 7681464SN/A private: 7691684SN/A /** Instruction effective address. 7701684SN/A * @todo: Consider if this is necessary or not. 7711684SN/A */ 7721464SN/A Addr instEffAddr; 7732292SN/A 7741684SN/A /** Whether or not the effective address calculation is completed. 7751684SN/A * @todo: Consider if this is necessary or not. 7761684SN/A */ 7771464SN/A bool eaCalcDone; 7781464SN/A 7794032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7804032Sktlim@umich.edu bool isUncacheable; 7814032Sktlim@umich.edu 7824032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7834032Sktlim@umich.edu bool reqMade; 7844032Sktlim@umich.edu 7851464SN/A public: 7861684SN/A /** Sets the effective address. */ 7871464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 7881684SN/A 7891684SN/A /** Returns the effective address. */ 7901464SN/A const Addr &getEA() const { return instEffAddr; } 7911684SN/A 7921684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 7931464SN/A bool doneEACalc() { return eaCalcDone; } 7941684SN/A 7951684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 7961464SN/A bool eaSrcsReady(); 7971681SN/A 7982292SN/A /** Whether or not the memory operation is done. */ 7992292SN/A bool memOpDone; 8002292SN/A 8014032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8024032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8034032Sktlim@umich.edu 8044032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8054032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8064032Sktlim@umich.edu 8071681SN/A public: 8081684SN/A /** Load queue index. */ 8091681SN/A int16_t lqIdx; 8101684SN/A 8111684SN/A /** Store queue index. */ 8121681SN/A int16_t sqIdx; 8132292SN/A 8142292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8152292SN/A ListIt instListIt; 8162292SN/A 8172292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8182292SN/A ListIt &getInstListIt() { return instListIt; } 8192292SN/A 8202292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8212292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8223326Sktlim@umich.edu 8233326Sktlim@umich.edu public: 8243326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8253326Sktlim@umich.edu unsigned readStCondFailures() 8263326Sktlim@umich.edu { return thread->storeCondFailures; } 8273326Sktlim@umich.edu 8283326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8293326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8303326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8311060SN/A}; 8321060SN/A 8331060SN/Atemplate<class Impl> 8347520Sgblack@eecs.umich.eduFault 8358444Sgblack@eecs.umich.eduBaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 8368444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8371060SN/A{ 8384032Sktlim@umich.edu reqMade = true; 8397944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8406974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8416974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8426974Stjones1@inf.ed.ac.uk 8437944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 8447944SGiacomo.Gabrielli@arm.com req = savedReq; 8457944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8467944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8477944SGiacomo.Gabrielli@arm.com } else { 8487944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 8497944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8504032Sktlim@umich.edu 8517944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 8527944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 8537944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 8547944SGiacomo.Gabrielli@arm.com } 8557944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8561060SN/A } 8571060SN/A 8587944SGiacomo.Gabrielli@arm.com if (translationCompleted) { 8597944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 8607944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 8618199SAli.Saidi@ARM.com effSize = size; 8627944SGiacomo.Gabrielli@arm.com effAddrValid = true; 8637944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 8647944SGiacomo.Gabrielli@arm.com } else { 8657944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 8667944SGiacomo.Gabrielli@arm.com // instruction as executed. 8677944SGiacomo.Gabrielli@arm.com this->setExecuted(); 8687944SGiacomo.Gabrielli@arm.com } 8697944SGiacomo.Gabrielli@arm.com 8707944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 8717944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 8727944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 8737944SGiacomo.Gabrielli@arm.com if (data) 8747944SGiacomo.Gabrielli@arm.com bzero(data, size); 8757944SGiacomo.Gabrielli@arm.com } 8767577SAli.Saidi@ARM.com } 8777577SAli.Saidi@ARM.com 8781060SN/A if (traceData) { 8791060SN/A traceData->setAddr(addr); 8801060SN/A } 8811060SN/A 8821060SN/A return fault; 8831060SN/A} 8841060SN/A 8851060SN/Atemplate<class Impl> 8867520Sgblack@eecs.umich.eduFault 8878444Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 8888444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 8891060SN/A{ 8901060SN/A if (traceData) { 8911060SN/A traceData->setAddr(addr); 8921060SN/A } 8931060SN/A 8944032Sktlim@umich.edu reqMade = true; 8957944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8966974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8976974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8986974Stjones1@inf.ed.ac.uk 8997944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 9007944SGiacomo.Gabrielli@arm.com req = savedReq; 9017944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9027944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9037944SGiacomo.Gabrielli@arm.com } else { 9047944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 9057944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9067944SGiacomo.Gabrielli@arm.com 9077944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9087944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9097944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9107944SGiacomo.Gabrielli@arm.com } 9117944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9126974Stjones1@inf.ed.ac.uk } 9134032Sktlim@umich.edu 9147944SGiacomo.Gabrielli@arm.com if (fault == NoFault && translationCompleted) { 9152678Sktlim@umich.edu effAddr = req->getVaddr(); 9168199SAli.Saidi@ARM.com effSize = size; 9174032Sktlim@umich.edu effAddrValid = true; 9186975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9191060SN/A } 9201060SN/A 9211060SN/A return fault; 9221060SN/A} 9231060SN/A 9246973Stjones1@inf.ed.ac.uktemplate<class Impl> 9256973Stjones1@inf.ed.ac.ukinline void 9266974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9276974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9286974Stjones1@inf.ed.ac.uk{ 9296974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9306974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9316974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9326974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9336974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9346974Stjones1@inf.ed.ac.uk 9356974Stjones1@inf.ed.ac.uk // Spans two blocks. 9366974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9376974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9386974Stjones1@inf.ed.ac.uk } 9396974Stjones1@inf.ed.ac.uk} 9406974Stjones1@inf.ed.ac.uk 9416974Stjones1@inf.ed.ac.uktemplate<class Impl> 9426974Stjones1@inf.ed.ac.ukinline void 9436974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 9446974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 9456973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 9466973Stjones1@inf.ed.ac.uk{ 9477944SGiacomo.Gabrielli@arm.com translationStarted = true; 9487944SGiacomo.Gabrielli@arm.com 9496974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 9506974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9516974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 9526974Stjones1@inf.ed.ac.uk 9536974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 9548486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 9558486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 9566974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 9577944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 9587944SGiacomo.Gabrielli@arm.com // Save memory requests. 9597944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 9607944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 9617944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 9627944SGiacomo.Gabrielli@arm.com } 9636974Stjones1@inf.ed.ac.uk } else { 9646974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9656974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 9666974Stjones1@inf.ed.ac.uk 9676974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 9688486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 9698486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 9708486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 9718486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 9726974Stjones1@inf.ed.ac.uk 9736974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 9746974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 9757944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 9767944SGiacomo.Gabrielli@arm.com // Save memory requests. 9777944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 9787944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 9797944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 9807944SGiacomo.Gabrielli@arm.com } 9816974Stjones1@inf.ed.ac.uk } 9826973Stjones1@inf.ed.ac.uk} 9836973Stjones1@inf.ed.ac.uk 9846973Stjones1@inf.ed.ac.uktemplate<class Impl> 9856973Stjones1@inf.ed.ac.ukinline void 9866973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 9876973Stjones1@inf.ed.ac.uk{ 9886973Stjones1@inf.ed.ac.uk fault = state->getFault(); 9896973Stjones1@inf.ed.ac.uk 9906973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 9916973Stjones1@inf.ed.ac.uk isUncacheable = true; 9926973Stjones1@inf.ed.ac.uk 9936973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 9946973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 9956973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 9966973Stjones1@inf.ed.ac.uk 9976973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 9986973Stjones1@inf.ed.ac.uk assert(state->res); 9996973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10006973Stjones1@inf.ed.ac.uk } 10016973Stjones1@inf.ed.ac.uk 10026973Stjones1@inf.ed.ac.uk } else { 10036973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10046973Stjones1@inf.ed.ac.uk } 10056973Stjones1@inf.ed.ac.uk delete state; 10067944SGiacomo.Gabrielli@arm.com 10077944SGiacomo.Gabrielli@arm.com translationCompleted = true; 10086973Stjones1@inf.ed.ac.uk} 10096973Stjones1@inf.ed.ac.uk 10101464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1011