base_dyn_inst.hh revision 7720
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 36973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 41060SN/A * All rights reserved. 51060SN/A * 61060SN/A * Redistribution and use in source and binary forms, with or without 71060SN/A * modification, are permitted provided that the following conditions are 81060SN/A * met: redistributions of source code must retain the above copyright 91060SN/A * notice, this list of conditions and the following disclaimer; 101060SN/A * redistributions in binary form must reproduce the above copyright 111060SN/A * notice, this list of conditions and the following disclaimer in the 121060SN/A * documentation and/or other materials provided with the distribution; 131060SN/A * neither the name of the copyright holders nor the names of its 141060SN/A * contributors may be used to endorse or promote products derived from 151060SN/A * this software without specific prior written permission. 161060SN/A * 171060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 306973Stjones1@inf.ed.ac.uk * Timothy M. Jones 311060SN/A */ 321060SN/A 331464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 341464SN/A#define __CPU_BASE_DYN_INST_HH__ 351060SN/A 362731Sktlim@umich.edu#include <bitset> 372292SN/A#include <list> 381464SN/A#include <string> 391060SN/A 402669Sktlim@umich.edu#include "arch/faults.hh" 417720Sgblack@eecs.umich.edu#include "arch/utility.hh" 421060SN/A#include "base/fast_alloc.hh" 431060SN/A#include "base/trace.hh" 441858SN/A#include "config/full_system.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 463770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 471464SN/A#include "cpu/exetrace.hh" 481464SN/A#include "cpu/inst_seq.hh" 492669Sktlim@umich.edu#include "cpu/op_class.hh" 501060SN/A#include "cpu/static_inst.hh" 516973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 522669Sktlim@umich.edu#include "mem/packet.hh" 537678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 542292SN/A#include "sim/system.hh" 556023Snate@binkert.org#include "sim/tlb.hh" 561060SN/A 571060SN/A/** 581060SN/A * @file 591060SN/A * Defines a dynamic instruction context. 601060SN/A */ 611060SN/A 621061SN/A// Forward declaration. 631061SN/Aclass StaticInstPtr; 641060SN/A 651060SN/Atemplate <class Impl> 661061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 671060SN/A{ 681060SN/A public: 691060SN/A // Typedef for the CPU. 702733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 712733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 721060SN/A 732292SN/A // Logical register index type. 742107SN/A typedef TheISA::RegIndex RegIndex; 752690Sktlim@umich.edu // Integer register type. 762107SN/A typedef TheISA::IntReg IntReg; 772690Sktlim@umich.edu // Floating point register type. 782690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 791060SN/A 802292SN/A // The DynInstPtr type. 812292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 822292SN/A 832292SN/A // The list of instructions iterator type. 842292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 852292SN/A 861060SN/A enum { 875543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 885543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 891060SN/A }; 901060SN/A 912292SN/A /** The StaticInst used by this BaseDynInst. */ 922107SN/A StaticInstPtr staticInst; 931060SN/A 941060SN/A //////////////////////////////////////////// 951060SN/A // 961060SN/A // INSTRUCTION EXECUTION 971060SN/A // 981060SN/A //////////////////////////////////////////// 992292SN/A /** InstRecord that tracks this instructions. */ 1001060SN/A Trace::InstRecord *traceData; 1011060SN/A 1025358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1035358Sgblack@eecs.umich.edu { 1045358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1055358Sgblack@eecs.umich.edu } 1065358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1075358Sgblack@eecs.umich.edu { 1085358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1095358Sgblack@eecs.umich.edu } 1105358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1115358Sgblack@eecs.umich.edu { 1125358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1135358Sgblack@eecs.umich.edu } 1145358Sgblack@eecs.umich.edu 1152292SN/A /** 1162292SN/A * Does a read to a given address. 1172292SN/A * @param addr The address to read. 1182292SN/A * @param data The read's data is written into this parameter. 1192292SN/A * @param flags The request's flags. 1202292SN/A * @return Returns any fault due to the read. 1212292SN/A */ 1221060SN/A template <class T> 1232132SN/A Fault read(Addr addr, T &data, unsigned flags); 1241060SN/A 1257520Sgblack@eecs.umich.edu Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1267520Sgblack@eecs.umich.edu 1272292SN/A /** 1282292SN/A * Does a write to a given address. 1292292SN/A * @param data The data to be written. 1302292SN/A * @param addr The address to write to. 1312292SN/A * @param flags The request's flags. 1322292SN/A * @param res The result of the write (for load locked/store conditionals). 1332292SN/A * @return Returns any fault due to the write. 1342292SN/A */ 1351060SN/A template <class T> 1366973Stjones1@inf.ed.ac.uk Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1376973Stjones1@inf.ed.ac.uk 1387520Sgblack@eecs.umich.edu Fault writeBytes(uint8_t *data, unsigned size, 1397520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1407520Sgblack@eecs.umich.edu 1416974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1426974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1436974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1446974Stjones1@inf.ed.ac.uk 1456973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1466974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1476974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1486973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1496973Stjones1@inf.ed.ac.uk 1506973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1516973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1521060SN/A 1531060SN/A void prefetch(Addr addr, unsigned flags); 1541060SN/A void writeHint(Addr addr, int size, unsigned flags); 1552132SN/A Fault copySrcTranslate(Addr src); 1562132SN/A Fault copy(Addr dest); 1571060SN/A 1581684SN/A /** @todo: Consider making this private. */ 1591060SN/A public: 1601060SN/A /** The sequence number of the instruction. */ 1611060SN/A InstSeqNum seqNum; 1621060SN/A 1632731Sktlim@umich.edu enum Status { 1642731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1652731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1662731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1672731Sktlim@umich.edu Completed, /// Instruction has completed 1682731Sktlim@umich.edu ResultReady, /// Instruction has its result 1692731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1702731Sktlim@umich.edu Issued, /// Instruction has issued 1712731Sktlim@umich.edu Executed, /// Instruction has executed 1722731Sktlim@umich.edu CanCommit, /// Instruction can commit 1732731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1742731Sktlim@umich.edu Committed, /// Instruction has committed 1752731Sktlim@umich.edu Squashed, /// Instruction is squashed 1762731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1772731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1782731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1792731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1802731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1812731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1822731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1832731Sktlim@umich.edu /// instructions ahead of it 1842731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1852731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1862731Sktlim@umich.edu NumStatus 1872731Sktlim@umich.edu }; 1882292SN/A 1892731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1902731Sktlim@umich.edu std::bitset<NumStatus> status; 1911060SN/A 1921060SN/A /** The thread this instruction is from. */ 1936221Snate@binkert.org ThreadID threadNumber; 1941060SN/A 1951060SN/A /** data address space ID, for loads & stores. */ 1961060SN/A short asid; 1971060SN/A 1982292SN/A /** How many source registers are ready. */ 1992292SN/A unsigned readyRegs; 2002292SN/A 2012733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2022733Sktlim@umich.edu ImplCPU *cpu; 2031060SN/A 2042680Sktlim@umich.edu /** Pointer to the thread state. */ 2052292SN/A ImplState *thread; 2061060SN/A 2071060SN/A /** The kind of fault this instruction has generated. */ 2082132SN/A Fault fault; 2091060SN/A 2102702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2112669Sktlim@umich.edu uint8_t *memData; 2122292SN/A 2131060SN/A /** The effective virtual address (lds & stores only). */ 2141060SN/A Addr effAddr; 2151060SN/A 2164032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2174032Sktlim@umich.edu bool effAddrValid; 2184032Sktlim@umich.edu 2191060SN/A /** The effective physical address. */ 2201060SN/A Addr physEffAddr; 2211060SN/A 2221060SN/A /** Effective virtual address for a copy source. */ 2231060SN/A Addr copySrcEffAddr; 2241060SN/A 2251060SN/A /** Effective physical address for a copy source. */ 2261060SN/A Addr copySrcPhysEffAddr; 2271060SN/A 2281060SN/A /** The memory request flags (from translation). */ 2291060SN/A unsigned memReqFlags; 2301060SN/A 2311464SN/A union Result { 2321464SN/A uint64_t integer; 2332356SN/A// float fp; 2341464SN/A double dbl; 2351464SN/A }; 2361060SN/A 2371464SN/A /** The result of the instruction; assumes for now that there's only one 2381464SN/A * destination register. 2391464SN/A */ 2401464SN/A Result instResult; 2411060SN/A 2423326Sktlim@umich.edu /** Records changes to result? */ 2433326Sktlim@umich.edu bool recordResult; 2443326Sktlim@umich.edu 2457597Sminkyu.jeong@arm.com /** Did this instruction execute, or is it predicated false */ 2467597Sminkyu.jeong@arm.com bool predicate; 2477597Sminkyu.jeong@arm.com 2483965Sgblack@eecs.umich.edu protected: 2497720Sgblack@eecs.umich.edu /** PC state for this instruction. */ 2507720Sgblack@eecs.umich.edu TheISA::PCState pc; 2511060SN/A 2527720Sgblack@eecs.umich.edu /** Predicted PC state after this instruction. */ 2537720Sgblack@eecs.umich.edu TheISA::PCState predPC; 2544636Sgblack@eecs.umich.edu 2553794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2563794Sgblack@eecs.umich.edu bool predTaken; 2573794Sgblack@eecs.umich.edu 2583965Sgblack@eecs.umich.edu public: 2593965Sgblack@eecs.umich.edu 2602292SN/A#ifdef DEBUG 2612292SN/A void dumpSNList(); 2622292SN/A#endif 2632292SN/A 2642292SN/A /** Whether or not the source register is ready. 2652292SN/A * @todo: Not sure this should be here vs the derived class. 2661060SN/A */ 2671060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2681060SN/A 2693770Sgblack@eecs.umich.edu protected: 2703770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2713770Sgblack@eecs.umich.edu * instruction. 2723770Sgblack@eecs.umich.edu */ 2733770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2743770Sgblack@eecs.umich.edu 2753770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2763770Sgblack@eecs.umich.edu * instruction. 2773770Sgblack@eecs.umich.edu */ 2783770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2793770Sgblack@eecs.umich.edu 2803770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2813770Sgblack@eecs.umich.edu * instruction. 2823770Sgblack@eecs.umich.edu */ 2833770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2843770Sgblack@eecs.umich.edu 2853770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2863770Sgblack@eecs.umich.edu * instruction. 2873770Sgblack@eecs.umich.edu */ 2883770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2893770Sgblack@eecs.umich.edu 2903770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2913770Sgblack@eecs.umich.edu * architected destinations. 2923770Sgblack@eecs.umich.edu */ 2933770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2943770Sgblack@eecs.umich.edu 2951060SN/A public: 2963770Sgblack@eecs.umich.edu 2973770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 2983770Sgblack@eecs.umich.edu * register. 2993770Sgblack@eecs.umich.edu */ 3003770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3013770Sgblack@eecs.umich.edu { 3023770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3033770Sgblack@eecs.umich.edu } 3043770Sgblack@eecs.umich.edu 3053770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3063770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3073770Sgblack@eecs.umich.edu { 3083770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3093770Sgblack@eecs.umich.edu } 3103770Sgblack@eecs.umich.edu 3113770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3123770Sgblack@eecs.umich.edu * register. 3133770Sgblack@eecs.umich.edu */ 3143770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3153770Sgblack@eecs.umich.edu { 3163770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3173770Sgblack@eecs.umich.edu } 3183770Sgblack@eecs.umich.edu 3193770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3203770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3213770Sgblack@eecs.umich.edu { 3223770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3233770Sgblack@eecs.umich.edu } 3243770Sgblack@eecs.umich.edu 3253770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3263770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3273770Sgblack@eecs.umich.edu */ 3283770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3293770Sgblack@eecs.umich.edu { 3303770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3313770Sgblack@eecs.umich.edu } 3323770Sgblack@eecs.umich.edu 3333770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3343770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3353770Sgblack@eecs.umich.edu */ 3363770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3373770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3383770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3393770Sgblack@eecs.umich.edu { 3403770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3413770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3423770Sgblack@eecs.umich.edu } 3433770Sgblack@eecs.umich.edu 3443770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3453770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3463770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3473770Sgblack@eecs.umich.edu */ 3483770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3493770Sgblack@eecs.umich.edu { 3503770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3513770Sgblack@eecs.umich.edu } 3523770Sgblack@eecs.umich.edu 3533770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3543770Sgblack@eecs.umich.edu */ 3553770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3563770Sgblack@eecs.umich.edu { 3573770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3583770Sgblack@eecs.umich.edu } 3593770Sgblack@eecs.umich.edu 3603770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3613770Sgblack@eecs.umich.edu * index. 3623770Sgblack@eecs.umich.edu */ 3633770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3643770Sgblack@eecs.umich.edu { 3653770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3663770Sgblack@eecs.umich.edu } 3674636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3684636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3697720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 3707720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 3714636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3724636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3734636Sgblack@eecs.umich.edu */ 3747720Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 3757720Sgblack@eecs.umich.edu TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 3763770Sgblack@eecs.umich.edu 3772292SN/A /** BaseDynInst constructor given a binary instruction. 3782292SN/A * @param inst The binary instruction. 3797720Sgblack@eecs.umich.edu * @param _pc The PC state for the instruction. 3807720Sgblack@eecs.umich.edu * @param _predPC The predicted next PC state for the instruction. 3812292SN/A * @param seq_num The sequence number of the instruction. 3822292SN/A * @param cpu Pointer to the instruction's CPU. 3832292SN/A */ 3847720Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc, 3857720Sgblack@eecs.umich.edu TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 3861060SN/A 3872292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3882292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3892292SN/A */ 3902107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3911060SN/A 3921060SN/A /** BaseDynInst destructor. */ 3931060SN/A ~BaseDynInst(); 3941060SN/A 3951464SN/A private: 3961684SN/A /** Function to initialize variables in the constructors. */ 3971464SN/A void initVars(); 3981060SN/A 3991464SN/A public: 4001060SN/A /** Dumps out contents of this BaseDynInst. */ 4011060SN/A void dump(); 4021060SN/A 4031060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4041060SN/A void dump(std::string &outstring); 4051060SN/A 4063326Sktlim@umich.edu /** Read this CPU's ID. */ 4075712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4083326Sktlim@umich.edu 4095714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4105714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4115714Shsul@eecs.umich.edu 4121060SN/A /** Returns the fault type. */ 4132132SN/A Fault getFault() { return fault; } 4141060SN/A 4151060SN/A /** Checks whether or not this instruction has had its branch target 4161060SN/A * calculated yet. For now it is not utilized and is hacked to be 4171060SN/A * always false. 4182292SN/A * @todo: Actually use this instruction. 4191060SN/A */ 4201060SN/A bool doneTargCalc() { return false; } 4211060SN/A 4227720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4237720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4243965Sgblack@eecs.umich.edu { 4257720Sgblack@eecs.umich.edu predPC = _predPC; 4263965Sgblack@eecs.umich.edu } 4272935Sksewell@umich.edu 4287720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4291060SN/A 4303794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4317720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4323794Sgblack@eecs.umich.edu 4333794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4347720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4351060SN/A 4364636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4377720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4384636Sgblack@eecs.umich.edu 4391060SN/A /** Returns whether the instruction was predicted taken or not. */ 4403794Sgblack@eecs.umich.edu bool readPredTaken() 4413794Sgblack@eecs.umich.edu { 4423794Sgblack@eecs.umich.edu return predTaken; 4433794Sgblack@eecs.umich.edu } 4443794Sgblack@eecs.umich.edu 4453794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4463794Sgblack@eecs.umich.edu { 4473794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4483794Sgblack@eecs.umich.edu } 4491060SN/A 4501060SN/A /** Returns whether the instruction mispredicted. */ 4512935Sksewell@umich.edu bool mispredicted() 4523794Sgblack@eecs.umich.edu { 4537720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4547720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4557720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4563794Sgblack@eecs.umich.edu } 4573794Sgblack@eecs.umich.edu 4581060SN/A // 4591060SN/A // Instruction types. Forward checks to StaticInst object. 4601060SN/A // 4615543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4625543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4635543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4645543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4652336SN/A bool isStoreConditional() const 4662336SN/A { return staticInst->isStoreConditional(); } 4671060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4681060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4691060SN/A bool isCopy() const { return staticInst->isCopy(); } 4705543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 4715543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 4725543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 4735543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 4745543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 4755543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4761060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4775543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4785543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4792935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4801060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4811060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4822292SN/A bool isSerializeBefore() const 4832731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4842292SN/A bool isSerializeAfter() const 4852731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 4861060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 4871060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 4881060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 4892292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 4902336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 4912308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 4924828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 4934654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 4944654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 4954636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 4964654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 4974654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 4984636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 4992292SN/A 5002292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5012731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5022292SN/A 5032292SN/A /** Clears the serializeBefore part of this instruction. */ 5042731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5052292SN/A 5062292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5072731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5082292SN/A 5092292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5102731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5112292SN/A 5122292SN/A /** Clears the serializeAfter part of this instruction.*/ 5132731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5142292SN/A 5152292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5162731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5172292SN/A 5182731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5192731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5202292SN/A 5212292SN/A /** Checks if the serialization part of this instruction has been 5222292SN/A * handled. This does not apply to the temporary serializing 5232292SN/A * state; it only applies to this instruction's own permanent 5242292SN/A * serializing state. 5252292SN/A */ 5262731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5271060SN/A 5281464SN/A /** Returns the opclass of this instruction. */ 5291464SN/A OpClass opClass() const { return staticInst->opClass(); } 5301464SN/A 5311464SN/A /** Returns the branch target address. */ 5327720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5337720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5341464SN/A 5352292SN/A /** Returns the number of source registers. */ 5365543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5371684SN/A 5382292SN/A /** Returns the number of destination registers. */ 5391060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5401060SN/A 5411060SN/A // the following are used to track physical register usage 5421060SN/A // for machines with separate int & FP reg files 5431060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5441060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5451060SN/A 5461060SN/A /** Returns the logical register index of the i'th destination register. */ 5472292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5481060SN/A 5491060SN/A /** Returns the logical register index of the i'th source register. */ 5502292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5511060SN/A 5521684SN/A /** Returns the result of an integer instruction. */ 5531464SN/A uint64_t readIntResult() { return instResult.integer; } 5541684SN/A 5551684SN/A /** Returns the result of a floating point instruction. */ 5562356SN/A float readFloatResult() { return (float)instResult.dbl; } 5571684SN/A 5581684SN/A /** Returns the result of a floating point (double) instruction. */ 5591464SN/A double readDoubleResult() { return instResult.dbl; } 5601060SN/A 5612702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5623735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5631060SN/A { 5643326Sktlim@umich.edu if (recordResult) 5653326Sktlim@umich.edu instResult.integer = val; 5661060SN/A } 5671060SN/A 5682702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5693735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5703735Sstever@eecs.umich.edu int width) 5712690Sktlim@umich.edu { 5723326Sktlim@umich.edu if (recordResult) { 5733326Sktlim@umich.edu if (width == 32) 5743326Sktlim@umich.edu instResult.dbl = (double)val; 5753326Sktlim@umich.edu else if (width == 64) 5763326Sktlim@umich.edu instResult.dbl = val; 5773326Sktlim@umich.edu else 5783326Sktlim@umich.edu panic("Unsupported width!"); 5793326Sktlim@umich.edu } 5802690Sktlim@umich.edu } 5812690Sktlim@umich.edu 5822702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5833735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5841060SN/A { 5853326Sktlim@umich.edu if (recordResult) 5863326Sktlim@umich.edu instResult.dbl = (double)val; 5872308SN/A } 5881060SN/A 5892702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5903735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 5913735Sstever@eecs.umich.edu int width) 5922308SN/A { 5933326Sktlim@umich.edu if (recordResult) 5943326Sktlim@umich.edu instResult.integer = val; 5952308SN/A } 5961060SN/A 5972702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5983735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 5992308SN/A { 6003326Sktlim@umich.edu if (recordResult) 6013326Sktlim@umich.edu instResult.integer = val; 6021060SN/A } 6031060SN/A 6042190SN/A /** Records that one of the source registers is ready. */ 6052292SN/A void markSrcRegReady(); 6062190SN/A 6072331SN/A /** Marks a specific register as ready. */ 6082292SN/A void markSrcRegReady(RegIndex src_idx); 6092190SN/A 6101684SN/A /** Returns if a source register is ready. */ 6111464SN/A bool isReadySrcRegIdx(int idx) const 6121464SN/A { 6131464SN/A return this->_readySrcRegIdx[idx]; 6141464SN/A } 6151464SN/A 6161684SN/A /** Sets this instruction as completed. */ 6172731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6181464SN/A 6192292SN/A /** Returns whether or not this instruction is completed. */ 6202731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6211464SN/A 6222731Sktlim@umich.edu /** Marks the result as ready. */ 6232731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6242308SN/A 6252731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6262731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6272308SN/A 6281060SN/A /** Sets this instruction as ready to issue. */ 6292731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6301060SN/A 6311060SN/A /** Returns whether or not this instruction is ready to issue. */ 6322731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6331060SN/A 6344032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6354032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6364032Sktlim@umich.edu 6371060SN/A /** Sets this instruction as issued from the IQ. */ 6382731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6391060SN/A 6401060SN/A /** Returns whether or not this instruction has issued. */ 6412731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6421060SN/A 6434032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6444032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6454032Sktlim@umich.edu 6461060SN/A /** Sets this instruction as executed. */ 6472731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6481060SN/A 6491060SN/A /** Returns whether or not this instruction has executed. */ 6502731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6511060SN/A 6521060SN/A /** Sets this instruction as ready to commit. */ 6532731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6541060SN/A 6551061SN/A /** Clears this instruction as being ready to commit. */ 6562731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6571061SN/A 6581060SN/A /** Returns whether or not this instruction is ready to commit. */ 6592731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6602731Sktlim@umich.edu 6612731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6622731Sktlim@umich.edu 6632731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6641060SN/A 6652292SN/A /** Sets this instruction as committed. */ 6662731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6672292SN/A 6682292SN/A /** Returns whether or not this instruction is committed. */ 6692731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6702292SN/A 6711060SN/A /** Sets this instruction as squashed. */ 6722731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6731060SN/A 6741060SN/A /** Returns whether or not this instruction is squashed. */ 6752731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6761060SN/A 6772292SN/A //Instruction Queue Entry 6782292SN/A //----------------------- 6792292SN/A /** Sets this instruction as a entry the IQ. */ 6802731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6812292SN/A 6822292SN/A /** Sets this instruction as a entry the IQ. */ 6832731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6842731Sktlim@umich.edu 6852731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 6862731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 6872292SN/A 6881060SN/A /** Sets this instruction as squashed in the IQ. */ 6892731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 6901060SN/A 6911060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 6922731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 6932292SN/A 6942292SN/A 6952292SN/A //Load / Store Queue Functions 6962292SN/A //----------------------- 6972292SN/A /** Sets this instruction as a entry the LSQ. */ 6982731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 6992292SN/A 7002292SN/A /** Sets this instruction as a entry the LSQ. */ 7012731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7022731Sktlim@umich.edu 7032731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7042731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7052292SN/A 7062292SN/A /** Sets this instruction as squashed in the LSQ. */ 7072731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7082292SN/A 7092292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7102731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7112292SN/A 7122292SN/A 7132292SN/A //Reorder Buffer Functions 7142292SN/A //----------------------- 7152292SN/A /** Sets this instruction as a entry the ROB. */ 7162731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7172292SN/A 7182292SN/A /** Sets this instruction as a entry the ROB. */ 7192731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7202731Sktlim@umich.edu 7212731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7222731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7232292SN/A 7242292SN/A /** Sets this instruction as squashed in the ROB. */ 7252731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7262292SN/A 7272292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7282731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7292292SN/A 7307720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 7317720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 7327720Sgblack@eecs.umich.edu 7337720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 7347720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 7357720Sgblack@eecs.umich.edu 7361060SN/A /** Read the PC of this instruction. */ 7377720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 7387720Sgblack@eecs.umich.edu 7397720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 7407720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 7411060SN/A 7424636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7437720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 7444636Sgblack@eecs.umich.edu 7457597Sminkyu.jeong@arm.com bool readPredicate() 7467597Sminkyu.jeong@arm.com { 7477597Sminkyu.jeong@arm.com return predicate; 7487597Sminkyu.jeong@arm.com } 7497597Sminkyu.jeong@arm.com 7507597Sminkyu.jeong@arm.com void setPredicate(bool val) 7517597Sminkyu.jeong@arm.com { 7527597Sminkyu.jeong@arm.com predicate = val; 7537600Sminkyu.jeong@arm.com 7547600Sminkyu.jeong@arm.com if (traceData) { 7557600Sminkyu.jeong@arm.com traceData->setPredicate(val); 7567600Sminkyu.jeong@arm.com } 7577597Sminkyu.jeong@arm.com } 7587597Sminkyu.jeong@arm.com 7592702Sktlim@umich.edu /** Sets the ASID. */ 7602292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7612292SN/A 7622702Sktlim@umich.edu /** Sets the thread id. */ 7636221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 7642292SN/A 7652731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7662702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7671060SN/A 7682731Sktlim@umich.edu /** Returns the thread context. */ 7692680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7701464SN/A 7711464SN/A private: 7721684SN/A /** Instruction effective address. 7731684SN/A * @todo: Consider if this is necessary or not. 7741684SN/A */ 7751464SN/A Addr instEffAddr; 7762292SN/A 7771684SN/A /** Whether or not the effective address calculation is completed. 7781684SN/A * @todo: Consider if this is necessary or not. 7791684SN/A */ 7801464SN/A bool eaCalcDone; 7811464SN/A 7824032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7834032Sktlim@umich.edu bool isUncacheable; 7844032Sktlim@umich.edu 7854032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7864032Sktlim@umich.edu bool reqMade; 7874032Sktlim@umich.edu 7881464SN/A public: 7891684SN/A /** Sets the effective address. */ 7901464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 7911684SN/A 7921684SN/A /** Returns the effective address. */ 7931464SN/A const Addr &getEA() const { return instEffAddr; } 7941684SN/A 7951684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 7961464SN/A bool doneEACalc() { return eaCalcDone; } 7971684SN/A 7981684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 7991464SN/A bool eaSrcsReady(); 8001681SN/A 8012292SN/A /** Whether or not the memory operation is done. */ 8022292SN/A bool memOpDone; 8032292SN/A 8044032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8054032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8064032Sktlim@umich.edu 8074032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8084032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8094032Sktlim@umich.edu 8101681SN/A public: 8111684SN/A /** Load queue index. */ 8121681SN/A int16_t lqIdx; 8131684SN/A 8141684SN/A /** Store queue index. */ 8151681SN/A int16_t sqIdx; 8162292SN/A 8172292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8182292SN/A ListIt instListIt; 8192292SN/A 8202292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8212292SN/A ListIt &getInstListIt() { return instListIt; } 8222292SN/A 8232292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8242292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8253326Sktlim@umich.edu 8263326Sktlim@umich.edu public: 8273326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8283326Sktlim@umich.edu unsigned readStCondFailures() 8293326Sktlim@umich.edu { return thread->storeCondFailures; } 8303326Sktlim@umich.edu 8313326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8323326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8333326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8341060SN/A}; 8351060SN/A 8361060SN/Atemplate<class Impl> 8377520Sgblack@eecs.umich.eduFault 8387520Sgblack@eecs.umich.eduBaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 8397520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8401060SN/A{ 8414032Sktlim@umich.edu reqMade = true; 8427720Sgblack@eecs.umich.edu Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), 8436429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 8442292SN/A 8456974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8466974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8476974Stjones1@inf.ed.ac.uk 8486974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 8496974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 8506974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 8516974Stjones1@inf.ed.ac.uk } 8526974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8534032Sktlim@umich.edu 8542678Sktlim@umich.edu if (fault == NoFault) { 8552678Sktlim@umich.edu effAddr = req->getVaddr(); 8564032Sktlim@umich.edu effAddrValid = true; 8576975Stjones1@inf.ed.ac.uk fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 8586973Stjones1@inf.ed.ac.uk } else { 8592292SN/A // Commit will have to clean up whatever happened. Set this 8602292SN/A // instruction as executed. 8612292SN/A this->setExecuted(); 8621060SN/A } 8631060SN/A 8647577SAli.Saidi@ARM.com if (fault != NoFault) { 8657577SAli.Saidi@ARM.com // Return a fixed value to keep simulation deterministic even 8667577SAli.Saidi@ARM.com // along misspeculated paths. 8677577SAli.Saidi@ARM.com bzero(data, size); 8687577SAli.Saidi@ARM.com } 8697577SAli.Saidi@ARM.com 8701060SN/A if (traceData) { 8711060SN/A traceData->setAddr(addr); 8721060SN/A } 8731060SN/A 8741060SN/A return fault; 8751060SN/A} 8761060SN/A 8771060SN/Atemplate<class Impl> 8781060SN/Atemplate<class T> 8792132SN/Ainline Fault 8807520Sgblack@eecs.umich.eduBaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 8817520Sgblack@eecs.umich.edu{ 8827520Sgblack@eecs.umich.edu Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 8837520Sgblack@eecs.umich.edu 8847520Sgblack@eecs.umich.edu data = TheISA::gtoh(data); 8857520Sgblack@eecs.umich.edu 8867520Sgblack@eecs.umich.edu if (traceData) { 8877520Sgblack@eecs.umich.edu traceData->setData(data); 8887520Sgblack@eecs.umich.edu } 8897520Sgblack@eecs.umich.edu 8907520Sgblack@eecs.umich.edu return fault; 8917520Sgblack@eecs.umich.edu} 8927520Sgblack@eecs.umich.edu 8937520Sgblack@eecs.umich.edutemplate<class Impl> 8947520Sgblack@eecs.umich.eduFault 8957520Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 8967520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 8971060SN/A{ 8981060SN/A if (traceData) { 8991060SN/A traceData->setAddr(addr); 9001060SN/A } 9011060SN/A 9024032Sktlim@umich.edu reqMade = true; 9037720Sgblack@eecs.umich.edu Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), 9046429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 9051060SN/A 9066974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9076974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9086974Stjones1@inf.ed.ac.uk 9096974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 9106974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 9116974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 9126974Stjones1@inf.ed.ac.uk } 9136974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9144032Sktlim@umich.edu 9152090SN/A if (fault == NoFault) { 9162678Sktlim@umich.edu effAddr = req->getVaddr(); 9174032Sktlim@umich.edu effAddrValid = true; 9186975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9191060SN/A } 9201060SN/A 9211060SN/A return fault; 9221060SN/A} 9231060SN/A 9246973Stjones1@inf.ed.ac.uktemplate<class Impl> 9257520Sgblack@eecs.umich.edutemplate<class T> 9267520Sgblack@eecs.umich.eduinline Fault 9277520Sgblack@eecs.umich.eduBaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9287520Sgblack@eecs.umich.edu{ 9297520Sgblack@eecs.umich.edu if (traceData) { 9307520Sgblack@eecs.umich.edu traceData->setData(data); 9317520Sgblack@eecs.umich.edu } 9327520Sgblack@eecs.umich.edu data = TheISA::htog(data); 9337520Sgblack@eecs.umich.edu return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 9347520Sgblack@eecs.umich.edu} 9357520Sgblack@eecs.umich.edu 9367520Sgblack@eecs.umich.edutemplate<class Impl> 9376973Stjones1@inf.ed.ac.ukinline void 9386974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9396974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9406974Stjones1@inf.ed.ac.uk{ 9416974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9426974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9436974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9446974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9456974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9466974Stjones1@inf.ed.ac.uk 9476974Stjones1@inf.ed.ac.uk // Spans two blocks. 9486974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9496974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9506974Stjones1@inf.ed.ac.uk } 9516974Stjones1@inf.ed.ac.uk} 9526974Stjones1@inf.ed.ac.uk 9536974Stjones1@inf.ed.ac.uktemplate<class Impl> 9546974Stjones1@inf.ed.ac.ukinline void 9556974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 9566974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 9576973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 9586973Stjones1@inf.ed.ac.uk{ 9596974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 9606974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9616974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 9626974Stjones1@inf.ed.ac.uk 9636974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 9646974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *trans = 9656974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state); 9666974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 9676974Stjones1@inf.ed.ac.uk } else { 9686974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9696974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 9706974Stjones1@inf.ed.ac.uk 9716974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 9726974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransLow = 9736974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 9746974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransHigh = 9756974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 9766974Stjones1@inf.ed.ac.uk 9776974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 9786974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 9796974Stjones1@inf.ed.ac.uk } 9806973Stjones1@inf.ed.ac.uk} 9816973Stjones1@inf.ed.ac.uk 9826973Stjones1@inf.ed.ac.uktemplate<class Impl> 9836973Stjones1@inf.ed.ac.ukinline void 9846973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 9856973Stjones1@inf.ed.ac.uk{ 9866973Stjones1@inf.ed.ac.uk fault = state->getFault(); 9876973Stjones1@inf.ed.ac.uk 9886973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 9896973Stjones1@inf.ed.ac.uk isUncacheable = true; 9906973Stjones1@inf.ed.ac.uk 9916973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 9926973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 9936973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 9946973Stjones1@inf.ed.ac.uk 9956973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 9966973Stjones1@inf.ed.ac.uk assert(state->res); 9976973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 9986973Stjones1@inf.ed.ac.uk } 9996973Stjones1@inf.ed.ac.uk 10006973Stjones1@inf.ed.ac.uk } else { 10016973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10026973Stjones1@inf.ed.ac.uk } 10036973Stjones1@inf.ed.ac.uk delete state; 10046973Stjones1@inf.ed.ac.uk} 10056973Stjones1@inf.ed.ac.uk 10061464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1007