base_dyn_inst.hh revision 4828
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321464SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 342731Sktlim@umich.edu#include <bitset> 352292SN/A#include <list> 361464SN/A#include <string> 371060SN/A 382669Sktlim@umich.edu#include "arch/faults.hh" 391060SN/A#include "base/fast_alloc.hh" 401060SN/A#include "base/trace.hh" 411858SN/A#include "config/full_system.hh" 423770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 431464SN/A#include "cpu/exetrace.hh" 441464SN/A#include "cpu/inst_seq.hh" 452669Sktlim@umich.edu#include "cpu/op_class.hh" 461060SN/A#include "cpu/static_inst.hh" 472669Sktlim@umich.edu#include "mem/packet.hh" 482292SN/A#include "sim/system.hh" 491060SN/A 501060SN/A/** 511060SN/A * @file 521060SN/A * Defines a dynamic instruction context. 531060SN/A */ 541060SN/A 551061SN/A// Forward declaration. 561061SN/Aclass StaticInstPtr; 571060SN/A 581060SN/Atemplate <class Impl> 591061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 601060SN/A{ 611060SN/A public: 621060SN/A // Typedef for the CPU. 632733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 642733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 651060SN/A 662292SN/A // Logical register index type. 672107SN/A typedef TheISA::RegIndex RegIndex; 682690Sktlim@umich.edu // Integer register type. 692107SN/A typedef TheISA::IntReg IntReg; 702690Sktlim@umich.edu // Floating point register type. 712690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 721060SN/A 732292SN/A // The DynInstPtr type. 742292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 752292SN/A 762292SN/A // The list of instructions iterator type. 772292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 782292SN/A 791060SN/A enum { 802292SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 812292SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 821060SN/A }; 831060SN/A 842292SN/A /** The StaticInst used by this BaseDynInst. */ 852107SN/A StaticInstPtr staticInst; 861060SN/A 871060SN/A //////////////////////////////////////////// 881060SN/A // 891060SN/A // INSTRUCTION EXECUTION 901060SN/A // 911060SN/A //////////////////////////////////////////// 922292SN/A /** InstRecord that tracks this instructions. */ 931060SN/A Trace::InstRecord *traceData; 941060SN/A 952292SN/A /** 962292SN/A * Does a read to a given address. 972292SN/A * @param addr The address to read. 982292SN/A * @param data The read's data is written into this parameter. 992292SN/A * @param flags The request's flags. 1002292SN/A * @return Returns any fault due to the read. 1012292SN/A */ 1021060SN/A template <class T> 1032132SN/A Fault read(Addr addr, T &data, unsigned flags); 1041060SN/A 1052292SN/A /** 1062292SN/A * Does a write to a given address. 1072292SN/A * @param data The data to be written. 1082292SN/A * @param addr The address to write to. 1092292SN/A * @param flags The request's flags. 1102292SN/A * @param res The result of the write (for load locked/store conditionals). 1112292SN/A * @return Returns any fault due to the write. 1122292SN/A */ 1131060SN/A template <class T> 1142132SN/A Fault write(T data, Addr addr, unsigned flags, 1151060SN/A uint64_t *res); 1161060SN/A 1171060SN/A void prefetch(Addr addr, unsigned flags); 1181060SN/A void writeHint(Addr addr, int size, unsigned flags); 1192132SN/A Fault copySrcTranslate(Addr src); 1202132SN/A Fault copy(Addr dest); 1211060SN/A 1221684SN/A /** @todo: Consider making this private. */ 1231060SN/A public: 1241060SN/A /** The sequence number of the instruction. */ 1251060SN/A InstSeqNum seqNum; 1261060SN/A 1272731Sktlim@umich.edu enum Status { 1282731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1292731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1302731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1312731Sktlim@umich.edu Completed, /// Instruction has completed 1322731Sktlim@umich.edu ResultReady, /// Instruction has its result 1332731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1342731Sktlim@umich.edu Issued, /// Instruction has issued 1352731Sktlim@umich.edu Executed, /// Instruction has executed 1362731Sktlim@umich.edu CanCommit, /// Instruction can commit 1372731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1382731Sktlim@umich.edu Committed, /// Instruction has committed 1392731Sktlim@umich.edu Squashed, /// Instruction is squashed 1402731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1412731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1422731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1432731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1442731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1452731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1462731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1472731Sktlim@umich.edu /// instructions ahead of it 1482731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1492731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1502731Sktlim@umich.edu NumStatus 1512731Sktlim@umich.edu }; 1522292SN/A 1532731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1542731Sktlim@umich.edu std::bitset<NumStatus> status; 1551060SN/A 1561060SN/A /** The thread this instruction is from. */ 1571060SN/A short threadNumber; 1581060SN/A 1591060SN/A /** data address space ID, for loads & stores. */ 1601060SN/A short asid; 1611060SN/A 1622292SN/A /** How many source registers are ready. */ 1632292SN/A unsigned readyRegs; 1642292SN/A 1652733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1662733Sktlim@umich.edu ImplCPU *cpu; 1671060SN/A 1682680Sktlim@umich.edu /** Pointer to the thread state. */ 1692292SN/A ImplState *thread; 1701060SN/A 1711060SN/A /** The kind of fault this instruction has generated. */ 1722132SN/A Fault fault; 1731060SN/A 1742702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 1752669Sktlim@umich.edu uint8_t *memData; 1762292SN/A 1771060SN/A /** The effective virtual address (lds & stores only). */ 1781060SN/A Addr effAddr; 1791060SN/A 1804032Sktlim@umich.edu /** Is the effective virtual address valid. */ 1814032Sktlim@umich.edu bool effAddrValid; 1824032Sktlim@umich.edu 1831060SN/A /** The effective physical address. */ 1841060SN/A Addr physEffAddr; 1851060SN/A 1861060SN/A /** Effective virtual address for a copy source. */ 1871060SN/A Addr copySrcEffAddr; 1881060SN/A 1891060SN/A /** Effective physical address for a copy source. */ 1901060SN/A Addr copySrcPhysEffAddr; 1911060SN/A 1921060SN/A /** The memory request flags (from translation). */ 1931060SN/A unsigned memReqFlags; 1941060SN/A 1951464SN/A union Result { 1961464SN/A uint64_t integer; 1972356SN/A// float fp; 1981464SN/A double dbl; 1991464SN/A }; 2001060SN/A 2011464SN/A /** The result of the instruction; assumes for now that there's only one 2021464SN/A * destination register. 2031464SN/A */ 2041464SN/A Result instResult; 2051060SN/A 2063326Sktlim@umich.edu /** Records changes to result? */ 2073326Sktlim@umich.edu bool recordResult; 2083326Sktlim@umich.edu 2091060SN/A /** PC of this instruction. */ 2101060SN/A Addr PC; 2111060SN/A 2124636Sgblack@eecs.umich.edu /** Micro PC of this instruction. */ 2134636Sgblack@eecs.umich.edu Addr microPC; 2144636Sgblack@eecs.umich.edu 2153965Sgblack@eecs.umich.edu protected: 2161060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2171060SN/A * once the target of the branch is truly known (either decode or 2181060SN/A * execute). 2191060SN/A */ 2201060SN/A Addr nextPC; 2211060SN/A 2222935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2232935Sksewell@umich.edu Addr nextNPC; 2242935Sksewell@umich.edu 2254636Sgblack@eecs.umich.edu /** Next non-speculative micro PC. */ 2264636Sgblack@eecs.umich.edu Addr nextMicroPC; 2274636Sgblack@eecs.umich.edu 2281060SN/A /** Predicted next PC. */ 2291060SN/A Addr predPC; 2301060SN/A 2313794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2323794Sgblack@eecs.umich.edu Addr predNPC; 2333794Sgblack@eecs.umich.edu 2344636Sgblack@eecs.umich.edu /** Predicted next microPC */ 2354636Sgblack@eecs.umich.edu Addr predMicroPC; 2364636Sgblack@eecs.umich.edu 2373794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2383794Sgblack@eecs.umich.edu bool predTaken; 2393794Sgblack@eecs.umich.edu 2403965Sgblack@eecs.umich.edu public: 2413965Sgblack@eecs.umich.edu 2421060SN/A /** Count of total number of dynamic instructions. */ 2431060SN/A static int instcount; 2441060SN/A 2452292SN/A#ifdef DEBUG 2462292SN/A void dumpSNList(); 2472292SN/A#endif 2482292SN/A 2492292SN/A /** Whether or not the source register is ready. 2502292SN/A * @todo: Not sure this should be here vs the derived class. 2511060SN/A */ 2521060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2531060SN/A 2543770Sgblack@eecs.umich.edu protected: 2553770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2563770Sgblack@eecs.umich.edu * instruction. 2573770Sgblack@eecs.umich.edu */ 2583770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2593770Sgblack@eecs.umich.edu 2603770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2613770Sgblack@eecs.umich.edu * instruction. 2623770Sgblack@eecs.umich.edu */ 2633770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2643770Sgblack@eecs.umich.edu 2653770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2663770Sgblack@eecs.umich.edu * instruction. 2673770Sgblack@eecs.umich.edu */ 2683770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2693770Sgblack@eecs.umich.edu 2703770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2713770Sgblack@eecs.umich.edu * instruction. 2723770Sgblack@eecs.umich.edu */ 2733770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2743770Sgblack@eecs.umich.edu 2753770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2763770Sgblack@eecs.umich.edu * architected destinations. 2773770Sgblack@eecs.umich.edu */ 2783770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2793770Sgblack@eecs.umich.edu 2801060SN/A public: 2813770Sgblack@eecs.umich.edu 2823770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 2833770Sgblack@eecs.umich.edu * register. 2843770Sgblack@eecs.umich.edu */ 2853770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 2863770Sgblack@eecs.umich.edu { 2873770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 2883770Sgblack@eecs.umich.edu } 2893770Sgblack@eecs.umich.edu 2903770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 2913770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 2923770Sgblack@eecs.umich.edu { 2933770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 2943770Sgblack@eecs.umich.edu } 2953770Sgblack@eecs.umich.edu 2963770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 2973770Sgblack@eecs.umich.edu * register. 2983770Sgblack@eecs.umich.edu */ 2993770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3003770Sgblack@eecs.umich.edu { 3013770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3023770Sgblack@eecs.umich.edu } 3033770Sgblack@eecs.umich.edu 3043770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3053770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3063770Sgblack@eecs.umich.edu { 3073770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3083770Sgblack@eecs.umich.edu } 3093770Sgblack@eecs.umich.edu 3103770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3113770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3123770Sgblack@eecs.umich.edu */ 3133770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3143770Sgblack@eecs.umich.edu { 3153770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3163770Sgblack@eecs.umich.edu } 3173770Sgblack@eecs.umich.edu 3183770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3193770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3203770Sgblack@eecs.umich.edu */ 3213770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3223770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3233770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3243770Sgblack@eecs.umich.edu { 3253770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3263770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3273770Sgblack@eecs.umich.edu } 3283770Sgblack@eecs.umich.edu 3293770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3303770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3313770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3323770Sgblack@eecs.umich.edu */ 3333770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3343770Sgblack@eecs.umich.edu { 3353770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3363770Sgblack@eecs.umich.edu } 3373770Sgblack@eecs.umich.edu 3383770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3393770Sgblack@eecs.umich.edu */ 3403770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3413770Sgblack@eecs.umich.edu { 3423770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3433770Sgblack@eecs.umich.edu } 3443770Sgblack@eecs.umich.edu 3453770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3463770Sgblack@eecs.umich.edu * index. 3473770Sgblack@eecs.umich.edu */ 3483770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3493770Sgblack@eecs.umich.edu { 3503770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3513770Sgblack@eecs.umich.edu } 3524636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3534636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3544636Sgblack@eecs.umich.edu * @param PC The PC of the instruction. 3554636Sgblack@eecs.umich.edu * @param pred_PC The predicted next PC. 3564636Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3574636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3584636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3594636Sgblack@eecs.umich.edu */ 3604636Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 3614636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3624636Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3633770Sgblack@eecs.umich.edu 3642292SN/A /** BaseDynInst constructor given a binary instruction. 3652292SN/A * @param inst The binary instruction. 3662292SN/A * @param PC The PC of the instruction. 3672292SN/A * @param pred_PC The predicted next PC. 3683794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3692292SN/A * @param seq_num The sequence number of the instruction. 3702292SN/A * @param cpu Pointer to the instruction's CPU. 3712292SN/A */ 3724636Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 3734636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3743770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3751060SN/A 3762292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3772292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3782292SN/A */ 3792107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3801060SN/A 3811060SN/A /** BaseDynInst destructor. */ 3821060SN/A ~BaseDynInst(); 3831060SN/A 3841464SN/A private: 3851684SN/A /** Function to initialize variables in the constructors. */ 3861464SN/A void initVars(); 3871060SN/A 3881464SN/A public: 3891060SN/A /** Dumps out contents of this BaseDynInst. */ 3901060SN/A void dump(); 3911060SN/A 3921060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 3931060SN/A void dump(std::string &outstring); 3941060SN/A 3953326Sktlim@umich.edu /** Read this CPU's ID. */ 3963326Sktlim@umich.edu int readCpuId() { return cpu->readCpuId(); } 3973326Sktlim@umich.edu 3981060SN/A /** Returns the fault type. */ 3992132SN/A Fault getFault() { return fault; } 4001060SN/A 4011060SN/A /** Checks whether or not this instruction has had its branch target 4021060SN/A * calculated yet. For now it is not utilized and is hacked to be 4031060SN/A * always false. 4042292SN/A * @todo: Actually use this instruction. 4051060SN/A */ 4061060SN/A bool doneTargCalc() { return false; } 4071060SN/A 4081684SN/A /** Returns the next PC. This could be the speculative next PC if it is 4091684SN/A * called prior to the actual branch target being calculated. 4101684SN/A */ 4111060SN/A Addr readNextPC() { return nextPC; } 4121060SN/A 4132935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 4142935Sksewell@umich.edu * called prior to the actual branch target being calculated. 4152935Sksewell@umich.edu */ 4163965Sgblack@eecs.umich.edu Addr readNextNPC() 4173965Sgblack@eecs.umich.edu { 4183965Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4193965Sgblack@eecs.umich.edu return nextNPC; 4203965Sgblack@eecs.umich.edu#else 4213965Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 4223965Sgblack@eecs.umich.edu#endif 4233965Sgblack@eecs.umich.edu } 4242935Sksewell@umich.edu 4254636Sgblack@eecs.umich.edu Addr readNextMicroPC() 4264636Sgblack@eecs.umich.edu { 4274636Sgblack@eecs.umich.edu return nextMicroPC; 4284636Sgblack@eecs.umich.edu } 4294636Sgblack@eecs.umich.edu 4301060SN/A /** Set the predicted target of this current instruction. */ 4314636Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 4324636Sgblack@eecs.umich.edu Addr predicted_MicroPC) 4333794Sgblack@eecs.umich.edu { 4343794Sgblack@eecs.umich.edu predPC = predicted_PC; 4353794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4364636Sgblack@eecs.umich.edu predMicroPC = predicted_MicroPC; 4373794Sgblack@eecs.umich.edu } 4381060SN/A 4393794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4403794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4413794Sgblack@eecs.umich.edu 4423794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4433794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4441060SN/A 4454636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4464636Sgblack@eecs.umich.edu Addr readPredMicroPC() { return predMicroPC; } 4474636Sgblack@eecs.umich.edu 4481060SN/A /** Returns whether the instruction was predicted taken or not. */ 4493794Sgblack@eecs.umich.edu bool readPredTaken() 4503794Sgblack@eecs.umich.edu { 4513794Sgblack@eecs.umich.edu return predTaken; 4523794Sgblack@eecs.umich.edu } 4533794Sgblack@eecs.umich.edu 4543794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4553794Sgblack@eecs.umich.edu { 4563794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4573794Sgblack@eecs.umich.edu } 4581060SN/A 4591060SN/A /** Returns whether the instruction mispredicted. */ 4602935Sksewell@umich.edu bool mispredicted() 4613794Sgblack@eecs.umich.edu { 4623965Sgblack@eecs.umich.edu return readPredPC() != readNextPC() || 4634636Sgblack@eecs.umich.edu readPredNPC() != readNextNPC() || 4644636Sgblack@eecs.umich.edu readPredMicroPC() != readNextMicroPC(); 4653794Sgblack@eecs.umich.edu } 4663794Sgblack@eecs.umich.edu 4671060SN/A // 4681060SN/A // Instruction types. Forward checks to StaticInst object. 4691060SN/A // 4701060SN/A bool isNop() const { return staticInst->isNop(); } 4711060SN/A bool isMemRef() const { return staticInst->isMemRef(); } 4721060SN/A bool isLoad() const { return staticInst->isLoad(); } 4731060SN/A bool isStore() const { return staticInst->isStore(); } 4742336SN/A bool isStoreConditional() const 4752336SN/A { return staticInst->isStoreConditional(); } 4761060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4771060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4781060SN/A bool isCopy() const { return staticInst->isCopy(); } 4791060SN/A bool isInteger() const { return staticInst->isInteger(); } 4801060SN/A bool isFloating() const { return staticInst->isFloating(); } 4811060SN/A bool isControl() const { return staticInst->isControl(); } 4821060SN/A bool isCall() const { return staticInst->isCall(); } 4831060SN/A bool isReturn() const { return staticInst->isReturn(); } 4841060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4851060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4861060SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4871060SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4882935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4891060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4901060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4912292SN/A bool isSerializeBefore() const 4922731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4932292SN/A bool isSerializeAfter() const 4942731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 4951060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 4961060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 4971060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 4982292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 4992336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5002308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5014828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5024654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5034654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5044636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5054654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5064654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5074636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5082292SN/A 5092292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5102731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5112292SN/A 5122292SN/A /** Clears the serializeBefore part of this instruction. */ 5132731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5142292SN/A 5152292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5162731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5172292SN/A 5182292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5192731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5202292SN/A 5212292SN/A /** Clears the serializeAfter part of this instruction.*/ 5222731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5232292SN/A 5242292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5252731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5262292SN/A 5272731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5282731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5292292SN/A 5302292SN/A /** Checks if the serialization part of this instruction has been 5312292SN/A * handled. This does not apply to the temporary serializing 5322292SN/A * state; it only applies to this instruction's own permanent 5332292SN/A * serializing state. 5342292SN/A */ 5352731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5361060SN/A 5371464SN/A /** Returns the opclass of this instruction. */ 5381464SN/A OpClass opClass() const { return staticInst->opClass(); } 5391464SN/A 5401464SN/A /** Returns the branch target address. */ 5411464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 5421464SN/A 5432292SN/A /** Returns the number of source registers. */ 5442292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5451684SN/A 5462292SN/A /** Returns the number of destination registers. */ 5471060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5481060SN/A 5491060SN/A // the following are used to track physical register usage 5501060SN/A // for machines with separate int & FP reg files 5511060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5521060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5531060SN/A 5541060SN/A /** Returns the logical register index of the i'th destination register. */ 5552292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5561060SN/A 5571060SN/A /** Returns the logical register index of the i'th source register. */ 5582292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5591060SN/A 5601684SN/A /** Returns the result of an integer instruction. */ 5611464SN/A uint64_t readIntResult() { return instResult.integer; } 5621684SN/A 5631684SN/A /** Returns the result of a floating point instruction. */ 5642356SN/A float readFloatResult() { return (float)instResult.dbl; } 5651684SN/A 5661684SN/A /** Returns the result of a floating point (double) instruction. */ 5671464SN/A double readDoubleResult() { return instResult.dbl; } 5681060SN/A 5692702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5703735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5711060SN/A { 5723326Sktlim@umich.edu if (recordResult) 5733326Sktlim@umich.edu instResult.integer = val; 5741060SN/A } 5751060SN/A 5762702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5773735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5783735Sstever@eecs.umich.edu int width) 5792690Sktlim@umich.edu { 5803326Sktlim@umich.edu if (recordResult) { 5813326Sktlim@umich.edu if (width == 32) 5823326Sktlim@umich.edu instResult.dbl = (double)val; 5833326Sktlim@umich.edu else if (width == 64) 5843326Sktlim@umich.edu instResult.dbl = val; 5853326Sktlim@umich.edu else 5863326Sktlim@umich.edu panic("Unsupported width!"); 5873326Sktlim@umich.edu } 5882690Sktlim@umich.edu } 5892690Sktlim@umich.edu 5902702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5913735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5921060SN/A { 5933326Sktlim@umich.edu if (recordResult) 5943326Sktlim@umich.edu instResult.dbl = (double)val; 5952308SN/A } 5961060SN/A 5972702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5983735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 5993735Sstever@eecs.umich.edu int width) 6002308SN/A { 6013326Sktlim@umich.edu if (recordResult) 6023326Sktlim@umich.edu instResult.integer = val; 6032308SN/A } 6041060SN/A 6052702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6063735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6072308SN/A { 6083326Sktlim@umich.edu if (recordResult) 6093326Sktlim@umich.edu instResult.integer = val; 6101060SN/A } 6111060SN/A 6122190SN/A /** Records that one of the source registers is ready. */ 6132292SN/A void markSrcRegReady(); 6142190SN/A 6152331SN/A /** Marks a specific register as ready. */ 6162292SN/A void markSrcRegReady(RegIndex src_idx); 6172190SN/A 6181684SN/A /** Returns if a source register is ready. */ 6191464SN/A bool isReadySrcRegIdx(int idx) const 6201464SN/A { 6211464SN/A return this->_readySrcRegIdx[idx]; 6221464SN/A } 6231464SN/A 6241684SN/A /** Sets this instruction as completed. */ 6252731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6261464SN/A 6272292SN/A /** Returns whether or not this instruction is completed. */ 6282731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6291464SN/A 6302731Sktlim@umich.edu /** Marks the result as ready. */ 6312731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6322308SN/A 6332731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6342731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6352308SN/A 6361060SN/A /** Sets this instruction as ready to issue. */ 6372731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6381060SN/A 6391060SN/A /** Returns whether or not this instruction is ready to issue. */ 6402731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6411060SN/A 6424032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6434032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6444032Sktlim@umich.edu 6451060SN/A /** Sets this instruction as issued from the IQ. */ 6462731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6471060SN/A 6481060SN/A /** Returns whether or not this instruction has issued. */ 6492731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6501060SN/A 6514032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6524032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6534032Sktlim@umich.edu 6541060SN/A /** Sets this instruction as executed. */ 6552731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6561060SN/A 6571060SN/A /** Returns whether or not this instruction has executed. */ 6582731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6591060SN/A 6601060SN/A /** Sets this instruction as ready to commit. */ 6612731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6621060SN/A 6631061SN/A /** Clears this instruction as being ready to commit. */ 6642731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6651061SN/A 6661060SN/A /** Returns whether or not this instruction is ready to commit. */ 6672731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6682731Sktlim@umich.edu 6692731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6702731Sktlim@umich.edu 6712731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6721060SN/A 6732292SN/A /** Sets this instruction as committed. */ 6742731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6752292SN/A 6762292SN/A /** Returns whether or not this instruction is committed. */ 6772731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6782292SN/A 6791060SN/A /** Sets this instruction as squashed. */ 6802731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6811060SN/A 6821060SN/A /** Returns whether or not this instruction is squashed. */ 6832731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6841060SN/A 6852292SN/A //Instruction Queue Entry 6862292SN/A //----------------------- 6872292SN/A /** Sets this instruction as a entry the IQ. */ 6882731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6892292SN/A 6902292SN/A /** Sets this instruction as a entry the IQ. */ 6912731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6922731Sktlim@umich.edu 6932731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 6942731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 6952292SN/A 6961060SN/A /** Sets this instruction as squashed in the IQ. */ 6972731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 6981060SN/A 6991060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7002731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7012292SN/A 7022292SN/A 7032292SN/A //Load / Store Queue Functions 7042292SN/A //----------------------- 7052292SN/A /** Sets this instruction as a entry the LSQ. */ 7062731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7072292SN/A 7082292SN/A /** Sets this instruction as a entry the LSQ. */ 7092731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7102731Sktlim@umich.edu 7112731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7122731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7132292SN/A 7142292SN/A /** Sets this instruction as squashed in the LSQ. */ 7152731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7162292SN/A 7172292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7182731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7192292SN/A 7202292SN/A 7212292SN/A //Reorder Buffer Functions 7222292SN/A //----------------------- 7232292SN/A /** Sets this instruction as a entry the ROB. */ 7242731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7252292SN/A 7262292SN/A /** Sets this instruction as a entry the ROB. */ 7272731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7282731Sktlim@umich.edu 7292731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7302731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7312292SN/A 7322292SN/A /** Sets this instruction as squashed in the ROB. */ 7332731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7342292SN/A 7352292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7362731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7372292SN/A 7381060SN/A /** Read the PC of this instruction. */ 7391464SN/A const Addr readPC() const { return PC; } 7401060SN/A 7414636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7424636Sgblack@eecs.umich.edu const Addr readMicroPC() const { return microPC; } 7434636Sgblack@eecs.umich.edu 7441060SN/A /** Set the next PC of this instruction (its actual target). */ 7454636Sgblack@eecs.umich.edu void setNextPC(Addr val) 7462308SN/A { 7472308SN/A nextPC = val; 7482308SN/A } 7492190SN/A 7502935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 7514636Sgblack@eecs.umich.edu void setNextNPC(Addr val) 7522935Sksewell@umich.edu { 7534632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 7542935Sksewell@umich.edu nextNPC = val; 7554632Sgblack@eecs.umich.edu#endif 7562935Sksewell@umich.edu } 7572935Sksewell@umich.edu 7584636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val) 7594636Sgblack@eecs.umich.edu { 7604636Sgblack@eecs.umich.edu nextMicroPC = val; 7614636Sgblack@eecs.umich.edu } 7624636Sgblack@eecs.umich.edu 7632702Sktlim@umich.edu /** Sets the ASID. */ 7642292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7652292SN/A 7662702Sktlim@umich.edu /** Sets the thread id. */ 7672702Sktlim@umich.edu void setTid(unsigned tid) { threadNumber = tid; } 7682292SN/A 7692731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7702702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7711060SN/A 7722731Sktlim@umich.edu /** Returns the thread context. */ 7732680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7741464SN/A 7751464SN/A private: 7761684SN/A /** Instruction effective address. 7771684SN/A * @todo: Consider if this is necessary or not. 7781684SN/A */ 7791464SN/A Addr instEffAddr; 7802292SN/A 7811684SN/A /** Whether or not the effective address calculation is completed. 7821684SN/A * @todo: Consider if this is necessary or not. 7831684SN/A */ 7841464SN/A bool eaCalcDone; 7851464SN/A 7864032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7874032Sktlim@umich.edu bool isUncacheable; 7884032Sktlim@umich.edu 7894032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7904032Sktlim@umich.edu bool reqMade; 7914032Sktlim@umich.edu 7921464SN/A public: 7931684SN/A /** Sets the effective address. */ 7941464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 7951684SN/A 7961684SN/A /** Returns the effective address. */ 7971464SN/A const Addr &getEA() const { return instEffAddr; } 7981684SN/A 7991684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8001464SN/A bool doneEACalc() { return eaCalcDone; } 8011684SN/A 8021684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8031464SN/A bool eaSrcsReady(); 8041681SN/A 8052292SN/A /** Whether or not the memory operation is done. */ 8062292SN/A bool memOpDone; 8072292SN/A 8084032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8094032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8104032Sktlim@umich.edu 8114032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8124032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8134032Sktlim@umich.edu 8141681SN/A public: 8151684SN/A /** Load queue index. */ 8161681SN/A int16_t lqIdx; 8171684SN/A 8181684SN/A /** Store queue index. */ 8191681SN/A int16_t sqIdx; 8202292SN/A 8212292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8222292SN/A ListIt instListIt; 8232292SN/A 8242292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8252292SN/A ListIt &getInstListIt() { return instListIt; } 8262292SN/A 8272292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8282292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8293326Sktlim@umich.edu 8303326Sktlim@umich.edu public: 8313326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8323326Sktlim@umich.edu unsigned readStCondFailures() 8333326Sktlim@umich.edu { return thread->storeCondFailures; } 8343326Sktlim@umich.edu 8353326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8363326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8373326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8381060SN/A}; 8391060SN/A 8401060SN/Atemplate<class Impl> 8411060SN/Atemplate<class T> 8422132SN/Ainline Fault 8431060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 8441060SN/A{ 8454032Sktlim@umich.edu reqMade = true; 8464032Sktlim@umich.edu Request *req = new Request(); 8474032Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 8484032Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 8492292SN/A 8502669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 8512292SN/A TheISA::VMPageSize) { 8524032Sktlim@umich.edu delete req; 8532292SN/A return TheISA::genAlignmentFault(); 8542292SN/A } 8551060SN/A 8562690Sktlim@umich.edu fault = cpu->translateDataReadReq(req, thread); 8571060SN/A 8584032Sktlim@umich.edu if (req->isUncacheable()) 8594032Sktlim@umich.edu isUncacheable = true; 8604032Sktlim@umich.edu 8612678Sktlim@umich.edu if (fault == NoFault) { 8622678Sktlim@umich.edu effAddr = req->getVaddr(); 8634032Sktlim@umich.edu effAddrValid = true; 8642678Sktlim@umich.edu physEffAddr = req->getPaddr(); 8652678Sktlim@umich.edu memReqFlags = req->getFlags(); 8661060SN/A 8672690Sktlim@umich.edu#if 0 8682292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 8692292SN/A fault = TheISA::genMachineCheckFault(); 8702292SN/A data = (T)-1; 8712292SN/A this->setExecuted(); 8722292SN/A } else { 8732292SN/A fault = cpu->read(req, data, lqIdx); 8742292SN/A } 8752292SN/A#else 8761681SN/A fault = cpu->read(req, data, lqIdx); 8772632Sstever@eecs.umich.edu#endif 8781684SN/A } else { 8791060SN/A // Return a fixed value to keep simulation deterministic even 8801060SN/A // along misspeculated paths. 8811060SN/A data = (T)-1; 8822292SN/A 8832292SN/A // Commit will have to clean up whatever happened. Set this 8842292SN/A // instruction as executed. 8852292SN/A this->setExecuted(); 8864032Sktlim@umich.edu delete req; 8871060SN/A } 8881060SN/A 8891060SN/A if (traceData) { 8901060SN/A traceData->setAddr(addr); 8911060SN/A traceData->setData(data); 8921060SN/A } 8931060SN/A 8941060SN/A return fault; 8951060SN/A} 8961060SN/A 8971060SN/Atemplate<class Impl> 8981060SN/Atemplate<class T> 8992132SN/Ainline Fault 9001060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9011060SN/A{ 9021060SN/A if (traceData) { 9031060SN/A traceData->setAddr(addr); 9041060SN/A traceData->setData(data); 9051060SN/A } 9061060SN/A 9074032Sktlim@umich.edu reqMade = true; 9084032Sktlim@umich.edu Request *req = new Request(); 9092669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 9102683Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 9111060SN/A 9122669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 9132292SN/A TheISA::VMPageSize) { 9144032Sktlim@umich.edu delete req; 9152292SN/A return TheISA::genAlignmentFault(); 9162292SN/A } 9171060SN/A 9182690Sktlim@umich.edu fault = cpu->translateDataWriteReq(req, thread); 9191060SN/A 9204032Sktlim@umich.edu if (req->isUncacheable()) 9214032Sktlim@umich.edu isUncacheable = true; 9224032Sktlim@umich.edu 9232090SN/A if (fault == NoFault) { 9242678Sktlim@umich.edu effAddr = req->getVaddr(); 9254032Sktlim@umich.edu effAddrValid = true; 9262678Sktlim@umich.edu physEffAddr = req->getPaddr(); 9272678Sktlim@umich.edu memReqFlags = req->getFlags(); 9284350Sgblack@eecs.umich.edu 9294350Sgblack@eecs.umich.edu if (req->isCondSwap()) { 9304350Sgblack@eecs.umich.edu assert(res); 9314350Sgblack@eecs.umich.edu req->setExtraData(*res); 9324350Sgblack@eecs.umich.edu } 9332690Sktlim@umich.edu#if 0 9342292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 9352292SN/A fault = TheISA::genMachineCheckFault(); 9362292SN/A } else { 9372292SN/A fault = cpu->write(req, data, sqIdx); 9382292SN/A } 9392292SN/A#else 9401681SN/A fault = cpu->write(req, data, sqIdx); 9412632Sstever@eecs.umich.edu#endif 9424032Sktlim@umich.edu } else { 9434032Sktlim@umich.edu delete req; 9441060SN/A } 9451060SN/A 9461060SN/A return fault; 9471060SN/A} 9481060SN/A 9491464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 950