base_dyn_inst.hh revision 2683
11060SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321464SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 342292SN/A#include <list> 351464SN/A#include <string> 361060SN/A 372669Sktlim@umich.edu#include "arch/faults.hh" 381060SN/A#include "base/fast_alloc.hh" 391060SN/A#include "base/trace.hh" 401858SN/A#include "config/full_system.hh" 411464SN/A#include "cpu/exetrace.hh" 421464SN/A#include "cpu/inst_seq.hh" 432669Sktlim@umich.edu#include "cpu/op_class.hh" 441060SN/A#include "cpu/static_inst.hh" 452669Sktlim@umich.edu#include "mem/packet.hh" 462292SN/A#include "sim/system.hh" 472292SN/A/* 481717SN/A#include "encumbered/cpu/full/bpred_update.hh" 491717SN/A#include "encumbered/cpu/full/spec_memory.hh" 501717SN/A#include "encumbered/cpu/full/spec_state.hh" 511717SN/A#include "encumbered/mem/functional/main.hh" 522292SN/A*/ 531060SN/A 541060SN/A/** 551060SN/A * @file 561060SN/A * Defines a dynamic instruction context. 571060SN/A */ 581060SN/A 591061SN/A// Forward declaration. 601061SN/Aclass StaticInstPtr; 611060SN/A 621060SN/Atemplate <class Impl> 631061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 641060SN/A{ 651060SN/A public: 661060SN/A // Typedef for the CPU. 671060SN/A typedef typename Impl::FullCPU FullCPU; 682292SN/A typedef typename FullCPU::ImplState ImplState; 691060SN/A 702292SN/A // Binary machine instruction type. 712107SN/A typedef TheISA::MachInst MachInst; 722292SN/A // Extended machine instruction type 732292SN/A typedef TheISA::ExtMachInst ExtMachInst; 742292SN/A // Logical register index type. 752107SN/A typedef TheISA::RegIndex RegIndex; 762292SN/A // Integer register index type. 772107SN/A typedef TheISA::IntReg IntReg; 781060SN/A 792292SN/A // The DynInstPtr type. 802292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 812292SN/A 822292SN/A // The list of instructions iterator type. 832292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 842292SN/A 851060SN/A enum { 862292SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 872292SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 881060SN/A }; 891060SN/A 902292SN/A /** The StaticInst used by this BaseDynInst. */ 912107SN/A StaticInstPtr staticInst; 921060SN/A 931060SN/A //////////////////////////////////////////// 941060SN/A // 951060SN/A // INSTRUCTION EXECUTION 961060SN/A // 971060SN/A //////////////////////////////////////////// 982292SN/A /** InstRecord that tracks this instructions. */ 991060SN/A Trace::InstRecord *traceData; 1001060SN/A 1012292SN/A /** 1022292SN/A * Does a read to a given address. 1032292SN/A * @param addr The address to read. 1042292SN/A * @param data The read's data is written into this parameter. 1052292SN/A * @param flags The request's flags. 1062292SN/A * @return Returns any fault due to the read. 1072292SN/A */ 1081060SN/A template <class T> 1092132SN/A Fault read(Addr addr, T &data, unsigned flags); 1101060SN/A 1112292SN/A /** 1122292SN/A * Does a write to a given address. 1132292SN/A * @param data The data to be written. 1142292SN/A * @param addr The address to write to. 1152292SN/A * @param flags The request's flags. 1162292SN/A * @param res The result of the write (for load locked/store conditionals). 1172292SN/A * @return Returns any fault due to the write. 1182292SN/A */ 1191060SN/A template <class T> 1202132SN/A Fault write(T data, Addr addr, unsigned flags, 1211060SN/A uint64_t *res); 1221060SN/A 1231060SN/A void prefetch(Addr addr, unsigned flags); 1241060SN/A void writeHint(Addr addr, int size, unsigned flags); 1252132SN/A Fault copySrcTranslate(Addr src); 1262132SN/A Fault copy(Addr dest); 1271060SN/A 1281684SN/A /** @todo: Consider making this private. */ 1291060SN/A public: 1301060SN/A /** The sequence number of the instruction. */ 1311060SN/A InstSeqNum seqNum; 1321060SN/A 1332292SN/A /** Is the instruction in the IQ */ 1342292SN/A bool iqEntry; 1352292SN/A 1362292SN/A /** Is the instruction in the ROB */ 1372292SN/A bool robEntry; 1382292SN/A 1392292SN/A /** Is the instruction in the LSQ */ 1402292SN/A bool lsqEntry; 1411060SN/A 1421464SN/A /** Is the instruction completed. */ 1431464SN/A bool completed; 1441464SN/A 1452308SN/A /** Is the instruction's result ready. */ 1462308SN/A bool resultReady; 1472308SN/A 1481060SN/A /** Can this instruction issue. */ 1491060SN/A bool canIssue; 1501060SN/A 1511060SN/A /** Has this instruction issued. */ 1521060SN/A bool issued; 1531060SN/A 1541060SN/A /** Has this instruction executed (or made it through execute) yet. */ 1551060SN/A bool executed; 1561060SN/A 1571060SN/A /** Can this instruction commit. */ 1581060SN/A bool canCommit; 1591060SN/A 1602292SN/A /** Is this instruction committed. */ 1612292SN/A bool committed; 1622292SN/A 1631060SN/A /** Is this instruction squashed. */ 1641060SN/A bool squashed; 1651060SN/A 1661060SN/A /** Is this instruction squashed in the instruction queue. */ 1671060SN/A bool squashedInIQ; 1681060SN/A 1692292SN/A /** Is this instruction squashed in the instruction queue. */ 1702292SN/A bool squashedInLSQ; 1712292SN/A 1722292SN/A /** Is this instruction squashed in the instruction queue. */ 1732292SN/A bool squashedInROB; 1742292SN/A 1751060SN/A /** Is this a recover instruction. */ 1761060SN/A bool recoverInst; 1771060SN/A 1781060SN/A /** Is this a thread blocking instruction. */ 1791060SN/A bool blockingInst; /* this inst has called thread_block() */ 1801060SN/A 1811060SN/A /** Is this a thread syncrhonization instruction. */ 1821060SN/A bool threadsyncWait; 1831060SN/A 1841060SN/A /** The thread this instruction is from. */ 1851060SN/A short threadNumber; 1861060SN/A 1871060SN/A /** data address space ID, for loads & stores. */ 1881060SN/A short asid; 1891060SN/A 1902292SN/A /** How many source registers are ready. */ 1912292SN/A unsigned readyRegs; 1922292SN/A 1931060SN/A /** Pointer to the FullCPU object. */ 1941060SN/A FullCPU *cpu; 1951060SN/A 1962680Sktlim@umich.edu /** Pointer to the thread state. */ 1972292SN/A ImplState *thread; 1981060SN/A 1991060SN/A /** The kind of fault this instruction has generated. */ 2002132SN/A Fault fault; 2011060SN/A 2022292SN/A /** The memory request. */ 2032669Sktlim@umich.edu// MemReqPtr req; 2042669Sktlim@umich.edu Request *req; 2052669Sktlim@umich.edu// Packet pkt; 2062669Sktlim@umich.edu 2072669Sktlim@umich.edu uint8_t *memData; 2082292SN/A 2091060SN/A /** The effective virtual address (lds & stores only). */ 2101060SN/A Addr effAddr; 2111060SN/A 2121060SN/A /** The effective physical address. */ 2131060SN/A Addr physEffAddr; 2141060SN/A 2151060SN/A /** Effective virtual address for a copy source. */ 2161060SN/A Addr copySrcEffAddr; 2171060SN/A 2181060SN/A /** Effective physical address for a copy source. */ 2191060SN/A Addr copySrcPhysEffAddr; 2201060SN/A 2211060SN/A /** The memory request flags (from translation). */ 2221060SN/A unsigned memReqFlags; 2231060SN/A 2241060SN/A /** The size of the data to be stored. */ 2251060SN/A int storeSize; 2261060SN/A 2271060SN/A /** The data to be stored. */ 2281060SN/A IntReg storeData; 2291060SN/A 2301464SN/A union Result { 2311464SN/A uint64_t integer; 2321464SN/A float fp; 2331464SN/A double dbl; 2341464SN/A }; 2351060SN/A 2361464SN/A /** The result of the instruction; assumes for now that there's only one 2371464SN/A * destination register. 2381464SN/A */ 2391464SN/A Result instResult; 2401060SN/A 2411060SN/A /** PC of this instruction. */ 2421060SN/A Addr PC; 2431060SN/A 2441060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2451060SN/A * once the target of the branch is truly known (either decode or 2461060SN/A * execute). 2471060SN/A */ 2481060SN/A Addr nextPC; 2491060SN/A 2501060SN/A /** Predicted next PC. */ 2511060SN/A Addr predPC; 2521060SN/A 2531060SN/A /** Count of total number of dynamic instructions. */ 2541060SN/A static int instcount; 2551060SN/A 2562292SN/A#ifdef DEBUG 2572292SN/A void dumpSNList(); 2582292SN/A#endif 2592292SN/A 2602292SN/A /** Whether or not the source register is ready. 2612292SN/A * @todo: Not sure this should be here vs the derived class. 2621060SN/A */ 2631060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2641060SN/A 2651060SN/A public: 2662292SN/A /** BaseDynInst constructor given a binary instruction. 2672292SN/A * @param inst The binary instruction. 2682292SN/A * @param PC The PC of the instruction. 2692292SN/A * @param pred_PC The predicted next PC. 2702292SN/A * @param seq_num The sequence number of the instruction. 2712292SN/A * @param cpu Pointer to the instruction's CPU. 2722292SN/A */ 2732292SN/A BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, 2741060SN/A FullCPU *cpu); 2751060SN/A 2762292SN/A /** BaseDynInst constructor given a StaticInst pointer. 2772292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 2782292SN/A */ 2792107SN/A BaseDynInst(StaticInstPtr &_staticInst); 2801060SN/A 2811060SN/A /** BaseDynInst destructor. */ 2821060SN/A ~BaseDynInst(); 2831060SN/A 2841464SN/A private: 2851684SN/A /** Function to initialize variables in the constructors. */ 2861464SN/A void initVars(); 2871060SN/A 2881464SN/A public: 2892292SN/A /** 2902292SN/A * @todo: Make this function work; currently it is a dummy function. 2912292SN/A * @param fault Last fault. 2922292SN/A * @param cmd Last command. 2932292SN/A * @param addr Virtual address of access. 2942292SN/A * @param p Memory accessed. 2952292SN/A * @param nbytes Access size. 2962292SN/A */ 2972669Sktlim@umich.edu// void 2982669Sktlim@umich.edu// trace_mem(Fault fault, 2992669Sktlim@umich.edu// MemCmd cmd, 3002669Sktlim@umich.edu// Addr addr, 3012669Sktlim@umich.edu// void *p, 3022669Sktlim@umich.edu// int nbytes); 3031060SN/A 3041060SN/A /** Dumps out contents of this BaseDynInst. */ 3051060SN/A void dump(); 3061060SN/A 3071060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 3081060SN/A void dump(std::string &outstring); 3091060SN/A 3101060SN/A /** Returns the fault type. */ 3112132SN/A Fault getFault() { return fault; } 3121060SN/A 3131060SN/A /** Checks whether or not this instruction has had its branch target 3141060SN/A * calculated yet. For now it is not utilized and is hacked to be 3151060SN/A * always false. 3162292SN/A * @todo: Actually use this instruction. 3171060SN/A */ 3181060SN/A bool doneTargCalc() { return false; } 3191060SN/A 3201684SN/A /** Returns the next PC. This could be the speculative next PC if it is 3211684SN/A * called prior to the actual branch target being calculated. 3221684SN/A */ 3231060SN/A Addr readNextPC() { return nextPC; } 3241060SN/A 3251060SN/A /** Set the predicted target of this current instruction. */ 3261060SN/A void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 3271060SN/A 3281060SN/A /** Returns the predicted target of the branch. */ 3291060SN/A Addr readPredTarg() { return predPC; } 3301060SN/A 3311060SN/A /** Returns whether the instruction was predicted taken or not. */ 3322292SN/A bool predTaken() { return predPC != (PC + sizeof(MachInst)); } 3331060SN/A 3341060SN/A /** Returns whether the instruction mispredicted. */ 3352292SN/A bool mispredicted() { return predPC != nextPC; } 3361060SN/A 3371060SN/A // 3381060SN/A // Instruction types. Forward checks to StaticInst object. 3391060SN/A // 3401060SN/A bool isNop() const { return staticInst->isNop(); } 3411060SN/A bool isMemRef() const { return staticInst->isMemRef(); } 3421060SN/A bool isLoad() const { return staticInst->isLoad(); } 3431060SN/A bool isStore() const { return staticInst->isStore(); } 3442336SN/A bool isStoreConditional() const 3452336SN/A { return staticInst->isStoreConditional(); } 3461060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 3471060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 3481060SN/A bool isCopy() const { return staticInst->isCopy(); } 3491060SN/A bool isInteger() const { return staticInst->isInteger(); } 3501060SN/A bool isFloating() const { return staticInst->isFloating(); } 3511060SN/A bool isControl() const { return staticInst->isControl(); } 3521060SN/A bool isCall() const { return staticInst->isCall(); } 3531060SN/A bool isReturn() const { return staticInst->isReturn(); } 3541060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 3551060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 3561060SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 3571060SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 3581060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 3591060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 3602292SN/A bool isSerializeBefore() const 3612292SN/A { return staticInst->isSerializeBefore() || serializeBefore; } 3622292SN/A bool isSerializeAfter() const 3632292SN/A { return staticInst->isSerializeAfter() || serializeAfter; } 3641060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 3651060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 3661060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 3672292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 3682336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 3692308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 3702292SN/A 3712292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 3722292SN/A void setSerializeBefore() { serializeBefore = true; } 3732292SN/A 3742292SN/A /** Clears the serializeBefore part of this instruction. */ 3752292SN/A void clearSerializeBefore() { serializeBefore = false; } 3762292SN/A 3772292SN/A /** Checks if this serializeBefore is only temporarily set. */ 3782292SN/A bool isTempSerializeBefore() { return serializeBefore; } 3792292SN/A 3802292SN/A /** Tracks if instruction has been externally set as serializeBefore. */ 3812292SN/A bool serializeBefore; 3822292SN/A 3832292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 3842292SN/A void setSerializeAfter() { serializeAfter = true; } 3852292SN/A 3862292SN/A /** Clears the serializeAfter part of this instruction.*/ 3872292SN/A void clearSerializeAfter() { serializeAfter = false; } 3882292SN/A 3892292SN/A /** Checks if this serializeAfter is only temporarily set. */ 3902292SN/A bool isTempSerializeAfter() { return serializeAfter; } 3912292SN/A 3922292SN/A /** Tracks if instruction has been externally set as serializeAfter. */ 3932292SN/A bool serializeAfter; 3942292SN/A 3952292SN/A /** Checks if the serialization part of this instruction has been 3962292SN/A * handled. This does not apply to the temporary serializing 3972292SN/A * state; it only applies to this instruction's own permanent 3982292SN/A * serializing state. 3992292SN/A */ 4002292SN/A bool isSerializeHandled() { return serializeHandled; } 4012292SN/A 4022292SN/A /** Sets the serialization part of this instruction as handled. */ 4032292SN/A void setSerializeHandled() { serializeHandled = true; } 4042292SN/A 4052292SN/A /** Whether or not the serialization of this instruction has been handled. */ 4062292SN/A bool serializeHandled; 4071060SN/A 4081464SN/A /** Returns the opclass of this instruction. */ 4091464SN/A OpClass opClass() const { return staticInst->opClass(); } 4101464SN/A 4111464SN/A /** Returns the branch target address. */ 4121464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 4131464SN/A 4142292SN/A /** Returns the number of source registers. */ 4152292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 4161684SN/A 4172292SN/A /** Returns the number of destination registers. */ 4181060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 4191060SN/A 4201060SN/A // the following are used to track physical register usage 4211060SN/A // for machines with separate int & FP reg files 4221060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 4231060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 4241060SN/A 4251060SN/A /** Returns the logical register index of the i'th destination register. */ 4262292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 4271060SN/A 4281060SN/A /** Returns the logical register index of the i'th source register. */ 4292292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 4301060SN/A 4311684SN/A /** Returns the result of an integer instruction. */ 4321464SN/A uint64_t readIntResult() { return instResult.integer; } 4331684SN/A 4341684SN/A /** Returns the result of a floating point instruction. */ 4351464SN/A float readFloatResult() { return instResult.fp; } 4361684SN/A 4371684SN/A /** Returns the result of a floating point (double) instruction. */ 4381464SN/A double readDoubleResult() { return instResult.dbl; } 4391060SN/A 4402308SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 4411060SN/A { 4422308SN/A instResult.integer = val; 4431060SN/A } 4441060SN/A 4452308SN/A void setFloatRegSingle(const StaticInst *si, int idx, float val) 4461060SN/A { 4472308SN/A instResult.fp = val; 4482308SN/A } 4491060SN/A 4502308SN/A void setFloatRegDouble(const StaticInst *si, int idx, double val) 4512308SN/A { 4522308SN/A instResult.dbl = val; 4532308SN/A } 4541060SN/A 4552308SN/A void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) 4562308SN/A { 4572308SN/A instResult.integer = val; 4581060SN/A } 4591060SN/A 4602190SN/A /** Records that one of the source registers is ready. */ 4612292SN/A void markSrcRegReady(); 4622190SN/A 4632331SN/A /** Marks a specific register as ready. */ 4642292SN/A void markSrcRegReady(RegIndex src_idx); 4652190SN/A 4661684SN/A /** Returns if a source register is ready. */ 4671464SN/A bool isReadySrcRegIdx(int idx) const 4681464SN/A { 4691464SN/A return this->_readySrcRegIdx[idx]; 4701464SN/A } 4711464SN/A 4721684SN/A /** Sets this instruction as completed. */ 4731464SN/A void setCompleted() { completed = true; } 4741464SN/A 4752292SN/A /** Returns whether or not this instruction is completed. */ 4761464SN/A bool isCompleted() const { return completed; } 4771464SN/A 4782308SN/A void setResultReady() { resultReady = true; } 4792308SN/A 4802308SN/A bool isResultReady() const { return resultReady; } 4812308SN/A 4821060SN/A /** Sets this instruction as ready to issue. */ 4831060SN/A void setCanIssue() { canIssue = true; } 4841060SN/A 4851060SN/A /** Returns whether or not this instruction is ready to issue. */ 4861060SN/A bool readyToIssue() const { return canIssue; } 4871060SN/A 4881060SN/A /** Sets this instruction as issued from the IQ. */ 4891060SN/A void setIssued() { issued = true; } 4901060SN/A 4911060SN/A /** Returns whether or not this instruction has issued. */ 4921464SN/A bool isIssued() const { return issued; } 4931060SN/A 4941060SN/A /** Sets this instruction as executed. */ 4951060SN/A void setExecuted() { executed = true; } 4961060SN/A 4971060SN/A /** Returns whether or not this instruction has executed. */ 4981464SN/A bool isExecuted() const { return executed; } 4991060SN/A 5001060SN/A /** Sets this instruction as ready to commit. */ 5011060SN/A void setCanCommit() { canCommit = true; } 5021060SN/A 5031061SN/A /** Clears this instruction as being ready to commit. */ 5041061SN/A void clearCanCommit() { canCommit = false; } 5051061SN/A 5061060SN/A /** Returns whether or not this instruction is ready to commit. */ 5071060SN/A bool readyToCommit() const { return canCommit; } 5081060SN/A 5092292SN/A /** Sets this instruction as committed. */ 5102292SN/A void setCommitted() { committed = true; } 5112292SN/A 5122292SN/A /** Returns whether or not this instruction is committed. */ 5132292SN/A bool isCommitted() const { return committed; } 5142292SN/A 5151060SN/A /** Sets this instruction as squashed. */ 5161060SN/A void setSquashed() { squashed = true; } 5171060SN/A 5181060SN/A /** Returns whether or not this instruction is squashed. */ 5191060SN/A bool isSquashed() const { return squashed; } 5201060SN/A 5212292SN/A //Instruction Queue Entry 5222292SN/A //----------------------- 5232292SN/A /** Sets this instruction as a entry the IQ. */ 5242292SN/A void setInIQ() { iqEntry = true; } 5252292SN/A 5262292SN/A /** Sets this instruction as a entry the IQ. */ 5272292SN/A void removeInIQ() { iqEntry = false; } 5282292SN/A 5291060SN/A /** Sets this instruction as squashed in the IQ. */ 5302292SN/A void setSquashedInIQ() { squashedInIQ = true; squashed = true;} 5311060SN/A 5321060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 5331464SN/A bool isSquashedInIQ() const { return squashedInIQ; } 5341060SN/A 5352292SN/A /** Returns whether or not this instruction has issued. */ 5362292SN/A bool isInIQ() const { return iqEntry; } 5372292SN/A 5382292SN/A 5392292SN/A //Load / Store Queue Functions 5402292SN/A //----------------------- 5412292SN/A /** Sets this instruction as a entry the LSQ. */ 5422292SN/A void setInLSQ() { lsqEntry = true; } 5432292SN/A 5442292SN/A /** Sets this instruction as a entry the LSQ. */ 5452292SN/A void removeInLSQ() { lsqEntry = false; } 5462292SN/A 5472292SN/A /** Sets this instruction as squashed in the LSQ. */ 5482292SN/A void setSquashedInLSQ() { squashedInLSQ = true;} 5492292SN/A 5502292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 5512292SN/A bool isSquashedInLSQ() const { return squashedInLSQ; } 5522292SN/A 5532292SN/A /** Returns whether or not this instruction is in the LSQ. */ 5542292SN/A bool isInLSQ() const { return lsqEntry; } 5552292SN/A 5562292SN/A 5572292SN/A //Reorder Buffer Functions 5582292SN/A //----------------------- 5592292SN/A /** Sets this instruction as a entry the ROB. */ 5602292SN/A void setInROB() { robEntry = true; } 5612292SN/A 5622292SN/A /** Sets this instruction as a entry the ROB. */ 5632292SN/A void removeInROB() { robEntry = false; } 5642292SN/A 5652292SN/A /** Sets this instruction as squashed in the ROB. */ 5662292SN/A void setSquashedInROB() { squashedInROB = true; } 5672292SN/A 5682292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 5692292SN/A bool isSquashedInROB() const { return squashedInROB; } 5702292SN/A 5712292SN/A /** Returns whether or not this instruction is in the ROB. */ 5722292SN/A bool isInROB() const { return robEntry; } 5732292SN/A 5741060SN/A /** Read the PC of this instruction. */ 5751464SN/A const Addr readPC() const { return PC; } 5761060SN/A 5771060SN/A /** Set the next PC of this instruction (its actual target). */ 5782308SN/A void setNextPC(uint64_t val) 5792308SN/A { 5802308SN/A nextPC = val; 5812308SN/A// instResult.integer = val; 5822308SN/A } 5832190SN/A 5842292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 5852292SN/A 5862292SN/A void setThread(unsigned tid) { threadNumber = tid; } 5872292SN/A 5882292SN/A void setState(ImplState *state) { thread = state; } 5891060SN/A 5902680Sktlim@umich.edu /** Returns the thread context. 5911684SN/A */ 5922680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 5931464SN/A 5941464SN/A private: 5951684SN/A /** Instruction effective address. 5961684SN/A * @todo: Consider if this is necessary or not. 5971684SN/A */ 5981464SN/A Addr instEffAddr; 5992292SN/A 6001684SN/A /** Whether or not the effective address calculation is completed. 6011684SN/A * @todo: Consider if this is necessary or not. 6021684SN/A */ 6031464SN/A bool eaCalcDone; 6041464SN/A 6051464SN/A public: 6061684SN/A /** Sets the effective address. */ 6071464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 6081684SN/A 6091684SN/A /** Returns the effective address. */ 6101464SN/A const Addr &getEA() const { return instEffAddr; } 6111684SN/A 6121684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 6131464SN/A bool doneEACalc() { return eaCalcDone; } 6141684SN/A 6151684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 6161464SN/A bool eaSrcsReady(); 6171681SN/A 6182292SN/A /** Whether or not the memory operation is done. */ 6192292SN/A bool memOpDone; 6202292SN/A 6211681SN/A public: 6221684SN/A /** Load queue index. */ 6231681SN/A int16_t lqIdx; 6241684SN/A 6251684SN/A /** Store queue index. */ 6261681SN/A int16_t sqIdx; 6272292SN/A 6282292SN/A bool reachedCommit; 6292292SN/A 6302292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 6312292SN/A ListIt instListIt; 6322292SN/A 6332292SN/A /** Returns iterator to this instruction in the list of all insts. */ 6342292SN/A ListIt &getInstListIt() { return instListIt; } 6352292SN/A 6362292SN/A /** Sets iterator for this instruction in the list of all insts. */ 6372292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 6381060SN/A}; 6391060SN/A 6401060SN/Atemplate<class Impl> 6411060SN/Atemplate<class T> 6422132SN/Ainline Fault 6431060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 6441060SN/A{ 6452292SN/A if (executed) { 6462669Sktlim@umich.edu panic("Not supposed to re-execute with split mem ops!"); 6472292SN/A fault = cpu->read(req, data, lqIdx); 6482292SN/A return fault; 6492292SN/A } 6502292SN/A 6512669Sktlim@umich.edu req = new Request(); 6522669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 6532683Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 6542292SN/A 6552669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 6562292SN/A TheISA::VMPageSize) { 6572292SN/A return TheISA::genAlignmentFault(); 6582292SN/A } 6591060SN/A 6601060SN/A fault = cpu->translateDataReadReq(req); 6611060SN/A 6622678Sktlim@umich.edu if (fault == NoFault) { 6632678Sktlim@umich.edu effAddr = req->getVaddr(); 6642678Sktlim@umich.edu physEffAddr = req->getPaddr(); 6652678Sktlim@umich.edu memReqFlags = req->getFlags(); 6661060SN/A 6672292SN/A#if FULL_SYSTEM 6682292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 6692292SN/A fault = TheISA::genMachineCheckFault(); 6702292SN/A data = (T)-1; 6712292SN/A this->setExecuted(); 6722292SN/A } else { 6732292SN/A fault = cpu->read(req, data, lqIdx); 6742292SN/A } 6752292SN/A#else 6761681SN/A fault = cpu->read(req, data, lqIdx); 6772632Sstever@eecs.umich.edu#endif 6781684SN/A } else { 6791060SN/A // Return a fixed value to keep simulation deterministic even 6801060SN/A // along misspeculated paths. 6811060SN/A data = (T)-1; 6822292SN/A 6832292SN/A // Commit will have to clean up whatever happened. Set this 6842292SN/A // instruction as executed. 6852292SN/A this->setExecuted(); 6861060SN/A } 6871060SN/A 6881060SN/A if (traceData) { 6891060SN/A traceData->setAddr(addr); 6901060SN/A traceData->setData(data); 6911060SN/A } 6921060SN/A 6931060SN/A return fault; 6941060SN/A} 6951060SN/A 6961060SN/Atemplate<class Impl> 6971060SN/Atemplate<class T> 6982132SN/Ainline Fault 6991060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 7001060SN/A{ 7011060SN/A if (traceData) { 7021060SN/A traceData->setAddr(addr); 7031060SN/A traceData->setData(data); 7041060SN/A } 7051060SN/A 7062669Sktlim@umich.edu req = new Request(); 7072669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 7082683Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 7091060SN/A 7102669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 7112292SN/A TheISA::VMPageSize) { 7122292SN/A return TheISA::genAlignmentFault(); 7132292SN/A } 7141060SN/A 7151060SN/A fault = cpu->translateDataWriteReq(req); 7161060SN/A 7172090SN/A if (fault == NoFault) { 7182678Sktlim@umich.edu effAddr = req->getVaddr(); 7192678Sktlim@umich.edu physEffAddr = req->getPaddr(); 7202678Sktlim@umich.edu memReqFlags = req->getFlags(); 7212292SN/A#if FULL_SYSTEM 7222292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 7232292SN/A fault = TheISA::genMachineCheckFault(); 7242292SN/A } else { 7252292SN/A fault = cpu->write(req, data, sqIdx); 7262292SN/A } 7272292SN/A#else 7281681SN/A fault = cpu->write(req, data, sqIdx); 7292632Sstever@eecs.umich.edu#endif 7301060SN/A } 7311060SN/A 7321060SN/A if (res) { 7331060SN/A // always return some result to keep misspeculated paths 7341060SN/A // (which will ignore faults) deterministic 7352669Sktlim@umich.edu *res = (fault == NoFault) ? req->getScResult() : 0; 7361060SN/A } 7371060SN/A 7381060SN/A return fault; 7391060SN/A} 7401060SN/A 7411464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 742