base_dyn_inst.hh revision 12749
11060SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011,2013,2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 166973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 171060SN/A * All rights reserved. 181060SN/A * 191060SN/A * Redistribution and use in source and binary forms, with or without 201060SN/A * modification, are permitted provided that the following conditions are 211060SN/A * met: redistributions of source code must retain the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer; 231060SN/A * redistributions in binary form must reproduce the above copyright 241060SN/A * notice, this list of conditions and the following disclaimer in the 251060SN/A * documentation and/or other materials provided with the distribution; 261060SN/A * neither the name of the copyright holders nor the names of its 271060SN/A * contributors may be used to endorse or promote products derived from 281060SN/A * this software without specific prior written permission. 291060SN/A * 301060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 436973Stjones1@inf.ed.ac.uk * Timothy M. Jones 441060SN/A */ 451060SN/A 461464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 471464SN/A#define __CPU_BASE_DYN_INST_HH__ 481060SN/A 4910835Sandreas.hansson@arm.com#include <array> 502731Sktlim@umich.edu#include <bitset> 5112109SRekai.GonzalezAlberquilla@arm.com#include <deque> 522292SN/A#include <list> 531464SN/A#include <string> 541060SN/A 5510687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 567720Sgblack@eecs.umich.edu#include "arch/utility.hh" 571060SN/A#include "base/trace.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 598887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 6010319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 611464SN/A#include "cpu/exetrace.hh" 6212107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 631464SN/A#include "cpu/inst_seq.hh" 6412107SRekai.GonzalezAlberquilla@arm.com#include "cpu/o3/comm.hh" 652669Sktlim@umich.edu#include "cpu/op_class.hh" 661060SN/A#include "cpu/static_inst.hh" 676973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 682669Sktlim@umich.edu#include "mem/packet.hh" 6911608Snikos.nikoleris@arm.com#include "mem/request.hh" 707678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 712292SN/A#include "sim/system.hh" 721060SN/A 731060SN/A/** 741060SN/A * @file 751060SN/A * Defines a dynamic instruction context. 761060SN/A */ 771060SN/A 781060SN/Atemplate <class Impl> 7910319SAndreas.Sandberg@ARM.comclass BaseDynInst : public ExecContext, public RefCounted 801060SN/A{ 811060SN/A public: 821060SN/A // Typedef for the CPU. 832733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 842733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 8512109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 861060SN/A 872292SN/A // The DynInstPtr type. 882292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 898486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 902292SN/A 912292SN/A // The list of instructions iterator type. 922292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 932292SN/A 941060SN/A enum { 955543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 968902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 971060SN/A }; 981060SN/A 999046SAli.Saidi@ARM.com protected: 1009046SAli.Saidi@ARM.com enum Status { 1019046SAli.Saidi@ARM.com IqEntry, /// Instruction is in the IQ 1029046SAli.Saidi@ARM.com RobEntry, /// Instruction is in the ROB 1039046SAli.Saidi@ARM.com LsqEntry, /// Instruction is in the LSQ 1049046SAli.Saidi@ARM.com Completed, /// Instruction has completed 1059046SAli.Saidi@ARM.com ResultReady, /// Instruction has its result 1069046SAli.Saidi@ARM.com CanIssue, /// Instruction can issue and execute 1079046SAli.Saidi@ARM.com Issued, /// Instruction has issued 1089046SAli.Saidi@ARM.com Executed, /// Instruction has executed 1099046SAli.Saidi@ARM.com CanCommit, /// Instruction can commit 1109046SAli.Saidi@ARM.com AtCommit, /// Instruction has reached commit 1119046SAli.Saidi@ARM.com Committed, /// Instruction has committed 1129046SAli.Saidi@ARM.com Squashed, /// Instruction is squashed 1139046SAli.Saidi@ARM.com SquashedInIQ, /// Instruction is squashed in the IQ 1149046SAli.Saidi@ARM.com SquashedInLSQ, /// Instruction is squashed in the LSQ 1159046SAli.Saidi@ARM.com SquashedInROB, /// Instruction is squashed in the ROB 1169046SAli.Saidi@ARM.com RecoverInst, /// Is a recover instruction 1179046SAli.Saidi@ARM.com BlockingInst, /// Is a blocking instruction 1189046SAli.Saidi@ARM.com ThreadsyncWait, /// Is a thread synchronization instruction 1199046SAli.Saidi@ARM.com SerializeBefore, /// Needs to serialize on 1209046SAli.Saidi@ARM.com /// instructions ahead of it 1219046SAli.Saidi@ARM.com SerializeAfter, /// Needs to serialize instructions behind it 1229046SAli.Saidi@ARM.com SerializeHandled, /// Serialization has been handled 1239046SAli.Saidi@ARM.com NumStatus 1249046SAli.Saidi@ARM.com }; 1259046SAli.Saidi@ARM.com 1269046SAli.Saidi@ARM.com enum Flags { 12712421Sgabeblack@google.com NotAnInst, 1289046SAli.Saidi@ARM.com TranslationStarted, 1299046SAli.Saidi@ARM.com TranslationCompleted, 1309046SAli.Saidi@ARM.com PossibleLoadViolation, 1319046SAli.Saidi@ARM.com HitExternalSnoop, 1329046SAli.Saidi@ARM.com EffAddrValid, 1339046SAli.Saidi@ARM.com RecordResult, 1349046SAli.Saidi@ARM.com Predicate, 1359046SAli.Saidi@ARM.com PredTaken, 13610824SAndreas.Sandberg@ARM.com IsStrictlyOrdered, 1379046SAli.Saidi@ARM.com ReqMade, 1389046SAli.Saidi@ARM.com MemOpDone, 1399046SAli.Saidi@ARM.com MaxFlags 1409046SAli.Saidi@ARM.com }; 1419046SAli.Saidi@ARM.com 1429046SAli.Saidi@ARM.com public: 1439046SAli.Saidi@ARM.com /** The sequence number of the instruction. */ 1449046SAli.Saidi@ARM.com InstSeqNum seqNum; 1459046SAli.Saidi@ARM.com 1462292SN/A /** The StaticInst used by this BaseDynInst. */ 14710417Sandreas.hansson@arm.com const StaticInstPtr staticInst; 1489046SAli.Saidi@ARM.com 1499046SAli.Saidi@ARM.com /** Pointer to the Impl's CPU object. */ 1509046SAli.Saidi@ARM.com ImplCPU *cpu; 1519046SAli.Saidi@ARM.com 15210030SAli.Saidi@ARM.com BaseCPU *getCpuPtr() { return cpu; } 15310030SAli.Saidi@ARM.com 1549046SAli.Saidi@ARM.com /** Pointer to the thread state. */ 1559046SAli.Saidi@ARM.com ImplState *thread; 1569046SAli.Saidi@ARM.com 1579046SAli.Saidi@ARM.com /** The kind of fault this instruction has generated. */ 1589046SAli.Saidi@ARM.com Fault fault; 1599046SAli.Saidi@ARM.com 1609046SAli.Saidi@ARM.com /** InstRecord that tracks this instructions. */ 1619046SAli.Saidi@ARM.com Trace::InstRecord *traceData; 1629046SAli.Saidi@ARM.com 1639046SAli.Saidi@ARM.com protected: 1649046SAli.Saidi@ARM.com /** The result of the instruction; assumes an instruction can have many 1659046SAli.Saidi@ARM.com * destination registers. 1669046SAli.Saidi@ARM.com */ 16712107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> instResult; 1689046SAli.Saidi@ARM.com 1699046SAli.Saidi@ARM.com /** PC state for this instruction. */ 1709046SAli.Saidi@ARM.com TheISA::PCState pc; 1719046SAli.Saidi@ARM.com 1729046SAli.Saidi@ARM.com /* An amalgamation of a lot of boolean values into one */ 1739046SAli.Saidi@ARM.com std::bitset<MaxFlags> instFlags; 1749046SAli.Saidi@ARM.com 1759046SAli.Saidi@ARM.com /** The status of this BaseDynInst. Several bits can be set. */ 1769046SAli.Saidi@ARM.com std::bitset<NumStatus> status; 1779046SAli.Saidi@ARM.com 1789046SAli.Saidi@ARM.com /** Whether or not the source register is ready. 1799046SAli.Saidi@ARM.com * @todo: Not sure this should be here vs the derived class. 1809046SAli.Saidi@ARM.com */ 1819046SAli.Saidi@ARM.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1829046SAli.Saidi@ARM.com 1839046SAli.Saidi@ARM.com public: 1849046SAli.Saidi@ARM.com /** The thread this instruction is from. */ 1859046SAli.Saidi@ARM.com ThreadID threadNumber; 1869046SAli.Saidi@ARM.com 1879046SAli.Saidi@ARM.com /** Iterator pointing to this BaseDynInst in the list of all insts. */ 1889046SAli.Saidi@ARM.com ListIt instListIt; 1899046SAli.Saidi@ARM.com 1909046SAli.Saidi@ARM.com ////////////////////// Branch Data /////////////// 1919046SAli.Saidi@ARM.com /** Predicted PC state after this instruction. */ 1929046SAli.Saidi@ARM.com TheISA::PCState predPC; 1939046SAli.Saidi@ARM.com 1949046SAli.Saidi@ARM.com /** The Macroop if one exists */ 19510417Sandreas.hansson@arm.com const StaticInstPtr macroop; 1961060SN/A 1979046SAli.Saidi@ARM.com /** How many source registers are ready. */ 1989046SAli.Saidi@ARM.com uint8_t readyRegs; 1999046SAli.Saidi@ARM.com 2009046SAli.Saidi@ARM.com public: 2019046SAli.Saidi@ARM.com /////////////////////// Load Store Data ////////////////////// 2029046SAli.Saidi@ARM.com /** The effective virtual address (lds & stores only). */ 2039046SAli.Saidi@ARM.com Addr effAddr; 2049046SAli.Saidi@ARM.com 2059046SAli.Saidi@ARM.com /** The effective physical address. */ 20611097Songal@cs.wisc.edu Addr physEffAddrLow; 20711097Songal@cs.wisc.edu 20811097Songal@cs.wisc.edu /** The effective physical address 20911097Songal@cs.wisc.edu * of the second request for a split request 21011097Songal@cs.wisc.edu */ 21111097Songal@cs.wisc.edu Addr physEffAddrHigh; 2129046SAli.Saidi@ARM.com 2139046SAli.Saidi@ARM.com /** The memory request flags (from translation). */ 2149046SAli.Saidi@ARM.com unsigned memReqFlags; 2159046SAli.Saidi@ARM.com 2169046SAli.Saidi@ARM.com /** data address space ID, for loads & stores. */ 2179046SAli.Saidi@ARM.com short asid; 2189046SAli.Saidi@ARM.com 2199046SAli.Saidi@ARM.com /** The size of the request */ 2209046SAli.Saidi@ARM.com uint8_t effSize; 2219046SAli.Saidi@ARM.com 2229046SAli.Saidi@ARM.com /** Pointer to the data for the memory access. */ 2239046SAli.Saidi@ARM.com uint8_t *memData; 2249046SAli.Saidi@ARM.com 2259046SAli.Saidi@ARM.com /** Load queue index. */ 2269046SAli.Saidi@ARM.com int16_t lqIdx; 2279046SAli.Saidi@ARM.com 2289046SAli.Saidi@ARM.com /** Store queue index. */ 2299046SAli.Saidi@ARM.com int16_t sqIdx; 2309046SAli.Saidi@ARM.com 2319046SAli.Saidi@ARM.com 2329046SAli.Saidi@ARM.com /////////////////////// TLB Miss ////////////////////// 2339046SAli.Saidi@ARM.com /** 2349046SAli.Saidi@ARM.com * Saved memory requests (needed when the DTB address translation is 2359046SAli.Saidi@ARM.com * delayed due to a hw page table walk). 2369046SAli.Saidi@ARM.com */ 2379046SAli.Saidi@ARM.com RequestPtr savedReq; 2389046SAli.Saidi@ARM.com RequestPtr savedSreqLow; 2399046SAli.Saidi@ARM.com RequestPtr savedSreqHigh; 2409046SAli.Saidi@ARM.com 2419046SAli.Saidi@ARM.com /////////////////////// Checker ////////////////////// 2429046SAli.Saidi@ARM.com // Need a copy of main request pointer to verify on writes. 2439046SAli.Saidi@ARM.com RequestPtr reqToVerify; 2449046SAli.Saidi@ARM.com 2459046SAli.Saidi@ARM.com protected: 2469046SAli.Saidi@ARM.com /** Flattened register index of the destination registers of this 2479046SAli.Saidi@ARM.com * instruction. 2489046SAli.Saidi@ARM.com */ 24912104Snathanael.premillieu@arm.com std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2509046SAli.Saidi@ARM.com 2519046SAli.Saidi@ARM.com /** Physical register index of the destination registers of this 2529046SAli.Saidi@ARM.com * instruction. 2539046SAli.Saidi@ARM.com */ 25412105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 2559046SAli.Saidi@ARM.com 2569046SAli.Saidi@ARM.com /** Physical register index of the source registers of this 2579046SAli.Saidi@ARM.com * instruction. 2589046SAli.Saidi@ARM.com */ 25912105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 2609046SAli.Saidi@ARM.com 2619046SAli.Saidi@ARM.com /** Physical register index of the previous producers of the 2629046SAli.Saidi@ARM.com * architected destinations. 2639046SAli.Saidi@ARM.com */ 26412105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2659046SAli.Saidi@ARM.com 2669046SAli.Saidi@ARM.com 2679046SAli.Saidi@ARM.com public: 2689046SAli.Saidi@ARM.com /** Records changes to result? */ 2699046SAli.Saidi@ARM.com void recordResult(bool f) { instFlags[RecordResult] = f; } 2709046SAli.Saidi@ARM.com 2719046SAli.Saidi@ARM.com /** Is the effective virtual address valid. */ 2729046SAli.Saidi@ARM.com bool effAddrValid() const { return instFlags[EffAddrValid]; } 2739046SAli.Saidi@ARM.com 2749046SAli.Saidi@ARM.com /** Whether or not the memory operation is done. */ 2759046SAli.Saidi@ARM.com bool memOpDone() const { return instFlags[MemOpDone]; } 2769046SAli.Saidi@ARM.com void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2779046SAli.Saidi@ARM.com 27812421Sgabeblack@google.com bool notAnInst() const { return instFlags[NotAnInst]; } 27912421Sgabeblack@google.com void setNotAnInst() { instFlags[NotAnInst] = true; } 28012421Sgabeblack@google.com 2819046SAli.Saidi@ARM.com 2821060SN/A //////////////////////////////////////////// 2831060SN/A // 2841060SN/A // INSTRUCTION EXECUTION 2851060SN/A // 2861060SN/A //////////////////////////////////////////// 2871060SN/A 2885358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2895358Sgblack@eecs.umich.edu { 2905358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2915358Sgblack@eecs.umich.edu } 2925358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2935358Sgblack@eecs.umich.edu { 2945358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2955358Sgblack@eecs.umich.edu } 2965358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2975358Sgblack@eecs.umich.edu { 2985358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2995358Sgblack@eecs.umich.edu } 3005358Sgblack@eecs.umich.edu 30111608Snikos.nikoleris@arm.com Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 3027520Sgblack@eecs.umich.edu 30311608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 30411608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res); 3057520Sgblack@eecs.umich.edu 3066974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 30712749Sgiacomo.travaglini@arm.com void splitRequest(const RequestPtr &req, RequestPtr &sreqLow, 3086974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 3096974Stjones1@inf.ed.ac.uk 3106973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 31112749Sgiacomo.travaglini@arm.com void initiateTranslation(const RequestPtr &req, const RequestPtr &sreqLow, 31212749Sgiacomo.travaglini@arm.com const RequestPtr &sreqHigh, uint64_t *res, 3136973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 3146973Stjones1@inf.ed.ac.uk 3156973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 3166973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 3171060SN/A 3187944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 3199046SAli.Saidi@ARM.com bool translationStarted() const { return instFlags[TranslationStarted]; } 3209046SAli.Saidi@ARM.com void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3217944SGiacomo.Gabrielli@arm.com 3227944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 3239046SAli.Saidi@ARM.com bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3249046SAli.Saidi@ARM.com void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3257944SGiacomo.Gabrielli@arm.com 3268545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 3278545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 3288545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3298545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 3308545Ssaidi@eecs.umich.edu */ 3319046SAli.Saidi@ARM.com bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3329046SAli.Saidi@ARM.com void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3338545Ssaidi@eecs.umich.edu 3348545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3358545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 3368545Ssaidi@eecs.umich.edu * reexecute 3378545Ssaidi@eecs.umich.edu */ 3389046SAli.Saidi@ARM.com bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3399046SAli.Saidi@ARM.com void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3408545Ssaidi@eecs.umich.edu 3417944SGiacomo.Gabrielli@arm.com /** 3427944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 3437944SGiacomo.Gabrielli@arm.com * page table walk. 3447944SGiacomo.Gabrielli@arm.com */ 3457944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 3467944SGiacomo.Gabrielli@arm.com { 3479046SAli.Saidi@ARM.com return (translationStarted() && !translationCompleted()); 3487944SGiacomo.Gabrielli@arm.com } 3497944SGiacomo.Gabrielli@arm.com 3501060SN/A public: 3512292SN/A#ifdef DEBUG 3522292SN/A void dumpSNList(); 3532292SN/A#endif 3542292SN/A 3553770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3563770Sgblack@eecs.umich.edu * register. 3573770Sgblack@eecs.umich.edu */ 35812105Snathanael.premillieu@arm.com PhysRegIdPtr renamedDestRegIdx(int idx) const 3593770Sgblack@eecs.umich.edu { 3603770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3613770Sgblack@eecs.umich.edu } 3623770Sgblack@eecs.umich.edu 3633770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 36412105Snathanael.premillieu@arm.com PhysRegIdPtr renamedSrcRegIdx(int idx) const 3653770Sgblack@eecs.umich.edu { 3669046SAli.Saidi@ARM.com assert(TheISA::MaxInstSrcRegs > idx); 3673770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3683770Sgblack@eecs.umich.edu } 3693770Sgblack@eecs.umich.edu 3703770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3713770Sgblack@eecs.umich.edu * register. 3723770Sgblack@eecs.umich.edu */ 37312106SRekai.GonzalezAlberquilla@arm.com const RegId& flattenedDestRegIdx(int idx) const 3743770Sgblack@eecs.umich.edu { 3753770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3763770Sgblack@eecs.umich.edu } 3773770Sgblack@eecs.umich.edu 3783770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3793770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3803770Sgblack@eecs.umich.edu */ 38112105Snathanael.premillieu@arm.com PhysRegIdPtr prevDestRegIdx(int idx) const 3823770Sgblack@eecs.umich.edu { 3833770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3843770Sgblack@eecs.umich.edu } 3853770Sgblack@eecs.umich.edu 3863770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3873770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3883770Sgblack@eecs.umich.edu */ 3893770Sgblack@eecs.umich.edu void renameDestReg(int idx, 39012105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_dest, 39112105Snathanael.premillieu@arm.com PhysRegIdPtr previous_rename) 3923770Sgblack@eecs.umich.edu { 3933770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3943770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3953770Sgblack@eecs.umich.edu } 3963770Sgblack@eecs.umich.edu 3973770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3983770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3993770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 4003770Sgblack@eecs.umich.edu */ 40112105Snathanael.premillieu@arm.com void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 4023770Sgblack@eecs.umich.edu { 4033770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 4043770Sgblack@eecs.umich.edu } 4053770Sgblack@eecs.umich.edu 4063770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 4073770Sgblack@eecs.umich.edu * index. 4083770Sgblack@eecs.umich.edu */ 40912106SRekai.GonzalezAlberquilla@arm.com void flattenDestReg(int idx, const RegId& flattened_dest) 4103770Sgblack@eecs.umich.edu { 4113770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 4123770Sgblack@eecs.umich.edu } 4134636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 4144636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 4157720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 4167720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 4174636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 4184636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4194636Sgblack@eecs.umich.edu */ 42010417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 4218502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4228502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4233770Sgblack@eecs.umich.edu 4242292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4252292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4262292SN/A */ 42710417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 4281060SN/A 4291060SN/A /** BaseDynInst destructor. */ 4301060SN/A ~BaseDynInst(); 4311060SN/A 4321464SN/A private: 4331684SN/A /** Function to initialize variables in the constructors. */ 4341464SN/A void initVars(); 4351060SN/A 4361464SN/A public: 4371060SN/A /** Dumps out contents of this BaseDynInst. */ 4381060SN/A void dump(); 4391060SN/A 4401060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4411060SN/A void dump(std::string &outstring); 4421060SN/A 4433326Sktlim@umich.edu /** Read this CPU's ID. */ 44410110Sandreas.hansson@arm.com int cpuId() const { return cpu->cpuId(); } 4453326Sktlim@umich.edu 44610190Sakash.bagdia@arm.com /** Read this CPU's Socket ID. */ 44710190Sakash.bagdia@arm.com uint32_t socketId() const { return cpu->socketId(); } 44810190Sakash.bagdia@arm.com 4498832SAli.Saidi@ARM.com /** Read this CPU's data requestor ID */ 45010110Sandreas.hansson@arm.com MasterID masterId() const { return cpu->dataMasterId(); } 4518832SAli.Saidi@ARM.com 4525714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 45311005Sandreas.sandberg@arm.com ContextID contextId() const { return thread->contextId(); } 4545714Shsul@eecs.umich.edu 4551060SN/A /** Returns the fault type. */ 45610110Sandreas.hansson@arm.com Fault getFault() const { return fault; } 4571060SN/A 4581060SN/A /** Checks whether or not this instruction has had its branch target 4591060SN/A * calculated yet. For now it is not utilized and is hacked to be 4601060SN/A * always false. 4612292SN/A * @todo: Actually use this instruction. 4621060SN/A */ 4631060SN/A bool doneTargCalc() { return false; } 4641060SN/A 4657720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4667720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4673965Sgblack@eecs.umich.edu { 4687720Sgblack@eecs.umich.edu predPC = _predPC; 4693965Sgblack@eecs.umich.edu } 4702935Sksewell@umich.edu 4717720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4721060SN/A 4733794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4747720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4753794Sgblack@eecs.umich.edu 4763794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4777720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4781060SN/A 4794636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4807720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4814636Sgblack@eecs.umich.edu 4821060SN/A /** Returns whether the instruction was predicted taken or not. */ 4833794Sgblack@eecs.umich.edu bool readPredTaken() 4843794Sgblack@eecs.umich.edu { 4859046SAli.Saidi@ARM.com return instFlags[PredTaken]; 4863794Sgblack@eecs.umich.edu } 4873794Sgblack@eecs.umich.edu 4883794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4893794Sgblack@eecs.umich.edu { 4909046SAli.Saidi@ARM.com instFlags[PredTaken] = predicted_taken; 4913794Sgblack@eecs.umich.edu } 4921060SN/A 4931060SN/A /** Returns whether the instruction mispredicted. */ 4942935Sksewell@umich.edu bool mispredicted() 4953794Sgblack@eecs.umich.edu { 4967720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4977720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4987720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4993794Sgblack@eecs.umich.edu } 5003794Sgblack@eecs.umich.edu 5011060SN/A // 5021060SN/A // Instruction types. Forward checks to StaticInst object. 5031060SN/A // 5045543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5055543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5065543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5075543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5082336SN/A bool isStoreConditional() const 5092336SN/A { return staticInst->isStoreConditional(); } 5101060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5111060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5125543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5135543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 51412110SRekai.GonzalezAlberquilla@arm.com bool isVector() const { return staticInst->isVector(); } 5155543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5165543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5175543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5185543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5191060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5205543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5215543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5222935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5231060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5241060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5252292SN/A bool isSerializeBefore() const 5262731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5272292SN/A bool isSerializeAfter() const 5282731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5297784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5301060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5311060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5321060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5332292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5342336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5352308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5364828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5374654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5384654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5394636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5404654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5414654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5424636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5432292SN/A 5442292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5452731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5462292SN/A 5472292SN/A /** Clears the serializeBefore part of this instruction. */ 5482731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5492292SN/A 5502292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5512731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5522292SN/A 5532292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5542731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5552292SN/A 5562292SN/A /** Clears the serializeAfter part of this instruction.*/ 5572731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5582292SN/A 5592292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5602731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5612292SN/A 5622731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5632731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5642292SN/A 5652292SN/A /** Checks if the serialization part of this instruction has been 5662292SN/A * handled. This does not apply to the temporary serializing 5672292SN/A * state; it only applies to this instruction's own permanent 5682292SN/A * serializing state. 5692292SN/A */ 5702731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5711060SN/A 5721464SN/A /** Returns the opclass of this instruction. */ 5731464SN/A OpClass opClass() const { return staticInst->opClass(); } 5741464SN/A 5751464SN/A /** Returns the branch target address. */ 5767720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5777720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5781464SN/A 5792292SN/A /** Returns the number of source registers. */ 5805543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5811684SN/A 5822292SN/A /** Returns the number of destination registers. */ 5831060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5841060SN/A 5851060SN/A // the following are used to track physical register usage 5861060SN/A // for machines with separate int & FP reg files 5871060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5881060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 58910715SRekai.GonzalezAlberquilla@arm.com int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 59012109SRekai.GonzalezAlberquilla@arm.com int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 59112109SRekai.GonzalezAlberquilla@arm.com int8_t numVecElemDestRegs() const { 59212109SRekai.GonzalezAlberquilla@arm.com return staticInst->numVecElemDestRegs(); 59312109SRekai.GonzalezAlberquilla@arm.com } 5941060SN/A 5951060SN/A /** Returns the logical register index of the i'th destination register. */ 59612106SRekai.GonzalezAlberquilla@arm.com const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5971060SN/A 5981060SN/A /** Returns the logical register index of the i'th source register. */ 59912106SRekai.GonzalezAlberquilla@arm.com const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 6001060SN/A 60112107SRekai.GonzalezAlberquilla@arm.com /** Return the size of the instResult queue. */ 60212107SRekai.GonzalezAlberquilla@arm.com uint8_t resultSize() { return instResult.size(); } 60312107SRekai.GonzalezAlberquilla@arm.com 60412107SRekai.GonzalezAlberquilla@arm.com /** Pops a result off the instResult queue. 60512107SRekai.GonzalezAlberquilla@arm.com * If the result stack is empty, return the default value. 60612107SRekai.GonzalezAlberquilla@arm.com * */ 60712107SRekai.GonzalezAlberquilla@arm.com InstResult popResult(InstResult dflt = InstResult()) 6088733Sgeoffrey.blake@arm.com { 6098733Sgeoffrey.blake@arm.com if (!instResult.empty()) { 61012107SRekai.GonzalezAlberquilla@arm.com InstResult t = instResult.front(); 6118733Sgeoffrey.blake@arm.com instResult.pop(); 61212107SRekai.GonzalezAlberquilla@arm.com return t; 6138733Sgeoffrey.blake@arm.com } 61412107SRekai.GonzalezAlberquilla@arm.com return dflt; 6158733Sgeoffrey.blake@arm.com } 6161684SN/A 61712107SRekai.GonzalezAlberquilla@arm.com /** Pushes a result onto the instResult queue. */ 61812109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 61912109SRekai.GonzalezAlberquilla@arm.com /** Scalar result. */ 62012107SRekai.GonzalezAlberquilla@arm.com template<typename T> 62112107SRekai.GonzalezAlberquilla@arm.com void setScalarResult(T&& t) 6228733Sgeoffrey.blake@arm.com { 6239046SAli.Saidi@ARM.com if (instFlags[RecordResult]) { 62412107SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 62512107SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::Scalar)); 6268733Sgeoffrey.blake@arm.com } 6278733Sgeoffrey.blake@arm.com } 6281060SN/A 62912109SRekai.GonzalezAlberquilla@arm.com /** Full vector result. */ 63012109SRekai.GonzalezAlberquilla@arm.com template<typename T> 63112109SRekai.GonzalezAlberquilla@arm.com void setVecResult(T&& t) 63212109SRekai.GonzalezAlberquilla@arm.com { 63312109SRekai.GonzalezAlberquilla@arm.com if (instFlags[RecordResult]) { 63412109SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 63512109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecReg)); 63612109SRekai.GonzalezAlberquilla@arm.com } 63712109SRekai.GonzalezAlberquilla@arm.com } 63812109SRekai.GonzalezAlberquilla@arm.com 63912109SRekai.GonzalezAlberquilla@arm.com /** Vector element result. */ 64012109SRekai.GonzalezAlberquilla@arm.com template<typename T> 64112109SRekai.GonzalezAlberquilla@arm.com void setVecElemResult(T&& t) 64212109SRekai.GonzalezAlberquilla@arm.com { 64312109SRekai.GonzalezAlberquilla@arm.com if (instFlags[RecordResult]) { 64412109SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 64512109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecElem)); 64612109SRekai.GonzalezAlberquilla@arm.com } 64712109SRekai.GonzalezAlberquilla@arm.com } 64812109SRekai.GonzalezAlberquilla@arm.com /** @} */ 64912109SRekai.GonzalezAlberquilla@arm.com 6502702Sktlim@umich.edu /** Records an integer register being set to a value. */ 65110319SAndreas.Sandberg@ARM.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 6521060SN/A { 65312107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6541060SN/A } 6551060SN/A 6569920Syasuko.eckert@amd.com /** Records a CC register being set to a value. */ 65710319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 6589920Syasuko.eckert@amd.com { 65912107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6609920Syasuko.eckert@amd.com } 6619920Syasuko.eckert@amd.com 6622702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6633735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6641060SN/A { 66512107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6662308SN/A } 6671060SN/A 66812109SRekai.GonzalezAlberquilla@arm.com /** Record a vector register being set to a value */ 66912109SRekai.GonzalezAlberquilla@arm.com void setVecRegOperand(const StaticInst *si, int idx, 67012109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) 67112109SRekai.GonzalezAlberquilla@arm.com { 67212109SRekai.GonzalezAlberquilla@arm.com setVecResult(val); 67312109SRekai.GonzalezAlberquilla@arm.com } 67412109SRekai.GonzalezAlberquilla@arm.com 6752702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 67612107SRekai.GonzalezAlberquilla@arm.com void 67712107SRekai.GonzalezAlberquilla@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 6782308SN/A { 67912107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6801060SN/A } 6811060SN/A 68212109SRekai.GonzalezAlberquilla@arm.com /** Record a vector register being set to a value */ 68312109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 68412109SRekai.GonzalezAlberquilla@arm.com { 68512109SRekai.GonzalezAlberquilla@arm.com setVecElemResult(val); 68612109SRekai.GonzalezAlberquilla@arm.com } 68712109SRekai.GonzalezAlberquilla@arm.com 6882190SN/A /** Records that one of the source registers is ready. */ 6892292SN/A void markSrcRegReady(); 6902190SN/A 6912331SN/A /** Marks a specific register as ready. */ 6922292SN/A void markSrcRegReady(RegIndex src_idx); 6932190SN/A 6941684SN/A /** Returns if a source register is ready. */ 6951464SN/A bool isReadySrcRegIdx(int idx) const 6961464SN/A { 6971464SN/A return this->_readySrcRegIdx[idx]; 6981464SN/A } 6991464SN/A 7001684SN/A /** Sets this instruction as completed. */ 7012731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 7021464SN/A 7032292SN/A /** Returns whether or not this instruction is completed. */ 7042731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 7051464SN/A 7062731Sktlim@umich.edu /** Marks the result as ready. */ 7072731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 7082308SN/A 7092731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 7102731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 7112308SN/A 7121060SN/A /** Sets this instruction as ready to issue. */ 7132731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 7141060SN/A 7151060SN/A /** Returns whether or not this instruction is ready to issue. */ 7162731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 7171060SN/A 7184032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 7194032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 7204032Sktlim@umich.edu 7211060SN/A /** Sets this instruction as issued from the IQ. */ 7222731Sktlim@umich.edu void setIssued() { status.set(Issued); } 7231060SN/A 7241060SN/A /** Returns whether or not this instruction has issued. */ 7252731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 7261060SN/A 7274032Sktlim@umich.edu /** Clears this instruction as being issued. */ 7284032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 7294032Sktlim@umich.edu 7301060SN/A /** Sets this instruction as executed. */ 7312731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 7321060SN/A 7331060SN/A /** Returns whether or not this instruction has executed. */ 7342731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 7351060SN/A 7361060SN/A /** Sets this instruction as ready to commit. */ 7372731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7381060SN/A 7391061SN/A /** Clears this instruction as being ready to commit. */ 7402731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 7411061SN/A 7421060SN/A /** Returns whether or not this instruction is ready to commit. */ 7432731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7442731Sktlim@umich.edu 7452731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7462731Sktlim@umich.edu 7472731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7481060SN/A 7492292SN/A /** Sets this instruction as committed. */ 7502731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7512292SN/A 7522292SN/A /** Returns whether or not this instruction is committed. */ 7532731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7542292SN/A 7551060SN/A /** Sets this instruction as squashed. */ 7562731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7571060SN/A 7581060SN/A /** Returns whether or not this instruction is squashed. */ 7592731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7601060SN/A 7612292SN/A //Instruction Queue Entry 7622292SN/A //----------------------- 7632292SN/A /** Sets this instruction as a entry the IQ. */ 7642731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7652292SN/A 7662292SN/A /** Sets this instruction as a entry the IQ. */ 7672731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7682731Sktlim@umich.edu 7692731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7702731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7712292SN/A 7721060SN/A /** Sets this instruction as squashed in the IQ. */ 7732731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7741060SN/A 7751060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7762731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7772292SN/A 7782292SN/A 7792292SN/A //Load / Store Queue Functions 7802292SN/A //----------------------- 7812292SN/A /** Sets this instruction as a entry the LSQ. */ 7822731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7832292SN/A 7842292SN/A /** Sets this instruction as a entry the LSQ. */ 7852731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7862731Sktlim@umich.edu 7872731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7882731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7892292SN/A 7902292SN/A /** Sets this instruction as squashed in the LSQ. */ 7912731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7922292SN/A 7932292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7942731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7952292SN/A 7962292SN/A 7972292SN/A //Reorder Buffer Functions 7982292SN/A //----------------------- 7992292SN/A /** Sets this instruction as a entry the ROB. */ 8002731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 8012292SN/A 8022292SN/A /** Sets this instruction as a entry the ROB. */ 8032731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 8042731Sktlim@umich.edu 8052731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 8062731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 8072292SN/A 8082292SN/A /** Sets this instruction as squashed in the ROB. */ 8092731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 8102292SN/A 8112292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 8122731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 8132292SN/A 8147720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 81510319SAndreas.Sandberg@ARM.com TheISA::PCState pcState() const { return pc; } 8167720Sgblack@eecs.umich.edu 8177720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 81810319SAndreas.Sandberg@ARM.com void pcState(const TheISA::PCState &val) { pc = val; } 8197720Sgblack@eecs.umich.edu 8201060SN/A /** Read the PC of this instruction. */ 82111294Sandreas.hansson@arm.com Addr instAddr() const { return pc.instAddr(); } 8227720Sgblack@eecs.umich.edu 8237720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 82411294Sandreas.hansson@arm.com Addr nextInstAddr() const { return pc.nextInstAddr(); } 8251060SN/A 8264636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 82711294Sandreas.hansson@arm.com Addr microPC() const { return pc.microPC(); } 8284636Sgblack@eecs.umich.edu 8297597Sminkyu.jeong@arm.com bool readPredicate() 8307597Sminkyu.jeong@arm.com { 8319046SAli.Saidi@ARM.com return instFlags[Predicate]; 8327597Sminkyu.jeong@arm.com } 8337597Sminkyu.jeong@arm.com 8347597Sminkyu.jeong@arm.com void setPredicate(bool val) 8357597Sminkyu.jeong@arm.com { 8369046SAli.Saidi@ARM.com instFlags[Predicate] = val; 8377600Sminkyu.jeong@arm.com 8387600Sminkyu.jeong@arm.com if (traceData) { 8397600Sminkyu.jeong@arm.com traceData->setPredicate(val); 8407600Sminkyu.jeong@arm.com } 8417597Sminkyu.jeong@arm.com } 8427597Sminkyu.jeong@arm.com 8432702Sktlim@umich.edu /** Sets the ASID. */ 8442292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8452292SN/A 8462702Sktlim@umich.edu /** Sets the thread id. */ 8476221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8482292SN/A 8492731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8502702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8511060SN/A 8522731Sktlim@umich.edu /** Returns the thread context. */ 8532680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8541464SN/A 8551464SN/A public: 8561684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8571464SN/A bool eaSrcsReady(); 8581681SN/A 85910824SAndreas.Sandberg@ARM.com /** Is this instruction's memory access strictly ordered? */ 86010824SAndreas.Sandberg@ARM.com bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 8614032Sktlim@umich.edu 8624032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8639046SAli.Saidi@ARM.com bool hasRequest() { return instFlags[ReqMade]; } 8642292SN/A 8652292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8662292SN/A ListIt &getInstListIt() { return instListIt; } 8672292SN/A 8682292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8692292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8703326Sktlim@umich.edu 8713326Sktlim@umich.edu public: 8723326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 87310319SAndreas.Sandberg@ARM.com unsigned int readStCondFailures() const 8743326Sktlim@umich.edu { return thread->storeCondFailures; } 8753326Sktlim@umich.edu 8763326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 87710319SAndreas.Sandberg@ARM.com void setStCondFailures(unsigned int sc_failures) 8783326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 87910529Smorr@cs.wisc.edu 88010529Smorr@cs.wisc.edu public: 88110529Smorr@cs.wisc.edu // monitor/mwait funtions 88211148Smitch.hayenga@arm.com void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 88311148Smitch.hayenga@arm.com bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 88410529Smorr@cs.wisc.edu void mwaitAtomic(ThreadContext *tc) 88511148Smitch.hayenga@arm.com { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 88611148Smitch.hayenga@arm.com AddressMonitor *getAddrMonitor() 88711148Smitch.hayenga@arm.com { return cpu->getCpuAddrMonitor(threadNumber); } 8881060SN/A}; 8891060SN/A 8901060SN/Atemplate<class Impl> 8917520Sgblack@eecs.umich.eduFault 89211608Snikos.nikoleris@arm.comBaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 89311608Snikos.nikoleris@arm.com Request::Flags flags) 8941060SN/A{ 8959046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 89612748Sgiacomo.travaglini@arm.com RequestPtr req = NULL; 89712748Sgiacomo.travaglini@arm.com RequestPtr sreqLow = NULL; 89812748Sgiacomo.travaglini@arm.com RequestPtr sreqHigh = NULL; 8996974Stjones1@inf.ed.ac.uk 9009046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 9017944SGiacomo.Gabrielli@arm.com req = savedReq; 9027944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9037944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9047944SGiacomo.Gabrielli@arm.com } else { 90512749Sgiacomo.travaglini@arm.com req = std::make_shared<Request>( 90612749Sgiacomo.travaglini@arm.com asid, addr, size, flags, masterId(), 90712749Sgiacomo.travaglini@arm.com this->pc.instAddr(), thread->contextId()); 9084032Sktlim@umich.edu 90910024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 91010024Sdam.sunwoo@arm.com 9117944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9127944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9137944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9147944SGiacomo.Gabrielli@arm.com } 9157944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 9161060SN/A } 9171060SN/A 9189046SAli.Saidi@ARM.com if (translationCompleted()) { 9197944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 9207944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 9218199SAli.Saidi@ARM.com effSize = size; 9229046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9238887Sgeoffrey.blake@arm.com 9248887Sgeoffrey.blake@arm.com if (cpu->checker) { 92512749Sgiacomo.travaglini@arm.com reqToVerify = std::make_shared<Request>(*req); 9268733Sgeoffrey.blake@arm.com } 92711302Ssteve.reinhardt@amd.com fault = cpu->read(req, sreqLow, sreqHigh, lqIdx); 9287944SGiacomo.Gabrielli@arm.com } else { 9297944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 9307944SGiacomo.Gabrielli@arm.com // instruction as executed. 9317944SGiacomo.Gabrielli@arm.com this->setExecuted(); 9327944SGiacomo.Gabrielli@arm.com } 9337577SAli.Saidi@ARM.com } 9347577SAli.Saidi@ARM.com 93510665SAli.Saidi@ARM.com if (traceData) 93610665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 9371060SN/A 9381060SN/A return fault; 9391060SN/A} 9401060SN/A 9411060SN/Atemplate<class Impl> 9427520Sgblack@eecs.umich.eduFault 94311608Snikos.nikoleris@arm.comBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 94411608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 9451060SN/A{ 94610665SAli.Saidi@ARM.com if (traceData) 94710665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 9481060SN/A 9499046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 95012748Sgiacomo.travaglini@arm.com RequestPtr req = NULL; 95112748Sgiacomo.travaglini@arm.com RequestPtr sreqLow = NULL; 95212748Sgiacomo.travaglini@arm.com RequestPtr sreqHigh = NULL; 9536974Stjones1@inf.ed.ac.uk 9549046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 9557944SGiacomo.Gabrielli@arm.com req = savedReq; 9567944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9577944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9587944SGiacomo.Gabrielli@arm.com } else { 95912749Sgiacomo.travaglini@arm.com req = std::make_shared<Request>( 96012749Sgiacomo.travaglini@arm.com asid, addr, size, flags, masterId(), 96112749Sgiacomo.travaglini@arm.com this->pc.instAddr(), thread->contextId()); 9627944SGiacomo.Gabrielli@arm.com 96310024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 96410024Sdam.sunwoo@arm.com 9657944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9667944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9677944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9687944SGiacomo.Gabrielli@arm.com } 9697944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9706974Stjones1@inf.ed.ac.uk } 9714032Sktlim@umich.edu 9729046SAli.Saidi@ARM.com if (fault == NoFault && translationCompleted()) { 9732678Sktlim@umich.edu effAddr = req->getVaddr(); 9748199SAli.Saidi@ARM.com effSize = size; 9759046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9768887Sgeoffrey.blake@arm.com 9778887Sgeoffrey.blake@arm.com if (cpu->checker) { 97812749Sgiacomo.travaglini@arm.com reqToVerify = std::make_shared<Request>(*req); 9798733Sgeoffrey.blake@arm.com } 9806975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9811060SN/A } 9821060SN/A 9831060SN/A return fault; 9841060SN/A} 9851060SN/A 9866973Stjones1@inf.ed.ac.uktemplate<class Impl> 9876973Stjones1@inf.ed.ac.ukinline void 98812749Sgiacomo.travaglini@arm.comBaseDynInst<Impl>::splitRequest(const RequestPtr &req, RequestPtr &sreqLow, 9896974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9906974Stjones1@inf.ed.ac.uk{ 9916974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9929814Sandreas.hansson@arm.com unsigned block_size = cpu->cacheLineSize(); 9936974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9946974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9956974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9966974Stjones1@inf.ed.ac.uk 9976974Stjones1@inf.ed.ac.uk // Spans two blocks. 9986974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9996974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 10006974Stjones1@inf.ed.ac.uk } 10016974Stjones1@inf.ed.ac.uk} 10026974Stjones1@inf.ed.ac.uk 10036974Stjones1@inf.ed.ac.uktemplate<class Impl> 10046974Stjones1@inf.ed.ac.ukinline void 100512749Sgiacomo.travaglini@arm.comBaseDynInst<Impl>::initiateTranslation(const RequestPtr &req, 100612749Sgiacomo.travaglini@arm.com const RequestPtr &sreqLow, 100712749Sgiacomo.travaglini@arm.com const RequestPtr &sreqHigh, 100812749Sgiacomo.travaglini@arm.com uint64_t *res, 10096973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 10106973Stjones1@inf.ed.ac.uk{ 10119046SAli.Saidi@ARM.com translationStarted(true); 10127944SGiacomo.Gabrielli@arm.com 10136974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10146974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10156974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10166974Stjones1@inf.ed.ac.uk 10176974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10188486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 10198486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 10209932SAli.Saidi@ARM.com 10216974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10229932SAli.Saidi@ARM.com 10239046SAli.Saidi@ARM.com if (!translationCompleted()) { 10249932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10259932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10269932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10279932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10289932SAli.Saidi@ARM.com fault = NoFault; 10299932SAli.Saidi@ARM.com 10307944SGiacomo.Gabrielli@arm.com // Save memory requests. 10317944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10327944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10337944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10347944SGiacomo.Gabrielli@arm.com } 10356974Stjones1@inf.ed.ac.uk } else { 10366974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10376974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10386974Stjones1@inf.ed.ac.uk 10396974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10408486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 10418486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 10428486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 10438486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 10446974Stjones1@inf.ed.ac.uk 10456974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10466974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10479932SAli.Saidi@ARM.com 10489046SAli.Saidi@ARM.com if (!translationCompleted()) { 10499932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10509932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10519932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10529932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10539932SAli.Saidi@ARM.com fault = NoFault; 10549932SAli.Saidi@ARM.com 10557944SGiacomo.Gabrielli@arm.com // Save memory requests. 10567944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10577944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10587944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10597944SGiacomo.Gabrielli@arm.com } 10606974Stjones1@inf.ed.ac.uk } 10616973Stjones1@inf.ed.ac.uk} 10626973Stjones1@inf.ed.ac.uk 10636973Stjones1@inf.ed.ac.uktemplate<class Impl> 10646973Stjones1@inf.ed.ac.ukinline void 10656973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10666973Stjones1@inf.ed.ac.uk{ 10676973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10686973Stjones1@inf.ed.ac.uk 106910824SAndreas.Sandberg@ARM.com instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 10706973Stjones1@inf.ed.ac.uk 10716973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 107211097Songal@cs.wisc.edu // save Paddr for a single req 107311097Songal@cs.wisc.edu physEffAddrLow = state->getPaddr(); 107411097Songal@cs.wisc.edu 107511097Songal@cs.wisc.edu // case for the request that has been split 107611097Songal@cs.wisc.edu if (state->isSplit) { 107711097Songal@cs.wisc.edu physEffAddrLow = state->sreqLow->getPaddr(); 107811097Songal@cs.wisc.edu physEffAddrHigh = state->sreqHigh->getPaddr(); 107911097Songal@cs.wisc.edu } 108011097Songal@cs.wisc.edu 10816973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10826973Stjones1@inf.ed.ac.uk 10836973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10846973Stjones1@inf.ed.ac.uk assert(state->res); 10856973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10866973Stjones1@inf.ed.ac.uk } 10876973Stjones1@inf.ed.ac.uk 10886973Stjones1@inf.ed.ac.uk } else { 10896973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10906973Stjones1@inf.ed.ac.uk } 10916973Stjones1@inf.ed.ac.uk delete state; 10927944SGiacomo.Gabrielli@arm.com 10939046SAli.Saidi@ARM.com translationCompleted(true); 10946973Stjones1@inf.ed.ac.uk} 10956973Stjones1@inf.ed.ac.uk 10961464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1097