base_dyn_inst.hh revision 10190
11060SN/A/* 29814Sandreas.hansson@arm.com * Copyright (c) 2011,2013 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 166973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 171060SN/A * All rights reserved. 181060SN/A * 191060SN/A * Redistribution and use in source and binary forms, with or without 201060SN/A * modification, are permitted provided that the following conditions are 211060SN/A * met: redistributions of source code must retain the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer; 231060SN/A * redistributions in binary form must reproduce the above copyright 241060SN/A * notice, this list of conditions and the following disclaimer in the 251060SN/A * documentation and/or other materials provided with the distribution; 261060SN/A * neither the name of the copyright holders nor the names of its 271060SN/A * contributors may be used to endorse or promote products derived from 281060SN/A * this software without specific prior written permission. 291060SN/A * 301060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 436973Stjones1@inf.ed.ac.uk * Timothy M. Jones 441060SN/A */ 451060SN/A 461464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 471464SN/A#define __CPU_BASE_DYN_INST_HH__ 481060SN/A 492731Sktlim@umich.edu#include <bitset> 502292SN/A#include <list> 511464SN/A#include <string> 528733Sgeoffrey.blake@arm.com#include <queue> 531060SN/A 547720Sgblack@eecs.umich.edu#include "arch/utility.hh" 551060SN/A#include "base/trace.hh" 566658Snate@binkert.org#include "config/the_isa.hh" 578887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 583770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 591464SN/A#include "cpu/exetrace.hh" 601464SN/A#include "cpu/inst_seq.hh" 612669Sktlim@umich.edu#include "cpu/op_class.hh" 621060SN/A#include "cpu/static_inst.hh" 636973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 642669Sktlim@umich.edu#include "mem/packet.hh" 657678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 668817Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 672292SN/A#include "sim/system.hh" 686023Snate@binkert.org#include "sim/tlb.hh" 691060SN/A 701060SN/A/** 711060SN/A * @file 721060SN/A * Defines a dynamic instruction context. 731060SN/A */ 741060SN/A 751060SN/Atemplate <class Impl> 769044SAli.Saidi@ARM.comclass BaseDynInst : public RefCounted 771060SN/A{ 781060SN/A public: 791060SN/A // Typedef for the CPU. 802733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 812733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 821060SN/A 832292SN/A // Logical register index type. 842107SN/A typedef TheISA::RegIndex RegIndex; 852690Sktlim@umich.edu // Integer register type. 862107SN/A typedef TheISA::IntReg IntReg; 872690Sktlim@umich.edu // Floating point register type. 882690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 891060SN/A 902292SN/A // The DynInstPtr type. 912292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 928486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 932292SN/A 942292SN/A // The list of instructions iterator type. 952292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 962292SN/A 971060SN/A enum { 985543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 998902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 1001060SN/A }; 1011060SN/A 1029046SAli.Saidi@ARM.com union Result { 1039046SAli.Saidi@ARM.com uint64_t integer; 1049046SAli.Saidi@ARM.com double dbl; 1059046SAli.Saidi@ARM.com void set(uint64_t i) { integer = i; } 1069046SAli.Saidi@ARM.com void set(double d) { dbl = d; } 1079046SAli.Saidi@ARM.com void get(uint64_t& i) { i = integer; } 1089046SAli.Saidi@ARM.com void get(double& d) { d = dbl; } 1099046SAli.Saidi@ARM.com }; 1109046SAli.Saidi@ARM.com 1119046SAli.Saidi@ARM.com protected: 1129046SAli.Saidi@ARM.com enum Status { 1139046SAli.Saidi@ARM.com IqEntry, /// Instruction is in the IQ 1149046SAli.Saidi@ARM.com RobEntry, /// Instruction is in the ROB 1159046SAli.Saidi@ARM.com LsqEntry, /// Instruction is in the LSQ 1169046SAli.Saidi@ARM.com Completed, /// Instruction has completed 1179046SAli.Saidi@ARM.com ResultReady, /// Instruction has its result 1189046SAli.Saidi@ARM.com CanIssue, /// Instruction can issue and execute 1199046SAli.Saidi@ARM.com Issued, /// Instruction has issued 1209046SAli.Saidi@ARM.com Executed, /// Instruction has executed 1219046SAli.Saidi@ARM.com CanCommit, /// Instruction can commit 1229046SAli.Saidi@ARM.com AtCommit, /// Instruction has reached commit 1239046SAli.Saidi@ARM.com Committed, /// Instruction has committed 1249046SAli.Saidi@ARM.com Squashed, /// Instruction is squashed 1259046SAli.Saidi@ARM.com SquashedInIQ, /// Instruction is squashed in the IQ 1269046SAli.Saidi@ARM.com SquashedInLSQ, /// Instruction is squashed in the LSQ 1279046SAli.Saidi@ARM.com SquashedInROB, /// Instruction is squashed in the ROB 1289046SAli.Saidi@ARM.com RecoverInst, /// Is a recover instruction 1299046SAli.Saidi@ARM.com BlockingInst, /// Is a blocking instruction 1309046SAli.Saidi@ARM.com ThreadsyncWait, /// Is a thread synchronization instruction 1319046SAli.Saidi@ARM.com SerializeBefore, /// Needs to serialize on 1329046SAli.Saidi@ARM.com /// instructions ahead of it 1339046SAli.Saidi@ARM.com SerializeAfter, /// Needs to serialize instructions behind it 1349046SAli.Saidi@ARM.com SerializeHandled, /// Serialization has been handled 1359046SAli.Saidi@ARM.com NumStatus 1369046SAli.Saidi@ARM.com }; 1379046SAli.Saidi@ARM.com 1389046SAli.Saidi@ARM.com enum Flags { 1399046SAli.Saidi@ARM.com TranslationStarted, 1409046SAli.Saidi@ARM.com TranslationCompleted, 1419046SAli.Saidi@ARM.com PossibleLoadViolation, 1429046SAli.Saidi@ARM.com HitExternalSnoop, 1439046SAli.Saidi@ARM.com EffAddrValid, 1449046SAli.Saidi@ARM.com RecordResult, 1459046SAli.Saidi@ARM.com Predicate, 1469046SAli.Saidi@ARM.com PredTaken, 1479046SAli.Saidi@ARM.com /** Whether or not the effective address calculation is completed. 1489046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 1499046SAli.Saidi@ARM.com */ 1509046SAli.Saidi@ARM.com EACalcDone, 1519046SAli.Saidi@ARM.com IsUncacheable, 1529046SAli.Saidi@ARM.com ReqMade, 1539046SAli.Saidi@ARM.com MemOpDone, 1549046SAli.Saidi@ARM.com MaxFlags 1559046SAli.Saidi@ARM.com }; 1569046SAli.Saidi@ARM.com 1579046SAli.Saidi@ARM.com public: 1589046SAli.Saidi@ARM.com /** The sequence number of the instruction. */ 1599046SAli.Saidi@ARM.com InstSeqNum seqNum; 1609046SAli.Saidi@ARM.com 1612292SN/A /** The StaticInst used by this BaseDynInst. */ 1622107SN/A StaticInstPtr staticInst; 1639046SAli.Saidi@ARM.com 1649046SAli.Saidi@ARM.com /** Pointer to the Impl's CPU object. */ 1659046SAli.Saidi@ARM.com ImplCPU *cpu; 1669046SAli.Saidi@ARM.com 16710030SAli.Saidi@ARM.com BaseCPU *getCpuPtr() { return cpu; } 16810030SAli.Saidi@ARM.com 1699046SAli.Saidi@ARM.com /** Pointer to the thread state. */ 1709046SAli.Saidi@ARM.com ImplState *thread; 1719046SAli.Saidi@ARM.com 1729046SAli.Saidi@ARM.com /** The kind of fault this instruction has generated. */ 1739046SAli.Saidi@ARM.com Fault fault; 1749046SAli.Saidi@ARM.com 1759046SAli.Saidi@ARM.com /** InstRecord that tracks this instructions. */ 1769046SAli.Saidi@ARM.com Trace::InstRecord *traceData; 1779046SAli.Saidi@ARM.com 1789046SAli.Saidi@ARM.com protected: 1799046SAli.Saidi@ARM.com /** The result of the instruction; assumes an instruction can have many 1809046SAli.Saidi@ARM.com * destination registers. 1819046SAli.Saidi@ARM.com */ 1829046SAli.Saidi@ARM.com std::queue<Result> instResult; 1839046SAli.Saidi@ARM.com 1849046SAli.Saidi@ARM.com /** PC state for this instruction. */ 1859046SAli.Saidi@ARM.com TheISA::PCState pc; 1869046SAli.Saidi@ARM.com 1879046SAli.Saidi@ARM.com /* An amalgamation of a lot of boolean values into one */ 1889046SAli.Saidi@ARM.com std::bitset<MaxFlags> instFlags; 1899046SAli.Saidi@ARM.com 1909046SAli.Saidi@ARM.com /** The status of this BaseDynInst. Several bits can be set. */ 1919046SAli.Saidi@ARM.com std::bitset<NumStatus> status; 1929046SAli.Saidi@ARM.com 1939046SAli.Saidi@ARM.com /** Whether or not the source register is ready. 1949046SAli.Saidi@ARM.com * @todo: Not sure this should be here vs the derived class. 1959046SAli.Saidi@ARM.com */ 1969046SAli.Saidi@ARM.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1979046SAli.Saidi@ARM.com 1989046SAli.Saidi@ARM.com public: 1999046SAli.Saidi@ARM.com /** The thread this instruction is from. */ 2009046SAli.Saidi@ARM.com ThreadID threadNumber; 2019046SAli.Saidi@ARM.com 2029046SAli.Saidi@ARM.com /** Iterator pointing to this BaseDynInst in the list of all insts. */ 2039046SAli.Saidi@ARM.com ListIt instListIt; 2049046SAli.Saidi@ARM.com 2059046SAli.Saidi@ARM.com ////////////////////// Branch Data /////////////// 2069046SAli.Saidi@ARM.com /** Predicted PC state after this instruction. */ 2079046SAli.Saidi@ARM.com TheISA::PCState predPC; 2089046SAli.Saidi@ARM.com 2099046SAli.Saidi@ARM.com /** The Macroop if one exists */ 2108502Sgblack@eecs.umich.edu StaticInstPtr macroop; 2111060SN/A 2129046SAli.Saidi@ARM.com /** How many source registers are ready. */ 2139046SAli.Saidi@ARM.com uint8_t readyRegs; 2149046SAli.Saidi@ARM.com 2159046SAli.Saidi@ARM.com public: 2169046SAli.Saidi@ARM.com /////////////////////// Load Store Data ////////////////////// 2179046SAli.Saidi@ARM.com /** The effective virtual address (lds & stores only). */ 2189046SAli.Saidi@ARM.com Addr effAddr; 2199046SAli.Saidi@ARM.com 2209046SAli.Saidi@ARM.com /** The effective physical address. */ 2219046SAli.Saidi@ARM.com Addr physEffAddr; 2229046SAli.Saidi@ARM.com 2239046SAli.Saidi@ARM.com /** The memory request flags (from translation). */ 2249046SAli.Saidi@ARM.com unsigned memReqFlags; 2259046SAli.Saidi@ARM.com 2269046SAli.Saidi@ARM.com /** data address space ID, for loads & stores. */ 2279046SAli.Saidi@ARM.com short asid; 2289046SAli.Saidi@ARM.com 2299046SAli.Saidi@ARM.com /** The size of the request */ 2309046SAli.Saidi@ARM.com uint8_t effSize; 2319046SAli.Saidi@ARM.com 2329046SAli.Saidi@ARM.com /** Pointer to the data for the memory access. */ 2339046SAli.Saidi@ARM.com uint8_t *memData; 2349046SAli.Saidi@ARM.com 2359046SAli.Saidi@ARM.com /** Load queue index. */ 2369046SAli.Saidi@ARM.com int16_t lqIdx; 2379046SAli.Saidi@ARM.com 2389046SAli.Saidi@ARM.com /** Store queue index. */ 2399046SAli.Saidi@ARM.com int16_t sqIdx; 2409046SAli.Saidi@ARM.com 2419046SAli.Saidi@ARM.com 2429046SAli.Saidi@ARM.com /////////////////////// TLB Miss ////////////////////// 2439046SAli.Saidi@ARM.com /** 2449046SAli.Saidi@ARM.com * Saved memory requests (needed when the DTB address translation is 2459046SAli.Saidi@ARM.com * delayed due to a hw page table walk). 2469046SAli.Saidi@ARM.com */ 2479046SAli.Saidi@ARM.com RequestPtr savedReq; 2489046SAli.Saidi@ARM.com RequestPtr savedSreqLow; 2499046SAli.Saidi@ARM.com RequestPtr savedSreqHigh; 2509046SAli.Saidi@ARM.com 2519046SAli.Saidi@ARM.com /////////////////////// Checker ////////////////////// 2529046SAli.Saidi@ARM.com // Need a copy of main request pointer to verify on writes. 2539046SAli.Saidi@ARM.com RequestPtr reqToVerify; 2549046SAli.Saidi@ARM.com 2559046SAli.Saidi@ARM.com private: 2569046SAli.Saidi@ARM.com /** Instruction effective address. 2579046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 2589046SAli.Saidi@ARM.com */ 2599046SAli.Saidi@ARM.com Addr instEffAddr; 2609046SAli.Saidi@ARM.com 2619046SAli.Saidi@ARM.com protected: 2629046SAli.Saidi@ARM.com /** Flattened register index of the destination registers of this 2639046SAli.Saidi@ARM.com * instruction. 2649046SAli.Saidi@ARM.com */ 2659046SAli.Saidi@ARM.com TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2669046SAli.Saidi@ARM.com 2679046SAli.Saidi@ARM.com /** Physical register index of the destination registers of this 2689046SAli.Saidi@ARM.com * instruction. 2699046SAli.Saidi@ARM.com */ 2709046SAli.Saidi@ARM.com PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2719046SAli.Saidi@ARM.com 2729046SAli.Saidi@ARM.com /** Physical register index of the source registers of this 2739046SAli.Saidi@ARM.com * instruction. 2749046SAli.Saidi@ARM.com */ 2759046SAli.Saidi@ARM.com PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2769046SAli.Saidi@ARM.com 2779046SAli.Saidi@ARM.com /** Physical register index of the previous producers of the 2789046SAli.Saidi@ARM.com * architected destinations. 2799046SAli.Saidi@ARM.com */ 2809046SAli.Saidi@ARM.com PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2819046SAli.Saidi@ARM.com 2829046SAli.Saidi@ARM.com 2839046SAli.Saidi@ARM.com public: 2849046SAli.Saidi@ARM.com /** Records changes to result? */ 2859046SAli.Saidi@ARM.com void recordResult(bool f) { instFlags[RecordResult] = f; } 2869046SAli.Saidi@ARM.com 2879046SAli.Saidi@ARM.com /** Is the effective virtual address valid. */ 2889046SAli.Saidi@ARM.com bool effAddrValid() const { return instFlags[EffAddrValid]; } 2899046SAli.Saidi@ARM.com 2909046SAli.Saidi@ARM.com /** Whether or not the memory operation is done. */ 2919046SAli.Saidi@ARM.com bool memOpDone() const { return instFlags[MemOpDone]; } 2929046SAli.Saidi@ARM.com void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2939046SAli.Saidi@ARM.com 2949046SAli.Saidi@ARM.com 2951060SN/A //////////////////////////////////////////// 2961060SN/A // 2971060SN/A // INSTRUCTION EXECUTION 2981060SN/A // 2991060SN/A //////////////////////////////////////////// 3001060SN/A 3015358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3025358Sgblack@eecs.umich.edu { 3035358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3045358Sgblack@eecs.umich.edu } 3055358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3065358Sgblack@eecs.umich.edu { 3075358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3085358Sgblack@eecs.umich.edu } 3095358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3105358Sgblack@eecs.umich.edu { 3115358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3125358Sgblack@eecs.umich.edu } 3135358Sgblack@eecs.umich.edu 3148444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3157520Sgblack@eecs.umich.edu 3168444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 3178444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 3187520Sgblack@eecs.umich.edu 3196974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 3206974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 3216974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 3226974Stjones1@inf.ed.ac.uk 3236973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 3246974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 3256974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 3266973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 3276973Stjones1@inf.ed.ac.uk 3286973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 3296973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 3301060SN/A 3317944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 3329046SAli.Saidi@ARM.com bool translationStarted() const { return instFlags[TranslationStarted]; } 3339046SAli.Saidi@ARM.com void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3347944SGiacomo.Gabrielli@arm.com 3357944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 3369046SAli.Saidi@ARM.com bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3379046SAli.Saidi@ARM.com void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3387944SGiacomo.Gabrielli@arm.com 3398545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 3408545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 3418545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3428545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 3438545Ssaidi@eecs.umich.edu */ 3449046SAli.Saidi@ARM.com bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3459046SAli.Saidi@ARM.com void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3468545Ssaidi@eecs.umich.edu 3478545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3488545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 3498545Ssaidi@eecs.umich.edu * reexecute 3508545Ssaidi@eecs.umich.edu */ 3519046SAli.Saidi@ARM.com bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3529046SAli.Saidi@ARM.com void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3538545Ssaidi@eecs.umich.edu 3547944SGiacomo.Gabrielli@arm.com /** 3557944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 3567944SGiacomo.Gabrielli@arm.com * page table walk. 3577944SGiacomo.Gabrielli@arm.com */ 3587944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 3597944SGiacomo.Gabrielli@arm.com { 3609046SAli.Saidi@ARM.com return (translationStarted() && !translationCompleted()); 3617944SGiacomo.Gabrielli@arm.com } 3627944SGiacomo.Gabrielli@arm.com 3631060SN/A public: 3642292SN/A#ifdef DEBUG 3652292SN/A void dumpSNList(); 3662292SN/A#endif 3672292SN/A 3683770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3693770Sgblack@eecs.umich.edu * register. 3703770Sgblack@eecs.umich.edu */ 3713770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3723770Sgblack@eecs.umich.edu { 3733770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3743770Sgblack@eecs.umich.edu } 3753770Sgblack@eecs.umich.edu 3763770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3773770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3783770Sgblack@eecs.umich.edu { 3799046SAli.Saidi@ARM.com assert(TheISA::MaxInstSrcRegs > idx); 3803770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3813770Sgblack@eecs.umich.edu } 3823770Sgblack@eecs.umich.edu 3833770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3843770Sgblack@eecs.umich.edu * register. 3853770Sgblack@eecs.umich.edu */ 3863770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3873770Sgblack@eecs.umich.edu { 3883770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3893770Sgblack@eecs.umich.edu } 3903770Sgblack@eecs.umich.edu 3913770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3923770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3933770Sgblack@eecs.umich.edu */ 3943770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3953770Sgblack@eecs.umich.edu { 3963770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3973770Sgblack@eecs.umich.edu } 3983770Sgblack@eecs.umich.edu 3993770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 4003770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 4013770Sgblack@eecs.umich.edu */ 4023770Sgblack@eecs.umich.edu void renameDestReg(int idx, 4033770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 4043770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 4053770Sgblack@eecs.umich.edu { 4063770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 4073770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 4083770Sgblack@eecs.umich.edu } 4093770Sgblack@eecs.umich.edu 4103770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 4113770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 4123770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 4133770Sgblack@eecs.umich.edu */ 4143770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 4153770Sgblack@eecs.umich.edu { 4163770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 4173770Sgblack@eecs.umich.edu } 4183770Sgblack@eecs.umich.edu 4193770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 4203770Sgblack@eecs.umich.edu * index. 4213770Sgblack@eecs.umich.edu */ 4223770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 4233770Sgblack@eecs.umich.edu { 4243770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 4253770Sgblack@eecs.umich.edu } 4264636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 4274636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 4287720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 4297720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 4304636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 4314636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4324636Sgblack@eecs.umich.edu */ 4338502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 4348502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4358502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4363770Sgblack@eecs.umich.edu 4372292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4382292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4392292SN/A */ 4408502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 4411060SN/A 4421060SN/A /** BaseDynInst destructor. */ 4431060SN/A ~BaseDynInst(); 4441060SN/A 4451464SN/A private: 4461684SN/A /** Function to initialize variables in the constructors. */ 4471464SN/A void initVars(); 4481060SN/A 4491464SN/A public: 4501060SN/A /** Dumps out contents of this BaseDynInst. */ 4511060SN/A void dump(); 4521060SN/A 4531060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4541060SN/A void dump(std::string &outstring); 4551060SN/A 4563326Sktlim@umich.edu /** Read this CPU's ID. */ 45710110Sandreas.hansson@arm.com int cpuId() const { return cpu->cpuId(); } 4583326Sktlim@umich.edu 45910190Sakash.bagdia@arm.com /** Read this CPU's Socket ID. */ 46010190Sakash.bagdia@arm.com uint32_t socketId() const { return cpu->socketId(); } 46110190Sakash.bagdia@arm.com 4628832SAli.Saidi@ARM.com /** Read this CPU's data requestor ID */ 46310110Sandreas.hansson@arm.com MasterID masterId() const { return cpu->dataMasterId(); } 4648832SAli.Saidi@ARM.com 4655714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 46610110Sandreas.hansson@arm.com int contextId() const { return thread->contextId(); } 4675714Shsul@eecs.umich.edu 4681060SN/A /** Returns the fault type. */ 46910110Sandreas.hansson@arm.com Fault getFault() const { return fault; } 4701060SN/A 4711060SN/A /** Checks whether or not this instruction has had its branch target 4721060SN/A * calculated yet. For now it is not utilized and is hacked to be 4731060SN/A * always false. 4742292SN/A * @todo: Actually use this instruction. 4751060SN/A */ 4761060SN/A bool doneTargCalc() { return false; } 4771060SN/A 4787720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4797720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4803965Sgblack@eecs.umich.edu { 4817720Sgblack@eecs.umich.edu predPC = _predPC; 4823965Sgblack@eecs.umich.edu } 4832935Sksewell@umich.edu 4847720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4851060SN/A 4863794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4877720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4883794Sgblack@eecs.umich.edu 4893794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4907720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4911060SN/A 4924636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4937720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4944636Sgblack@eecs.umich.edu 4951060SN/A /** Returns whether the instruction was predicted taken or not. */ 4963794Sgblack@eecs.umich.edu bool readPredTaken() 4973794Sgblack@eecs.umich.edu { 4989046SAli.Saidi@ARM.com return instFlags[PredTaken]; 4993794Sgblack@eecs.umich.edu } 5003794Sgblack@eecs.umich.edu 5013794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 5023794Sgblack@eecs.umich.edu { 5039046SAli.Saidi@ARM.com instFlags[PredTaken] = predicted_taken; 5043794Sgblack@eecs.umich.edu } 5051060SN/A 5061060SN/A /** Returns whether the instruction mispredicted. */ 5072935Sksewell@umich.edu bool mispredicted() 5083794Sgblack@eecs.umich.edu { 5097720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 5107720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 5117720Sgblack@eecs.umich.edu return !(tempPC == predPC); 5123794Sgblack@eecs.umich.edu } 5133794Sgblack@eecs.umich.edu 5141060SN/A // 5151060SN/A // Instruction types. Forward checks to StaticInst object. 5161060SN/A // 5175543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5185543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5195543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5205543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5212336SN/A bool isStoreConditional() const 5222336SN/A { return staticInst->isStoreConditional(); } 5231060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5241060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5255543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5265543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5275543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5285543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5295543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5305543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5311060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5325543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5335543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5342935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5351060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5361060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5372292SN/A bool isSerializeBefore() const 5382731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5392292SN/A bool isSerializeAfter() const 5402731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5417784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5421060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5431060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5441060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5452292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5462336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5472308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5484828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5494654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5504654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5514636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5524654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5534654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5544636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5552292SN/A 5562292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5572731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5582292SN/A 5592292SN/A /** Clears the serializeBefore part of this instruction. */ 5602731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5612292SN/A 5622292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5632731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5642292SN/A 5652292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5662731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5672292SN/A 5682292SN/A /** Clears the serializeAfter part of this instruction.*/ 5692731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5702292SN/A 5712292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5722731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5732292SN/A 5742731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5752731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5762292SN/A 5772292SN/A /** Checks if the serialization part of this instruction has been 5782292SN/A * handled. This does not apply to the temporary serializing 5792292SN/A * state; it only applies to this instruction's own permanent 5802292SN/A * serializing state. 5812292SN/A */ 5822731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5831060SN/A 5841464SN/A /** Returns the opclass of this instruction. */ 5851464SN/A OpClass opClass() const { return staticInst->opClass(); } 5861464SN/A 5871464SN/A /** Returns the branch target address. */ 5887720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5897720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5901464SN/A 5912292SN/A /** Returns the number of source registers. */ 5925543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5931684SN/A 5942292SN/A /** Returns the number of destination registers. */ 5951060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5961060SN/A 5971060SN/A // the following are used to track physical register usage 5981060SN/A // for machines with separate int & FP reg files 5991060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 6001060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 6011060SN/A 6021060SN/A /** Returns the logical register index of the i'th destination register. */ 6032292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 6041060SN/A 6051060SN/A /** Returns the logical register index of the i'th source register. */ 6062292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 6071060SN/A 6088733Sgeoffrey.blake@arm.com /** Pops a result off the instResult queue */ 6098733Sgeoffrey.blake@arm.com template <class T> 6108733Sgeoffrey.blake@arm.com void popResult(T& t) 6118733Sgeoffrey.blake@arm.com { 6128733Sgeoffrey.blake@arm.com if (!instResult.empty()) { 6138733Sgeoffrey.blake@arm.com instResult.front().get(t); 6148733Sgeoffrey.blake@arm.com instResult.pop(); 6158733Sgeoffrey.blake@arm.com } 6168733Sgeoffrey.blake@arm.com } 6171684SN/A 6188733Sgeoffrey.blake@arm.com /** Read the most recent result stored by this instruction */ 6198733Sgeoffrey.blake@arm.com template <class T> 6208733Sgeoffrey.blake@arm.com void readResult(T& t) 6218733Sgeoffrey.blake@arm.com { 6228733Sgeoffrey.blake@arm.com instResult.back().get(t); 6238733Sgeoffrey.blake@arm.com } 6241684SN/A 6258733Sgeoffrey.blake@arm.com /** Pushes a result onto the instResult queue */ 6268733Sgeoffrey.blake@arm.com template <class T> 6278733Sgeoffrey.blake@arm.com void setResult(T t) 6288733Sgeoffrey.blake@arm.com { 6299046SAli.Saidi@ARM.com if (instFlags[RecordResult]) { 6308733Sgeoffrey.blake@arm.com Result instRes; 6318733Sgeoffrey.blake@arm.com instRes.set(t); 6328733Sgeoffrey.blake@arm.com instResult.push(instRes); 6338733Sgeoffrey.blake@arm.com } 6348733Sgeoffrey.blake@arm.com } 6351060SN/A 6362702Sktlim@umich.edu /** Records an integer register being set to a value. */ 6373735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 6381060SN/A { 6398733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6401060SN/A } 6411060SN/A 6429920Syasuko.eckert@amd.com /** Records a CC register being set to a value. */ 6439920Syasuko.eckert@amd.com void setCCRegOperand(const StaticInst *si, int idx, uint64_t val) 6449920Syasuko.eckert@amd.com { 6459920Syasuko.eckert@amd.com setResult<uint64_t>(val); 6469920Syasuko.eckert@amd.com } 6479920Syasuko.eckert@amd.com 6482702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6493735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 6503735Sstever@eecs.umich.edu int width) 6512690Sktlim@umich.edu { 6528733Sgeoffrey.blake@arm.com if (width == 32 || width == 64) { 6538733Sgeoffrey.blake@arm.com setResult<double>(val); 6548733Sgeoffrey.blake@arm.com } else { 6558733Sgeoffrey.blake@arm.com panic("Unsupported width!"); 6563326Sktlim@umich.edu } 6572690Sktlim@umich.edu } 6582690Sktlim@umich.edu 6592702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6603735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6611060SN/A { 6628733Sgeoffrey.blake@arm.com setResult<double>(val); 6632308SN/A } 6641060SN/A 6652702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6663735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6673735Sstever@eecs.umich.edu int width) 6682308SN/A { 6698733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6702308SN/A } 6711060SN/A 6722702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6733735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6742308SN/A { 6758733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6761060SN/A } 6771060SN/A 6782190SN/A /** Records that one of the source registers is ready. */ 6792292SN/A void markSrcRegReady(); 6802190SN/A 6812331SN/A /** Marks a specific register as ready. */ 6822292SN/A void markSrcRegReady(RegIndex src_idx); 6832190SN/A 6841684SN/A /** Returns if a source register is ready. */ 6851464SN/A bool isReadySrcRegIdx(int idx) const 6861464SN/A { 6871464SN/A return this->_readySrcRegIdx[idx]; 6881464SN/A } 6891464SN/A 6901684SN/A /** Sets this instruction as completed. */ 6912731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6921464SN/A 6932292SN/A /** Returns whether or not this instruction is completed. */ 6942731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6951464SN/A 6962731Sktlim@umich.edu /** Marks the result as ready. */ 6972731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6982308SN/A 6992731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 7002731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 7012308SN/A 7021060SN/A /** Sets this instruction as ready to issue. */ 7032731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 7041060SN/A 7051060SN/A /** Returns whether or not this instruction is ready to issue. */ 7062731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 7071060SN/A 7084032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 7094032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 7104032Sktlim@umich.edu 7111060SN/A /** Sets this instruction as issued from the IQ. */ 7122731Sktlim@umich.edu void setIssued() { status.set(Issued); } 7131060SN/A 7141060SN/A /** Returns whether or not this instruction has issued. */ 7152731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 7161060SN/A 7174032Sktlim@umich.edu /** Clears this instruction as being issued. */ 7184032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 7194032Sktlim@umich.edu 7201060SN/A /** Sets this instruction as executed. */ 7212731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 7221060SN/A 7231060SN/A /** Returns whether or not this instruction has executed. */ 7242731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 7251060SN/A 7261060SN/A /** Sets this instruction as ready to commit. */ 7272731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7281060SN/A 7291061SN/A /** Clears this instruction as being ready to commit. */ 7302731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 7311061SN/A 7321060SN/A /** Returns whether or not this instruction is ready to commit. */ 7332731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7342731Sktlim@umich.edu 7352731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7362731Sktlim@umich.edu 7372731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7381060SN/A 7392292SN/A /** Sets this instruction as committed. */ 7402731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7412292SN/A 7422292SN/A /** Returns whether or not this instruction is committed. */ 7432731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7442292SN/A 7451060SN/A /** Sets this instruction as squashed. */ 7462731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7471060SN/A 7481060SN/A /** Returns whether or not this instruction is squashed. */ 7492731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7501060SN/A 7512292SN/A //Instruction Queue Entry 7522292SN/A //----------------------- 7532292SN/A /** Sets this instruction as a entry the IQ. */ 7542731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7552292SN/A 7562292SN/A /** Sets this instruction as a entry the IQ. */ 7572731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7582731Sktlim@umich.edu 7592731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7602731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7612292SN/A 7621060SN/A /** Sets this instruction as squashed in the IQ. */ 7632731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7641060SN/A 7651060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7662731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7672292SN/A 7682292SN/A 7692292SN/A //Load / Store Queue Functions 7702292SN/A //----------------------- 7712292SN/A /** Sets this instruction as a entry the LSQ. */ 7722731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7732292SN/A 7742292SN/A /** Sets this instruction as a entry the LSQ. */ 7752731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7762731Sktlim@umich.edu 7772731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7782731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7792292SN/A 7802292SN/A /** Sets this instruction as squashed in the LSQ. */ 7812731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7822292SN/A 7832292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7842731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7852292SN/A 7862292SN/A 7872292SN/A //Reorder Buffer Functions 7882292SN/A //----------------------- 7892292SN/A /** Sets this instruction as a entry the ROB. */ 7902731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7912292SN/A 7922292SN/A /** Sets this instruction as a entry the ROB. */ 7932731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7942731Sktlim@umich.edu 7952731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7962731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7972292SN/A 7982292SN/A /** Sets this instruction as squashed in the ROB. */ 7992731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 8002292SN/A 8012292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 8022731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 8032292SN/A 8047720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 8057720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 8067720Sgblack@eecs.umich.edu 8077720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 8087720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 8097720Sgblack@eecs.umich.edu 8101060SN/A /** Read the PC of this instruction. */ 8117720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 8127720Sgblack@eecs.umich.edu 8137720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 8147720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 8151060SN/A 8164636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 8177720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 8184636Sgblack@eecs.umich.edu 8197597Sminkyu.jeong@arm.com bool readPredicate() 8207597Sminkyu.jeong@arm.com { 8219046SAli.Saidi@ARM.com return instFlags[Predicate]; 8227597Sminkyu.jeong@arm.com } 8237597Sminkyu.jeong@arm.com 8247597Sminkyu.jeong@arm.com void setPredicate(bool val) 8257597Sminkyu.jeong@arm.com { 8269046SAli.Saidi@ARM.com instFlags[Predicate] = val; 8277600Sminkyu.jeong@arm.com 8287600Sminkyu.jeong@arm.com if (traceData) { 8297600Sminkyu.jeong@arm.com traceData->setPredicate(val); 8307600Sminkyu.jeong@arm.com } 8317597Sminkyu.jeong@arm.com } 8327597Sminkyu.jeong@arm.com 8332702Sktlim@umich.edu /** Sets the ASID. */ 8342292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8352292SN/A 8362702Sktlim@umich.edu /** Sets the thread id. */ 8376221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8382292SN/A 8392731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8402702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8411060SN/A 8422731Sktlim@umich.edu /** Returns the thread context. */ 8432680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8441464SN/A 8451464SN/A public: 8461684SN/A /** Sets the effective address. */ 8479046SAli.Saidi@ARM.com void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 8481684SN/A 8491684SN/A /** Returns the effective address. */ 8501464SN/A const Addr &getEA() const { return instEffAddr; } 8511684SN/A 8521684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8539046SAli.Saidi@ARM.com bool doneEACalc() { return instFlags[EACalcDone]; } 8541684SN/A 8551684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8561464SN/A bool eaSrcsReady(); 8571681SN/A 8584032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8599046SAli.Saidi@ARM.com bool uncacheable() { return instFlags[IsUncacheable]; } 8604032Sktlim@umich.edu 8614032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8629046SAli.Saidi@ARM.com bool hasRequest() { return instFlags[ReqMade]; } 8632292SN/A 8642292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8652292SN/A ListIt &getInstListIt() { return instListIt; } 8662292SN/A 8672292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8682292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8693326Sktlim@umich.edu 8703326Sktlim@umich.edu public: 8713326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8723326Sktlim@umich.edu unsigned readStCondFailures() 8733326Sktlim@umich.edu { return thread->storeCondFailures; } 8743326Sktlim@umich.edu 8753326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8763326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8773326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8781060SN/A}; 8791060SN/A 8801060SN/Atemplate<class Impl> 8817520Sgblack@eecs.umich.eduFault 8828444Sgblack@eecs.umich.eduBaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 8838444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8841060SN/A{ 8859046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 8867944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8876974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8886974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8896974Stjones1@inf.ed.ac.uk 8909046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 8917944SGiacomo.Gabrielli@arm.com req = savedReq; 8927944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8937944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8947944SGiacomo.Gabrielli@arm.com } else { 8958832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 8967944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8974032Sktlim@umich.edu 89810024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 89910024Sdam.sunwoo@arm.com 9007944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9017944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9027944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9037944SGiacomo.Gabrielli@arm.com } 9047944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 9051060SN/A } 9061060SN/A 9079046SAli.Saidi@ARM.com if (translationCompleted()) { 9087944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 9097944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 9108199SAli.Saidi@ARM.com effSize = size; 9119046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9128887Sgeoffrey.blake@arm.com 9138887Sgeoffrey.blake@arm.com if (cpu->checker) { 9148887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9158887Sgeoffrey.blake@arm.com delete reqToVerify; 9168887Sgeoffrey.blake@arm.com } 9178887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9188733Sgeoffrey.blake@arm.com } 9197944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 9207944SGiacomo.Gabrielli@arm.com } else { 9217944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 9227944SGiacomo.Gabrielli@arm.com // instruction as executed. 9237944SGiacomo.Gabrielli@arm.com this->setExecuted(); 9247944SGiacomo.Gabrielli@arm.com } 9257944SGiacomo.Gabrielli@arm.com 9267944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 9277944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 9287944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 9297944SGiacomo.Gabrielli@arm.com if (data) 9307944SGiacomo.Gabrielli@arm.com bzero(data, size); 9317944SGiacomo.Gabrielli@arm.com } 9327577SAli.Saidi@ARM.com } 9337577SAli.Saidi@ARM.com 9341060SN/A if (traceData) { 9351060SN/A traceData->setAddr(addr); 9361060SN/A } 9371060SN/A 9381060SN/A return fault; 9391060SN/A} 9401060SN/A 9411060SN/Atemplate<class Impl> 9427520Sgblack@eecs.umich.eduFault 9438444Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 9448444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9451060SN/A{ 9461060SN/A if (traceData) { 9471060SN/A traceData->setAddr(addr); 9481060SN/A } 9491060SN/A 9509046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 9517944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9526974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9536974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9546974Stjones1@inf.ed.ac.uk 9559046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 9567944SGiacomo.Gabrielli@arm.com req = savedReq; 9577944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9587944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9597944SGiacomo.Gabrielli@arm.com } else { 9608832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 9617944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9627944SGiacomo.Gabrielli@arm.com 96310024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 96410024Sdam.sunwoo@arm.com 9657944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9667944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9677944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9687944SGiacomo.Gabrielli@arm.com } 9697944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9706974Stjones1@inf.ed.ac.uk } 9714032Sktlim@umich.edu 9729046SAli.Saidi@ARM.com if (fault == NoFault && translationCompleted()) { 9732678Sktlim@umich.edu effAddr = req->getVaddr(); 9748199SAli.Saidi@ARM.com effSize = size; 9759046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9768887Sgeoffrey.blake@arm.com 9778887Sgeoffrey.blake@arm.com if (cpu->checker) { 9788887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9798887Sgeoffrey.blake@arm.com delete reqToVerify; 9808887Sgeoffrey.blake@arm.com } 9818887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9828733Sgeoffrey.blake@arm.com } 9836975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9841060SN/A } 9851060SN/A 9861060SN/A return fault; 9871060SN/A} 9881060SN/A 9896973Stjones1@inf.ed.ac.uktemplate<class Impl> 9906973Stjones1@inf.ed.ac.ukinline void 9916974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9926974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9936974Stjones1@inf.ed.ac.uk{ 9946974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9959814Sandreas.hansson@arm.com unsigned block_size = cpu->cacheLineSize(); 9966974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9976974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9986974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9996974Stjones1@inf.ed.ac.uk 10006974Stjones1@inf.ed.ac.uk // Spans two blocks. 10016974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 10026974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 10036974Stjones1@inf.ed.ac.uk } 10046974Stjones1@inf.ed.ac.uk} 10056974Stjones1@inf.ed.ac.uk 10066974Stjones1@inf.ed.ac.uktemplate<class Impl> 10076974Stjones1@inf.ed.ac.ukinline void 10086974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 10096974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 10106973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 10116973Stjones1@inf.ed.ac.uk{ 10129046SAli.Saidi@ARM.com translationStarted(true); 10137944SGiacomo.Gabrielli@arm.com 10146974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10156974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10166974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10176974Stjones1@inf.ed.ac.uk 10186974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10198486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 10208486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 10219932SAli.Saidi@ARM.com 10226974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10239932SAli.Saidi@ARM.com 10249046SAli.Saidi@ARM.com if (!translationCompleted()) { 10259932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10269932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10279932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10289932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10299932SAli.Saidi@ARM.com fault = NoFault; 10309932SAli.Saidi@ARM.com 10317944SGiacomo.Gabrielli@arm.com // Save memory requests. 10327944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10337944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10347944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10357944SGiacomo.Gabrielli@arm.com } 10366974Stjones1@inf.ed.ac.uk } else { 10376974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10386974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10396974Stjones1@inf.ed.ac.uk 10406974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10418486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 10428486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 10438486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 10448486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 10456974Stjones1@inf.ed.ac.uk 10466974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10476974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10489932SAli.Saidi@ARM.com 10499046SAli.Saidi@ARM.com if (!translationCompleted()) { 10509932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10519932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10529932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10539932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10549932SAli.Saidi@ARM.com fault = NoFault; 10559932SAli.Saidi@ARM.com 10567944SGiacomo.Gabrielli@arm.com // Save memory requests. 10577944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10587944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10597944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10607944SGiacomo.Gabrielli@arm.com } 10616974Stjones1@inf.ed.ac.uk } 10626973Stjones1@inf.ed.ac.uk} 10636973Stjones1@inf.ed.ac.uk 10646973Stjones1@inf.ed.ac.uktemplate<class Impl> 10656973Stjones1@inf.ed.ac.ukinline void 10666973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10676973Stjones1@inf.ed.ac.uk{ 10686973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10696973Stjones1@inf.ed.ac.uk 10709046SAli.Saidi@ARM.com instFlags[IsUncacheable] = state->isUncacheable(); 10716973Stjones1@inf.ed.ac.uk 10726973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10736973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10746973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10756973Stjones1@inf.ed.ac.uk 10766973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10776973Stjones1@inf.ed.ac.uk assert(state->res); 10786973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10796973Stjones1@inf.ed.ac.uk } 10806973Stjones1@inf.ed.ac.uk 10816973Stjones1@inf.ed.ac.uk } else { 10826973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10836973Stjones1@inf.ed.ac.uk } 10846973Stjones1@inf.ed.ac.uk delete state; 10857944SGiacomo.Gabrielli@arm.com 10869046SAli.Saidi@ARM.com translationCompleted(true); 10876973Stjones1@inf.ed.ac.uk} 10886973Stjones1@inf.ed.ac.uk 10891464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1090