base.hh revision 8779:2a590c51adb1
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * Copyright (c) 2011 Regents of the University of California 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 * Nathan Binkert 31 * Rick Strong 32 */ 33 34#ifndef __CPU_BASE_HH__ 35#define __CPU_BASE_HH__ 36 37#include <vector> 38 39#include "arch/interrupts.hh" 40#include "arch/isa_traits.hh" 41#include "arch/microcode_rom.hh" 42#include "base/statistics.hh" 43#include "config/full_system.hh" 44#include "config/the_isa.hh" 45#include "mem/mem_object.hh" 46#include "sim/eventq.hh" 47#include "sim/full_system.hh" 48#include "sim/insttracer.hh" 49 50class BaseCPUParams; 51class BranchPred; 52class CheckerCPU; 53class ThreadContext; 54class System; 55class Port; 56 57namespace TheISA 58{ 59 class Predecoder; 60} 61 62class CPUProgressEvent : public Event 63{ 64 protected: 65 Tick _interval; 66 Counter lastNumInst; 67 BaseCPU *cpu; 68 bool _repeatEvent; 69 70 public: 71 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 72 73 void process(); 74 75 void interval(Tick ival) { _interval = ival; } 76 Tick interval() { return _interval; } 77 78 void repeatEvent(bool repeat) { _repeatEvent = repeat; } 79 80 virtual const char *description() const; 81}; 82 83class BaseCPU : public MemObject 84{ 85 protected: 86 // CPU's clock period in terms of the number of ticks of curTime. 87 Tick clock; 88 // @todo remove me after debugging with legion done 89 Tick instCnt; 90 // every cpu has an id, put it in the base cpu 91 // Set at initialization, only time a cpuId might change is during a 92 // takeover (which should be done from within the BaseCPU anyway, 93 // therefore no setCpuId() method is provided 94 int _cpuId; 95 96 public: 97 /** Reads this CPU's ID. */ 98 int cpuId() { return _cpuId; } 99 100// Tick currentTick; 101 inline Tick frequency() const { return SimClock::Frequency / clock; } 102 inline Tick ticks(int numCycles) const { return clock * numCycles; } 103 inline Tick curCycle() const { return curTick() / clock; } 104 inline Tick tickToCycles(Tick val) const { return val / clock; } 105 inline void workItemBegin() { numWorkItemsStarted++; } 106 inline void workItemEnd() { numWorkItemsCompleted++; } 107 // @todo remove me after debugging with legion done 108 Tick instCount() { return instCnt; } 109 110 /** The next cycle the CPU should be scheduled, given a cache 111 * access or quiesce event returning on this cycle. This function 112 * may return curTick() if the CPU should run on the current cycle. 113 */ 114 Tick nextCycle(); 115 116 /** The next cycle the CPU should be scheduled, given a cache 117 * access or quiesce event returning on the given Tick. This 118 * function may return curTick() if the CPU should run on the 119 * current cycle. 120 * @param begin_tick The tick that the event is completing on. 121 */ 122 Tick nextCycle(Tick begin_tick); 123 124 TheISA::MicrocodeRom microcodeRom; 125 126 protected: 127 TheISA::Interrupts *interrupts; 128 129 public: 130 TheISA::Interrupts * 131 getInterruptController() 132 { 133 return interrupts; 134 } 135 136 virtual void wakeup() = 0; 137 138 void 139 postInterrupt(int int_num, int index) 140 { 141 interrupts->post(int_num, index); 142 if (FullSystem) 143 wakeup(); 144 } 145 146 void 147 clearInterrupt(int int_num, int index) 148 { 149 interrupts->clear(int_num, index); 150 } 151 152 void 153 clearInterrupts() 154 { 155 interrupts->clearAll(); 156 } 157 158 bool 159 checkInterrupts(ThreadContext *tc) const 160 { 161 return interrupts->checkInterrupts(tc); 162 } 163 164 class ProfileEvent : public Event 165 { 166 private: 167 BaseCPU *cpu; 168 Tick interval; 169 170 public: 171 ProfileEvent(BaseCPU *cpu, Tick interval); 172 void process(); 173 }; 174 ProfileEvent *profileEvent; 175 176 protected: 177 std::vector<ThreadContext *> threadContexts; 178 std::vector<TheISA::Predecoder *> predecoders; 179 180 Trace::InstTracer * tracer; 181 182 public: 183 184 // Mask to align PCs to MachInst sized boundaries 185 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 186 187 /// Provide access to the tracer pointer 188 Trace::InstTracer * getTracer() { return tracer; } 189 190 /// Notify the CPU that the indicated context is now active. The 191 /// delay parameter indicates the number of ticks to wait before 192 /// executing (typically 0 or 1). 193 virtual void activateContext(int thread_num, int delay) {} 194 195 /// Notify the CPU that the indicated context is now suspended. 196 virtual void suspendContext(int thread_num) {} 197 198 /// Notify the CPU that the indicated context is now deallocated. 199 virtual void deallocateContext(int thread_num) {} 200 201 /// Notify the CPU that the indicated context is now halted. 202 virtual void haltContext(int thread_num) {} 203 204 /// Given a Thread Context pointer return the thread num 205 int findContext(ThreadContext *tc); 206 207 /// Given a thread num get tho thread context for it 208 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 209 210 public: 211 typedef BaseCPUParams Params; 212 const Params *params() const 213 { return reinterpret_cast<const Params *>(_params); } 214 BaseCPU(Params *params); 215 virtual ~BaseCPU(); 216 217 virtual void init(); 218 virtual void startup(); 219 virtual void regStats(); 220 221 virtual void activateWhenReady(ThreadID tid) {}; 222 223 void registerThreadContexts(); 224 225 /// Prepare for another CPU to take over execution. When it is 226 /// is ready (drained pipe) it signals the sampler. 227 virtual void switchOut(); 228 229 /// Take over execution from the given CPU. Used for warm-up and 230 /// sampling. 231 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 232 233 /** 234 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 235 * This is a constant for the duration of the simulation. 236 */ 237 ThreadID numThreads; 238 239 /** 240 * Vector of per-thread instruction-based event queues. Used for 241 * scheduling events based on number of instructions committed by 242 * a particular thread. 243 */ 244 EventQueue **comInstEventQueue; 245 246 /** 247 * Vector of per-thread load-based event queues. Used for 248 * scheduling events based on number of loads committed by 249 *a particular thread. 250 */ 251 EventQueue **comLoadEventQueue; 252 253 System *system; 254 255 Tick phase; 256 257 /** 258 * Serialize this object to the given output stream. 259 * @param os The stream to serialize to. 260 */ 261 virtual void serialize(std::ostream &os); 262 263 /** 264 * Reconstruct the state of this object from a checkpoint. 265 * @param cp The checkpoint use. 266 * @param section The section name of this object 267 */ 268 virtual void unserialize(Checkpoint *cp, const std::string §ion); 269 270 /** 271 * Return pointer to CPU's branch predictor (NULL if none). 272 * @return Branch predictor pointer. 273 */ 274 virtual BranchPred *getBranchPred() { return NULL; }; 275 276 virtual Counter totalInstructions() const = 0; 277 278 // Function tracing 279 private: 280 bool functionTracingEnabled; 281 std::ostream *functionTraceStream; 282 Addr currentFunctionStart; 283 Addr currentFunctionEnd; 284 Tick functionEntryTick; 285 void enableFunctionTrace(); 286 void traceFunctionsInternal(Addr pc); 287 288 protected: 289 void traceFunctions(Addr pc) 290 { 291 if (functionTracingEnabled) 292 traceFunctionsInternal(pc); 293 } 294 295 private: 296 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 297 298 public: 299 static int numSimulatedCPUs() { return cpuList.size(); } 300 static Counter numSimulatedInstructions() 301 { 302 Counter total = 0; 303 304 int size = cpuList.size(); 305 for (int i = 0; i < size; ++i) 306 total += cpuList[i]->totalInstructions(); 307 308 return total; 309 } 310 311 public: 312 // Number of CPU cycles simulated 313 Stats::Scalar numCycles; 314 Stats::Scalar numWorkItemsStarted; 315 Stats::Scalar numWorkItemsCompleted; 316}; 317 318#endif // __CPU_BASE_HH__ 319