base.hh revision 8181:f789b9aac5f4
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 37100Sgblack@eecs.umich.edu * Copyright (c) 2011 Regents of the University of California 47100Sgblack@eecs.umich.edu * All rights reserved. 57100Sgblack@eecs.umich.edu * 67100Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 77100Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 87100Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 97100Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 107100Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 117100Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 127100Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 137100Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 147100Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu * this software without specific prior written permission. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * Authors: Steve Reinhardt 306019Shines@cs.fsu.edu * Nathan Binkert 316019Shines@cs.fsu.edu * Rick Strong 326019Shines@cs.fsu.edu */ 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.edu#ifndef __CPU_BASE_HH__ 356019Shines@cs.fsu.edu#define __CPU_BASE_HH__ 366019Shines@cs.fsu.edu 376019Shines@cs.fsu.edu#include <vector> 386019Shines@cs.fsu.edu 396019Shines@cs.fsu.edu#include "arch/isa_traits.hh" 406019Shines@cs.fsu.edu#include "arch/microcode_rom.hh" 416019Shines@cs.fsu.edu#include "base/statistics.hh" 426757SAli.Saidi@ARM.com#include "config/full_system.hh" 436019Shines@cs.fsu.edu#include "config/the_isa.hh" 446019Shines@cs.fsu.edu#include "sim/eventq.hh" 456019Shines@cs.fsu.edu#include "sim/insttracer.hh" 466019Shines@cs.fsu.edu#include "mem/mem_object.hh" 476019Shines@cs.fsu.edu 486019Shines@cs.fsu.edu#if FULL_SYSTEM 496019Shines@cs.fsu.edu#include "arch/interrupts.hh" 509022Sgblack@eecs.umich.edu#endif 516019Shines@cs.fsu.edu 527170Sgblack@eecs.umich.educlass BaseCPUParams; 536253Sgblack@eecs.umich.educlass BranchPred; 547202Sgblack@eecs.umich.educlass CheckerCPU; 556253Sgblack@eecs.umich.educlass ThreadContext; 566253Sgblack@eecs.umich.educlass System; 577396Sgblack@eecs.umich.educlass Port; 588745Sgblack@eecs.umich.edu 597405SAli.Saidi@ARM.comnamespace TheISA 608782Sgblack@eecs.umich.edu{ 618782Sgblack@eecs.umich.edu class Predecoder; 628782Sgblack@eecs.umich.edu} 637259Sgblack@eecs.umich.edu 648757Sgblack@eecs.umich.educlass CPUProgressEvent : public Event 658782Sgblack@eecs.umich.edu{ 668757Sgblack@eecs.umich.edu protected: 678777Sgblack@eecs.umich.edu Tick _interval; 688782Sgblack@eecs.umich.edu Counter lastNumInst; 698756Sgblack@eecs.umich.edu BaseCPU *cpu; 706019Shines@cs.fsu.edu bool _repeatEvent; 716757SAli.Saidi@ARM.com 728757Sgblack@eecs.umich.edu public: 736019Shines@cs.fsu.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 748745Sgblack@eecs.umich.edu 756397Sgblack@eecs.umich.edu void process(); 768782Sgblack@eecs.umich.edu 776019Shines@cs.fsu.edu void interval(Tick ival) { _interval = ival; } 786397Sgblack@eecs.umich.edu Tick interval() { return _interval; } 798335Snate@binkert.org 809023Sgblack@eecs.umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 819023Sgblack@eecs.umich.edu 828335Snate@binkert.org virtual const char *description() const; 836019Shines@cs.fsu.edu}; 846019Shines@cs.fsu.edu 856019Shines@cs.fsu.educlass BaseCPU : public MemObject 866019Shines@cs.fsu.edu{ 876019Shines@cs.fsu.edu protected: 886019Shines@cs.fsu.edu // CPU's clock period in terms of the number of ticks of curTime. 896019Shines@cs.fsu.edu Tick clock; 906019Shines@cs.fsu.edu // @todo remove me after debugging with legion done 91 Tick instCnt; 92 // every cpu has an id, put it in the base cpu 93 // Set at initialization, only time a cpuId might change is during a 94 // takeover (which should be done from within the BaseCPU anyway, 95 // therefore no setCpuId() method is provided 96 int _cpuId; 97 98 public: 99 /** Reads this CPU's ID. */ 100 int cpuId() { return _cpuId; } 101 102// Tick currentTick; 103 inline Tick frequency() const { return SimClock::Frequency / clock; } 104 inline Tick ticks(int numCycles) const { return clock * numCycles; } 105 inline Tick curCycle() const { return curTick() / clock; } 106 inline Tick tickToCycles(Tick val) const { return val / clock; } 107 inline void workItemBegin() { numWorkItemsStarted++; } 108 inline void workItemEnd() { numWorkItemsCompleted++; } 109 // @todo remove me after debugging with legion done 110 Tick instCount() { return instCnt; } 111 112 /** The next cycle the CPU should be scheduled, given a cache 113 * access or quiesce event returning on this cycle. This function 114 * may return curTick() if the CPU should run on the current cycle. 115 */ 116 Tick nextCycle(); 117 118 /** The next cycle the CPU should be scheduled, given a cache 119 * access or quiesce event returning on the given Tick. This 120 * function may return curTick() if the CPU should run on the 121 * current cycle. 122 * @param begin_tick The tick that the event is completing on. 123 */ 124 Tick nextCycle(Tick begin_tick); 125 126 TheISA::MicrocodeRom microcodeRom; 127 128#if FULL_SYSTEM 129 protected: 130 TheISA::Interrupts *interrupts; 131 132 public: 133 TheISA::Interrupts * 134 getInterruptController() 135 { 136 return interrupts; 137 } 138 139 virtual void wakeup() = 0; 140 141 void 142 postInterrupt(int int_num, int index) 143 { 144 interrupts->post(int_num, index); 145 wakeup(); 146 } 147 148 void 149 clearInterrupt(int int_num, int index) 150 { 151 interrupts->clear(int_num, index); 152 } 153 154 void 155 clearInterrupts() 156 { 157 interrupts->clearAll(); 158 } 159 160 bool 161 checkInterrupts(ThreadContext *tc) const 162 { 163 return interrupts->checkInterrupts(tc); 164 } 165 166 class ProfileEvent : public Event 167 { 168 private: 169 BaseCPU *cpu; 170 Tick interval; 171 172 public: 173 ProfileEvent(BaseCPU *cpu, Tick interval); 174 void process(); 175 }; 176 ProfileEvent *profileEvent; 177#endif 178 179 protected: 180 std::vector<ThreadContext *> threadContexts; 181 std::vector<TheISA::Predecoder *> predecoders; 182 183 Trace::InstTracer * tracer; 184 185 public: 186 187 // Mask to align PCs to MachInst sized boundaries 188 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 189 190 /// Provide access to the tracer pointer 191 Trace::InstTracer * getTracer() { return tracer; } 192 193 /// Notify the CPU that the indicated context is now active. The 194 /// delay parameter indicates the number of ticks to wait before 195 /// executing (typically 0 or 1). 196 virtual void activateContext(int thread_num, int delay) {} 197 198 /// Notify the CPU that the indicated context is now suspended. 199 virtual void suspendContext(int thread_num) {} 200 201 /// Notify the CPU that the indicated context is now deallocated. 202 virtual void deallocateContext(int thread_num) {} 203 204 /// Notify the CPU that the indicated context is now halted. 205 virtual void haltContext(int thread_num) {} 206 207 /// Given a Thread Context pointer return the thread num 208 int findContext(ThreadContext *tc); 209 210 /// Given a thread num get tho thread context for it 211 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 212 213 public: 214 typedef BaseCPUParams Params; 215 const Params *params() const 216 { return reinterpret_cast<const Params *>(_params); } 217 BaseCPU(Params *params); 218 virtual ~BaseCPU(); 219 220 virtual void init(); 221 virtual void startup(); 222 virtual void regStats(); 223 224 virtual void activateWhenReady(ThreadID tid) {}; 225 226 void registerThreadContexts(); 227 228 /// Prepare for another CPU to take over execution. When it is 229 /// is ready (drained pipe) it signals the sampler. 230 virtual void switchOut(); 231 232 /// Take over execution from the given CPU. Used for warm-up and 233 /// sampling. 234 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 235 236 /** 237 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 238 * This is a constant for the duration of the simulation. 239 */ 240 ThreadID numThreads; 241 242 /** 243 * Vector of per-thread instruction-based event queues. Used for 244 * scheduling events based on number of instructions committed by 245 * a particular thread. 246 */ 247 EventQueue **comInstEventQueue; 248 249 /** 250 * Vector of per-thread load-based event queues. Used for 251 * scheduling events based on number of loads committed by 252 *a particular thread. 253 */ 254 EventQueue **comLoadEventQueue; 255 256 System *system; 257 258 Tick phase; 259 260#if FULL_SYSTEM 261 /** 262 * Serialize this object to the given output stream. 263 * @param os The stream to serialize to. 264 */ 265 virtual void serialize(std::ostream &os); 266 267 /** 268 * Reconstruct the state of this object from a checkpoint. 269 * @param cp The checkpoint use. 270 * @param section The section name of this object 271 */ 272 virtual void unserialize(Checkpoint *cp, const std::string §ion); 273 274#endif 275 276 /** 277 * Return pointer to CPU's branch predictor (NULL if none). 278 * @return Branch predictor pointer. 279 */ 280 virtual BranchPred *getBranchPred() { return NULL; }; 281 282 virtual Counter totalInstructions() const = 0; 283 284 // Function tracing 285 private: 286 bool functionTracingEnabled; 287 std::ostream *functionTraceStream; 288 Addr currentFunctionStart; 289 Addr currentFunctionEnd; 290 Tick functionEntryTick; 291 void enableFunctionTrace(); 292 void traceFunctionsInternal(Addr pc); 293 294 protected: 295 void traceFunctions(Addr pc) 296 { 297 if (functionTracingEnabled) 298 traceFunctionsInternal(pc); 299 } 300 301 private: 302 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 303 304 public: 305 static int numSimulatedCPUs() { return cpuList.size(); } 306 static Counter numSimulatedInstructions() 307 { 308 Counter total = 0; 309 310 int size = cpuList.size(); 311 for (int i = 0; i < size; ++i) 312 total += cpuList[i]->totalInstructions(); 313 314 return total; 315 } 316 317 public: 318 // Number of CPU cycles simulated 319 Stats::Scalar numCycles; 320 Stats::Scalar numWorkItemsStarted; 321 Stats::Scalar numWorkItemsCompleted; 322}; 323 324#endif // __CPU_BASE_HH__ 325