base.hh revision 5715:e8c1d4e669a7
15703SN/A/* 25703SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 35703SN/A * All rights reserved. 49988Snilay@cs.wisc.edu * 58825Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 69988Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 77935SN/A * met: redistributions of source code must retain the above copyright 87935SN/A * notice, this list of conditions and the following disclaimer; 97935SN/A * redistributions in binary form must reproduce the above copyright 105703SN/A * notice, this list of conditions and the following disclaimer in the 115703SN/A * documentation and/or other materials provided with the distribution; 125703SN/A * neither the name of the copyright holders nor the names of its 1310315Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 145703SN/A * this software without specific prior written permission. 155703SN/A * 169885Sstever@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179885Sstever@gmail.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810900Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199988Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205703SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110900Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210315Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237670SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410242Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255703SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269449SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278464SN/A * 2810798Ssteve.reinhardt@amd.com * Authors: Steve Reinhardt 298721SN/A * Nathan Binkert 3010900Snilay@cs.wisc.edu */ 3110900Snilay@cs.wisc.edu 325703SN/A#ifndef __CPU_BASE_HH__ 335703SN/A#define __CPU_BASE_HH__ 345703SN/A 357935SN/A#include <vector> 367935SN/A 377935SN/A#include "arch/isa_traits.hh" 387935SN/A#include "arch/microcode_rom.hh" 397935SN/A#include "base/statistics.hh" 407935SN/A#include "config/full_system.hh" 417935SN/A#include "sim/eventq.hh" 428983Snate@binkert.org#include "sim/insttracer.hh" 435703SN/A#include "mem/mem_object.hh" 445703SN/A 455703SN/A#if FULL_SYSTEM 469885Sstever@gmail.com#include "arch/interrupts.hh" 475703SN/A#endif 489988Snilay@cs.wisc.edu 498721SN/Aclass BaseCPUParams; 508721SN/Aclass BranchPred; 518721SN/Aclass CheckerCPU; 528983Snate@binkert.orgclass ThreadContext; 538983Snate@binkert.orgclass System; 545703SN/Aclass Port; 559885Sstever@gmail.com 569885Sstever@gmail.comnamespace TheISA 579885Sstever@gmail.com{ 5810315Snilay@cs.wisc.edu class Predecoder; 599988Snilay@cs.wisc.edu} 6010315Snilay@cs.wisc.edu 619885Sstever@gmail.comclass CPUProgressEvent : public Event 629885Sstever@gmail.com{ 635703SN/A protected: 645703SN/A Tick interval; 659481Snilay@cs.wisc.edu Counter lastNumInst; 665703SN/A BaseCPU *cpu; 675703SN/A 688241SN/A public: 698241SN/A CPUProgressEvent(BaseCPU *_cpu, Tick ival); 705703SN/A 715703SN/A void process(); 725703SN/A 735703SN/A virtual const char *description() const; 749481Snilay@cs.wisc.edu}; 755703SN/A 765876SN/Aclass BaseCPU : public MemObject 779885Sstever@gmail.com{ 785703SN/A protected: 795703SN/A // CPU's clock period in terms of the number of ticks of curTime. 805703SN/A Tick clock; 815703SN/A // @todo remove me after debugging with legion done 825703SN/A Tick instCnt; 835703SN/A // every cpu has an id, put it in the base cpu 845703SN/A // Set at initialization, only time a cpuId might change is during a 855703SN/A // takeover (which should be done from within the BaseCPU anyway, 865703SN/A // therefore no setCpuId() method is provided 875703SN/A int _cpuId; 885703SN/A 895703SN/A public: 905703SN/A /** Reads this CPU's ID. */ 915703SN/A int cpuId() { return _cpuId; } 929988Snilay@cs.wisc.edu 939988Snilay@cs.wisc.edu// Tick currentTick; 9410451Snilay@cs.wisc.edu inline Tick frequency() const { return Clock::Frequency / clock; } 955703SN/A inline Tick ticks(int numCycles) const { return clock * numCycles; } 965703SN/A inline Tick curCycle() const { return curTick / clock; } 975703SN/A inline Tick tickToCycles(Tick val) const { return val / clock; } 985703SN/A // @todo remove me after debugging with legion done 995703SN/A Tick instCount() { return instCnt; } 1005703SN/A 1015703SN/A /** The next cycle the CPU should be scheduled, given a cache 1025703SN/A * access or quiesce event returning on this cycle. This function 1035703SN/A * may return curTick if the CPU should run on the current cycle. 1045703SN/A */ 1055703SN/A Tick nextCycle(); 1065703SN/A 1079348SAli.Saidi@ARM.com /** The next cycle the CPU should be scheduled, given a cache 1085703SN/A * access or quiesce event returning on the given Tick. This 1095703SN/A * function may return curTick if the CPU should run on the 1105703SN/A * current cycle. 1115703SN/A * @param begin_tick The tick that the event is completing on. 1125703SN/A */ 1135703SN/A Tick nextCycle(Tick begin_tick); 1145703SN/A 1158825Snilay@cs.wisc.edu TheISA::MicrocodeRom microcodeRom; 1165703SN/A 1179924Ssteve.reinhardt@amd.com#if FULL_SYSTEM 1185703SN/A protected: 1195703SN/A TheISA::Interrupts *interrupts; 1205703SN/A 1215703SN/A public: 1225703SN/A TheISA::Interrupts * 1235703SN/A getInterruptController() 1245703SN/A { 1255703SN/A return interrupts; 1265703SN/A } 1275703SN/A 1285703SN/A virtual void postInterrupt(int int_num, int index); 1295703SN/A virtual void clearInterrupt(int int_num, int index); 1309661SAli.Saidi@ARM.com virtual void clearInterrupts(); 1315703SN/A 1325703SN/A bool 1335703SN/A checkInterrupts(ThreadContext *tc) const 1345703SN/A { 1355703SN/A return interrupts->checkInterrupts(tc); 1365703SN/A } 1375703SN/A 1385703SN/A class ProfileEvent : public Event 1395703SN/A { 14010242Ssteve.reinhardt@amd.com private: 1415703SN/A BaseCPU *cpu; 1428521SN/A Tick interval; 1439449SAli.Saidi@ARM.com 1445703SN/A public: 1455703SN/A ProfileEvent(BaseCPU *cpu, Tick interval); 1465703SN/A void process(); 1475703SN/A }; 1488825Snilay@cs.wisc.edu ProfileEvent *profileEvent; 1495703SN/A#endif 1505703SN/A 1515703SN/A protected: 1529481Snilay@cs.wisc.edu std::vector<ThreadContext *> threadContexts; 15310798Ssteve.reinhardt@amd.com std::vector<TheISA::Predecoder *> predecoders; 1549481Snilay@cs.wisc.edu 1559481Snilay@cs.wisc.edu Trace::InstTracer * tracer; 1569481Snilay@cs.wisc.edu 1579481Snilay@cs.wisc.edu public: 1589481Snilay@cs.wisc.edu 1599988Snilay@cs.wisc.edu /// Provide access to the tracer pointer 1609481Snilay@cs.wisc.edu Trace::InstTracer * getTracer() { return tracer; } 1619481Snilay@cs.wisc.edu 1629481Snilay@cs.wisc.edu /// Notify the CPU that the indicated context is now active. The 1639481Snilay@cs.wisc.edu /// delay parameter indicates the number of ticks to wait before 1649481Snilay@cs.wisc.edu /// executing (typically 0 or 1). 1659481Snilay@cs.wisc.edu virtual void activateContext(int thread_num, int delay) {} 1669481Snilay@cs.wisc.edu 1679481Snilay@cs.wisc.edu /// Notify the CPU that the indicated context is now suspended. 1685703SN/A virtual void suspendContext(int thread_num) {} 16911103Snilay@cs.wisc.edu 1709885Sstever@gmail.com /// Notify the CPU that the indicated context is now deallocated. 1718983Snate@binkert.org virtual void deallocateContext(int thread_num) {} 1725703SN/A 1739885Sstever@gmail.com /// Notify the CPU that the indicated context is now halted. 17410798Ssteve.reinhardt@amd.com virtual void haltContext(int thread_num) {} 1759988Snilay@cs.wisc.edu 1766123SN/A /// Given a Thread Context pointer return the thread num 1779348SAli.Saidi@ARM.com int findContext(ThreadContext *tc); 17810900Snilay@cs.wisc.edu 1795703SN/A /// Given a thread num get tho thread context for it 1805703SN/A ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1815876SN/A 1828835SAli.Saidi@ARM.com public: 1839348SAli.Saidi@ARM.com typedef BaseCPUParams Params; 18410036SAli.Saidi@ARM.com const Params *params() const 1855703SN/A { return reinterpret_cast<const Params *>(_params); } 1868835SAli.Saidi@ARM.com BaseCPU(Params *params); 1879885Sstever@gmail.com virtual ~BaseCPU(); 1885703SN/A 1895703SN/A virtual void init(); 1905703SN/A virtual void startup(); 1919348SAli.Saidi@ARM.com virtual void regStats(); 1925703SN/A 1939885Sstever@gmail.com virtual void activateWhenReady(int tid) {}; 1949885Sstever@gmail.com 1959885Sstever@gmail.com void registerThreadContexts(); 1969885Sstever@gmail.com 1979885Sstever@gmail.com /// Prepare for another CPU to take over execution. When it is 1989988Snilay@cs.wisc.edu /// is ready (drained pipe) it signals the sampler. 1999885Sstever@gmail.com virtual void switchOut(); 20010036SAli.Saidi@ARM.com 2019885Sstever@gmail.com /// Take over execution from the given CPU. Used for warm-up and 2029885Sstever@gmail.com /// sampling. 2035703SN/A virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 2046024SN/A 2059988Snilay@cs.wisc.edu /** 2065703SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 2075703SN/A * This is a constant for the duration of the simulation. 2085703SN/A */ 2095703SN/A int number_of_threads; 2107761SN/A 2117761SN/A TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 2129988Snilay@cs.wisc.edu 2135703SN/A /** 2145703SN/A * Vector of per-thread instruction-based event queues. Used for 2155703SN/A * scheduling events based on number of instructions committed by 2165703SN/A * a particular thread. 2175703SN/A */ 2189988Snilay@cs.wisc.edu EventQueue **comInstEventQueue; 2195703SN/A 2205703SN/A /** 2215703SN/A * Vector of per-thread load-based event queues. Used for 2225703SN/A * scheduling events based on number of loads committed by 2239988Snilay@cs.wisc.edu *a particular thread. 2245703SN/A */ 2255703SN/A EventQueue **comLoadEventQueue; 22610900Snilay@cs.wisc.edu 2275703SN/A System *system; 2285703SN/A 2295703SN/A Tick phase; 2305703SN/A 2315703SN/A#if FULL_SYSTEM 2329988Snilay@cs.wisc.edu /** 2335703SN/A * Serialize this object to the given output stream. 2345703SN/A * @param os The stream to serialize to. 2355703SN/A */ 2365703SN/A virtual void serialize(std::ostream &os); 2379988Snilay@cs.wisc.edu 2385703SN/A /** 2395703SN/A * Reconstruct the state of this object from a checkpoint. 24010900Snilay@cs.wisc.edu * @param cp The checkpoint use. 2415703SN/A * @param section The section name of this object 2425703SN/A */ 2435703SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2449988Snilay@cs.wisc.edu 2455703SN/A#endif 2465703SN/A 24710900Snilay@cs.wisc.edu /** 2485703SN/A * Return pointer to CPU's branch predictor (NULL if none). 2495703SN/A * @return Branch predictor pointer. 2505703SN/A */ 2515703SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2525703SN/A 2539988Snilay@cs.wisc.edu virtual Counter totalInstructions() const { return 0; } 2545703SN/A 2555703SN/A // Function tracing 2565703SN/A private: 2575703SN/A bool functionTracingEnabled; 2589988Snilay@cs.wisc.edu std::ostream *functionTraceStream; 2595703SN/A Addr currentFunctionStart; 2605703SN/A Addr currentFunctionEnd; 26110900Snilay@cs.wisc.edu Tick functionEntryTick; 2625703SN/A void enableFunctionTrace(); 2635703SN/A void traceFunctionsInternal(Addr pc); 2645703SN/A 2659988Snilay@cs.wisc.edu protected: 2665703SN/A void traceFunctions(Addr pc) 2675703SN/A { 26810900Snilay@cs.wisc.edu if (functionTracingEnabled) 2695703SN/A traceFunctionsInternal(pc); 2705703SN/A } 2715703SN/A 2729988Snilay@cs.wisc.edu private: 2735703SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2745703SN/A 27510900Snilay@cs.wisc.edu public: 2765703SN/A static int numSimulatedCPUs() { return cpuList.size(); } 2775703SN/A static Counter numSimulatedInstructions() 2785703SN/A { 2795703SN/A Counter total = 0; 2805703SN/A 2819988Snilay@cs.wisc.edu int size = cpuList.size(); 2825703SN/A for (int i = 0; i < size; ++i) 2835703SN/A total += cpuList[i]->totalInstructions(); 2845703SN/A 2855703SN/A return total; 2869988Snilay@cs.wisc.edu } 2875703SN/A 2885703SN/A public: 28910900Snilay@cs.wisc.edu // Number of CPU cycles simulated 2905703SN/A Stats::Scalar<> numCycles; 2915703SN/A}; 2925703SN/A 2939988Snilay@cs.wisc.edu#endif // __CPU_BASE_HH__ 2945703SN/A