base.hh revision 5252:c2804af3a7f4
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "base/statistics.hh" 39#include "config/full_system.hh" 40#include "sim/eventq.hh" 41#include "sim/insttracer.hh" 42#include "mem/mem_object.hh" 43 44#if FULL_SYSTEM 45#include "arch/interrupts.hh" 46#endif 47 48class BranchPred; 49class CheckerCPU; 50class ThreadContext; 51class System; 52class Port; 53 54namespace TheISA 55{ 56 class Predecoder; 57} 58 59class CPUProgressEvent : public Event 60{ 61 protected: 62 Tick interval; 63 Counter lastNumInst; 64 BaseCPU *cpu; 65 66 public: 67 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 68 69 void process(); 70 71 virtual const char *description(); 72}; 73 74class BaseCPU : public MemObject 75{ 76 protected: 77 // CPU's clock period in terms of the number of ticks of curTime. 78 Tick clock; 79 // @todo remove me after debugging with legion done 80 Tick instCnt; 81 82 public: 83// Tick currentTick; 84 inline Tick frequency() const { return Clock::Frequency / clock; } 85 inline Tick ticks(int numCycles) const { return clock * numCycles; } 86 inline Tick curCycle() const { return curTick / clock; } 87 inline Tick tickToCycles(Tick val) const { return val / clock; } 88 // @todo remove me after debugging with legion done 89 Tick instCount() { return instCnt; } 90 91 /** The next cycle the CPU should be scheduled, given a cache 92 * access or quiesce event returning on this cycle. This function 93 * may return curTick if the CPU should run on the current cycle. 94 */ 95 Tick nextCycle(); 96 97 /** The next cycle the CPU should be scheduled, given a cache 98 * access or quiesce event returning on the given Tick. This 99 * function may return curTick if the CPU should run on the 100 * current cycle. 101 * @param begin_tick The tick that the event is completing on. 102 */ 103 Tick nextCycle(Tick begin_tick); 104 105#if FULL_SYSTEM 106 protected: 107// uint64_t interrupts[TheISA::NumInterruptLevels]; 108// uint64_t intstatus; 109 TheISA::Interrupts interrupts; 110 111 public: 112 virtual void post_interrupt(int int_num, int index); 113 virtual void clear_interrupt(int int_num, int index); 114 virtual void clear_interrupts(); 115 virtual uint64_t get_interrupts(int int_num); 116 117 bool check_interrupts(ThreadContext * tc) const 118 { return interrupts.check_interrupts(tc); } 119 120 class ProfileEvent : public Event 121 { 122 private: 123 BaseCPU *cpu; 124 int interval; 125 126 public: 127 ProfileEvent(BaseCPU *cpu, int interval); 128 void process(); 129 }; 130 ProfileEvent *profileEvent; 131#endif 132 133 protected: 134 std::vector<ThreadContext *> threadContexts; 135 std::vector<TheISA::Predecoder *> predecoders; 136 137 Trace::InstTracer * tracer; 138 139 public: 140 141 /// Provide access to the tracer pointer 142 Trace::InstTracer * getTracer() { return tracer; } 143 144 /// Notify the CPU that the indicated context is now active. The 145 /// delay parameter indicates the number of ticks to wait before 146 /// executing (typically 0 or 1). 147 virtual void activateContext(int thread_num, int delay) {} 148 149 /// Notify the CPU that the indicated context is now suspended. 150 virtual void suspendContext(int thread_num) {} 151 152 /// Notify the CPU that the indicated context is now deallocated. 153 virtual void deallocateContext(int thread_num) {} 154 155 /// Notify the CPU that the indicated context is now halted. 156 virtual void haltContext(int thread_num) {} 157 158 /// Given a Thread Context pointer return the thread num 159 int findContext(ThreadContext *tc); 160 161 /// Given a thread num get tho thread context for it 162 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 163 164 public: 165 struct Params 166 { 167 std::string name; 168 int numberOfThreads; 169 bool deferRegistration; 170 Counter max_insts_any_thread; 171 Counter max_insts_all_threads; 172 Counter max_loads_any_thread; 173 Counter max_loads_all_threads; 174 Tick clock; 175 bool functionTrace; 176 Tick functionTraceStart; 177 System *system; 178 int cpu_id; 179 Trace::InstTracer * tracer; 180 181 Tick phase; 182#if FULL_SYSTEM 183 Tick profile; 184 185 bool do_statistics_insts; 186 bool do_checkpoint_insts; 187 bool do_quiesce; 188#endif 189 Tick progress_interval; 190 BaseCPU *checker; 191 192 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 193 194 Params(); 195 }; 196 197 const Params *params; 198 199 BaseCPU(Params *params); 200 virtual ~BaseCPU(); 201 202 virtual void init(); 203 virtual void startup(); 204 virtual void regStats(); 205 206 virtual void activateWhenReady(int tid) {}; 207 208 void registerThreadContexts(); 209 210 /// Prepare for another CPU to take over execution. When it is 211 /// is ready (drained pipe) it signals the sampler. 212 virtual void switchOut(); 213 214 /// Take over execution from the given CPU. Used for warm-up and 215 /// sampling. 216 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 217 218 /** 219 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 220 * This is a constant for the duration of the simulation. 221 */ 222 int number_of_threads; 223 224 /** 225 * Vector of per-thread instruction-based event queues. Used for 226 * scheduling events based on number of instructions committed by 227 * a particular thread. 228 */ 229 EventQueue **comInstEventQueue; 230 231 /** 232 * Vector of per-thread load-based event queues. Used for 233 * scheduling events based on number of loads committed by 234 *a particular thread. 235 */ 236 EventQueue **comLoadEventQueue; 237 238 System *system; 239 240 Tick phase; 241 242#if FULL_SYSTEM 243 /** 244 * Serialize this object to the given output stream. 245 * @param os The stream to serialize to. 246 */ 247 virtual void serialize(std::ostream &os); 248 249 /** 250 * Reconstruct the state of this object from a checkpoint. 251 * @param cp The checkpoint use. 252 * @param section The section name of this object 253 */ 254 virtual void unserialize(Checkpoint *cp, const std::string §ion); 255 256#endif 257 258 /** 259 * Return pointer to CPU's branch predictor (NULL if none). 260 * @return Branch predictor pointer. 261 */ 262 virtual BranchPred *getBranchPred() { return NULL; }; 263 264 virtual Counter totalInstructions() const { return 0; } 265 266 // Function tracing 267 private: 268 bool functionTracingEnabled; 269 std::ostream *functionTraceStream; 270 Addr currentFunctionStart; 271 Addr currentFunctionEnd; 272 Tick functionEntryTick; 273 void enableFunctionTrace(); 274 void traceFunctionsInternal(Addr pc); 275 276 protected: 277 void traceFunctions(Addr pc) 278 { 279 if (functionTracingEnabled) 280 traceFunctionsInternal(pc); 281 } 282 283 private: 284 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 285 286 public: 287 static int numSimulatedCPUs() { return cpuList.size(); } 288 static Counter numSimulatedInstructions() 289 { 290 Counter total = 0; 291 292 int size = cpuList.size(); 293 for (int i = 0; i < size; ++i) 294 total += cpuList[i]->totalInstructions(); 295 296 return total; 297 } 298 299 public: 300 // Number of CPU cycles simulated 301 Stats::Scalar<> numCycles; 302}; 303 304#endif // __CPU_BASE_HH__ 305