base.hh revision 5099:8ff1345b3ae4
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "base/statistics.hh" 39#include "config/full_system.hh" 40#include "sim/eventq.hh" 41#include "sim/insttracer.hh" 42#include "mem/mem_object.hh" 43 44#if FULL_SYSTEM 45#include "arch/interrupts.hh" 46#endif 47 48class BranchPred; 49class CheckerCPU; 50class ThreadContext; 51class System; 52class Port; 53 54namespace TheISA 55{ 56 class Predecoder; 57} 58 59class CPUProgressEvent : public Event 60{ 61 protected: 62 Tick interval; 63 Counter lastNumInst; 64 BaseCPU *cpu; 65 66 public: 67 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 68 69 void process(); 70 71 virtual const char *description(); 72}; 73 74class BaseCPU : public MemObject 75{ 76 protected: 77 // CPU's clock period in terms of the number of ticks of curTime. 78 Tick clock; 79 // @todo remove me after debugging with legion done 80 Tick instCnt; 81 82 public: 83// Tick currentTick; 84 inline Tick frequency() const { return Clock::Frequency / clock; } 85 inline Tick cycles(int numCycles) const { return clock * numCycles; } 86 inline Tick curCycle() const { return curTick / clock; } 87 inline Tick tickToCycles(Tick val) const { return val / clock; } 88 // @todo remove me after debugging with legion done 89 Tick instCount() { return instCnt; } 90 91 /** The next cycle the CPU should be scheduled, given a cache 92 * access or quiesce event returning on this cycle. This function 93 * may return curTick if the CPU should run on the current cycle. 94 */ 95 Tick nextCycle(); 96 97 /** The next cycle the CPU should be scheduled, given a cache 98 * access or quiesce event returning on the given Tick. This 99 * function may return curTick if the CPU should run on the 100 * current cycle. 101 * @param begin_tick The tick that the event is completing on. 102 */ 103 Tick nextCycle(Tick begin_tick); 104 105#if FULL_SYSTEM 106 protected: 107// uint64_t interrupts[TheISA::NumInterruptLevels]; 108// uint64_t intstatus; 109 TheISA::Interrupts interrupts; 110 111 public: 112 virtual void post_interrupt(int int_num, int index); 113 virtual void clear_interrupt(int int_num, int index); 114 virtual void clear_interrupts(); 115 virtual uint64_t get_interrupts(int int_num); 116 117 bool check_interrupts(ThreadContext * tc) const 118 { return interrupts.check_interrupts(tc); } 119 120 class ProfileEvent : public Event 121 { 122 private: 123 BaseCPU *cpu; 124 int interval; 125 126 public: 127 ProfileEvent(BaseCPU *cpu, int interval); 128 void process(); 129 }; 130 ProfileEvent *profileEvent; 131#endif 132 133 protected: 134 std::vector<ThreadContext *> threadContexts; 135 std::vector<TheISA::Predecoder *> predecoders; 136 137 Trace::InstTracer * tracer; 138 139 public: 140 141 /// Provide access to the tracer pointer 142 Trace::InstTracer * getTracer() { return tracer; } 143 144 /// Notify the CPU that the indicated context is now active. The 145 /// delay parameter indicates the number of ticks to wait before 146 /// executing (typically 0 or 1). 147 virtual void activateContext(int thread_num, int delay) {} 148 149 /// Notify the CPU that the indicated context is now suspended. 150 virtual void suspendContext(int thread_num) {} 151 152 /// Notify the CPU that the indicated context is now deallocated. 153 virtual void deallocateContext(int thread_num) {} 154 155 /// Notify the CPU that the indicated context is now halted. 156 virtual void haltContext(int thread_num) {} 157 158 /// Given a Thread Context pointer return the thread num 159 int findContext(ThreadContext *tc); 160 161 /// Given a thread num get tho thread context for it 162 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 163 164 public: 165 struct Params 166 { 167 std::string name; 168 int numberOfThreads; 169 bool deferRegistration; 170 Counter max_insts_any_thread; 171 Counter max_insts_all_threads; 172 Counter max_loads_any_thread; 173 Counter max_loads_all_threads; 174 Tick clock; 175 bool functionTrace; 176 Tick functionTraceStart; 177 System *system; 178 int cpu_id; 179 Trace::InstTracer * tracer; 180 181 Tick phase; 182#if FULL_SYSTEM 183 Tick profile; 184 185 bool do_statistics_insts; 186 bool do_checkpoint_insts; 187 bool do_quiesce; 188#endif 189 Tick progress_interval; 190 BaseCPU *checker; 191 192 Params(); 193 }; 194 195 const Params *params; 196 197 BaseCPU(Params *params); 198 virtual ~BaseCPU(); 199 200 virtual void init(); 201 virtual void startup(); 202 virtual void regStats(); 203 204 virtual void activateWhenReady(int tid) {}; 205 206 void registerThreadContexts(); 207 208 /// Prepare for another CPU to take over execution. When it is 209 /// is ready (drained pipe) it signals the sampler. 210 virtual void switchOut(); 211 212 /// Take over execution from the given CPU. Used for warm-up and 213 /// sampling. 214 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 215 216 /** 217 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 218 * This is a constant for the duration of the simulation. 219 */ 220 int number_of_threads; 221 222 /** 223 * Vector of per-thread instruction-based event queues. Used for 224 * scheduling events based on number of instructions committed by 225 * a particular thread. 226 */ 227 EventQueue **comInstEventQueue; 228 229 /** 230 * Vector of per-thread load-based event queues. Used for 231 * scheduling events based on number of loads committed by 232 *a particular thread. 233 */ 234 EventQueue **comLoadEventQueue; 235 236 System *system; 237 238 Tick phase; 239 240#if FULL_SYSTEM 241 /** 242 * Serialize this object to the given output stream. 243 * @param os The stream to serialize to. 244 */ 245 virtual void serialize(std::ostream &os); 246 247 /** 248 * Reconstruct the state of this object from a checkpoint. 249 * @param cp The checkpoint use. 250 * @param section The section name of this object 251 */ 252 virtual void unserialize(Checkpoint *cp, const std::string §ion); 253 254#endif 255 256 /** 257 * Return pointer to CPU's branch predictor (NULL if none). 258 * @return Branch predictor pointer. 259 */ 260 virtual BranchPred *getBranchPred() { return NULL; }; 261 262 virtual Counter totalInstructions() const { return 0; } 263 264 // Function tracing 265 private: 266 bool functionTracingEnabled; 267 std::ostream *functionTraceStream; 268 Addr currentFunctionStart; 269 Addr currentFunctionEnd; 270 Tick functionEntryTick; 271 void enableFunctionTrace(); 272 void traceFunctionsInternal(Addr pc); 273 274 protected: 275 void traceFunctions(Addr pc) 276 { 277 if (functionTracingEnabled) 278 traceFunctionsInternal(pc); 279 } 280 281 private: 282 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 283 284 public: 285 static int numSimulatedCPUs() { return cpuList.size(); } 286 static Counter numSimulatedInstructions() 287 { 288 Counter total = 0; 289 290 int size = cpuList.size(); 291 for (int i = 0; i < size; ++i) 292 total += cpuList[i]->totalInstructions(); 293 294 return total; 295 } 296 297 public: 298 // Number of CPU cycles simulated 299 Stats::Scalar<> numCycles; 300}; 301 302#endif // __CPU_BASE_HH__ 303