base.hh revision 3495:884bf1f0c0c9
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "sim/eventq.hh" 40#include "mem/mem_object.hh" 41#include "arch/isa_traits.hh" 42 43class BranchPred; 44class CheckerCPU; 45class ThreadContext; 46class System; 47class Port; 48 49class CPUProgressEvent : public Event 50{ 51 protected: 52 Tick interval; 53 Counter lastNumInst; 54 BaseCPU *cpu; 55 56 public: 57 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 58 59 void process(); 60 61 virtual const char *description(); 62}; 63 64class BaseCPU : public MemObject 65{ 66 protected: 67 // CPU's clock period in terms of the number of ticks of curTime. 68 Tick clock; 69 70 public: 71// Tick currentTick; 72 inline Tick frequency() const { return Clock::Frequency / clock; } 73 inline Tick cycles(int numCycles) const { return clock * numCycles; } 74 inline Tick curCycle() const { return curTick / clock; } 75 76 /** The next cycle the CPU should be scheduled, given a cache 77 * access or quiesce event returning on this cycle. This function 78 * may return curTick if the CPU should run on the current cycle. 79 */ 80 Tick nextCycle(); 81 82 /** The next cycle the CPU should be scheduled, given a cache 83 * access or quiesce event returning on the given Tick. This 84 * function may return curTick if the CPU should run on the 85 * current cycle. 86 * @param begin_tick The tick that the event is completing on. 87 */ 88 Tick nextCycle(Tick begin_tick); 89 90#if FULL_SYSTEM 91 protected: 92 uint64_t interrupts[TheISA::NumInterruptLevels]; 93 uint64_t intstatus; 94 95 public: 96 virtual void post_interrupt(int int_num, int index); 97 virtual void clear_interrupt(int int_num, int index); 98 virtual void clear_interrupts(); 99 bool checkInterrupts; 100 101 bool check_interrupt(int int_num) const { 102 if (int_num > TheISA::NumInterruptLevels) 103 panic("int_num out of bounds\n"); 104 105 return interrupts[int_num] != 0; 106 } 107 108 bool check_interrupts() const { return intstatus != 0; } 109 uint64_t intr_status() const { return intstatus; } 110 111 class ProfileEvent : public Event 112 { 113 private: 114 BaseCPU *cpu; 115 int interval; 116 117 public: 118 ProfileEvent(BaseCPU *cpu, int interval); 119 void process(); 120 }; 121 ProfileEvent *profileEvent; 122#endif 123 124 protected: 125 std::vector<ThreadContext *> threadContexts; 126 127 public: 128 129 /// Notify the CPU that the indicated context is now active. The 130 /// delay parameter indicates the number of ticks to wait before 131 /// executing (typically 0 or 1). 132 virtual void activateContext(int thread_num, int delay) {} 133 134 /// Notify the CPU that the indicated context is now suspended. 135 virtual void suspendContext(int thread_num) {} 136 137 /// Notify the CPU that the indicated context is now deallocated. 138 virtual void deallocateContext(int thread_num) {} 139 140 /// Notify the CPU that the indicated context is now halted. 141 virtual void haltContext(int thread_num) {} 142 143 public: 144 struct Params 145 { 146 std::string name; 147 int numberOfThreads; 148 bool deferRegistration; 149 Counter max_insts_any_thread; 150 Counter max_insts_all_threads; 151 Counter max_loads_any_thread; 152 Counter max_loads_all_threads; 153 Tick clock; 154 bool functionTrace; 155 Tick functionTraceStart; 156 System *system; 157 int cpu_id; 158#if FULL_SYSTEM 159 Tick profile; 160#endif 161 Tick progress_interval; 162 BaseCPU *checker; 163 164 Params(); 165 }; 166 167 const Params *params; 168 169 BaseCPU(Params *params); 170 virtual ~BaseCPU(); 171 172 virtual void init(); 173 virtual void startup(); 174 virtual void regStats(); 175 176 virtual void activateWhenReady(int tid) {}; 177 178 void registerThreadContexts(); 179 180 /// Prepare for another CPU to take over execution. When it is 181 /// is ready (drained pipe) it signals the sampler. 182 virtual void switchOut(); 183 184 /// Take over execution from the given CPU. Used for warm-up and 185 /// sampling. 186 virtual void takeOverFrom(BaseCPU *); 187 188 /** 189 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 190 * This is a constant for the duration of the simulation. 191 */ 192 int number_of_threads; 193 194 /** 195 * Vector of per-thread instruction-based event queues. Used for 196 * scheduling events based on number of instructions committed by 197 * a particular thread. 198 */ 199 EventQueue **comInstEventQueue; 200 201 /** 202 * Vector of per-thread load-based event queues. Used for 203 * scheduling events based on number of loads committed by 204 *a particular thread. 205 */ 206 EventQueue **comLoadEventQueue; 207 208 System *system; 209 210#if FULL_SYSTEM 211 /** 212 * Serialize this object to the given output stream. 213 * @param os The stream to serialize to. 214 */ 215 virtual void serialize(std::ostream &os); 216 217 /** 218 * Reconstruct the state of this object from a checkpoint. 219 * @param cp The checkpoint use. 220 * @param section The section name of this object 221 */ 222 virtual void unserialize(Checkpoint *cp, const std::string §ion); 223 224#endif 225 226 /** 227 * Return pointer to CPU's branch predictor (NULL if none). 228 * @return Branch predictor pointer. 229 */ 230 virtual BranchPred *getBranchPred() { return NULL; }; 231 232 virtual Counter totalInstructions() const { return 0; } 233 234 // Function tracing 235 private: 236 bool functionTracingEnabled; 237 std::ostream *functionTraceStream; 238 Addr currentFunctionStart; 239 Addr currentFunctionEnd; 240 Tick functionEntryTick; 241 void enableFunctionTrace(); 242 void traceFunctionsInternal(Addr pc); 243 244 protected: 245 void traceFunctions(Addr pc) 246 { 247 if (functionTracingEnabled) 248 traceFunctionsInternal(pc); 249 } 250 251 private: 252 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 253 254 public: 255 static int numSimulatedCPUs() { return cpuList.size(); } 256 static Counter numSimulatedInstructions() 257 { 258 Counter total = 0; 259 260 int size = cpuList.size(); 261 for (int i = 0; i < size; ++i) 262 total += cpuList[i]->totalInstructions(); 263 264 return total; 265 } 266 267 public: 268 // Number of CPU cycles simulated 269 Stats::Scalar<> numCycles; 270}; 271 272#endif // __CPU_BASE_HH__ 273