base.hh revision 11423:831c7f2f9e39
110388SAndreas.Sandberg@ARM.com/* 210388SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2013 ARM Limited 310388SAndreas.Sandberg@ARM.com * All rights reserved 410388SAndreas.Sandberg@ARM.com * 510388SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 610388SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 710388SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 810388SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 910388SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 1010388SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 1110388SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 1210388SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 1310388SAndreas.Sandberg@ARM.com * 1410388SAndreas.Sandberg@ARM.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1510388SAndreas.Sandberg@ARM.com * Copyright (c) 2011 Regents of the University of California 1610388SAndreas.Sandberg@ARM.com * All rights reserved. 1710388SAndreas.Sandberg@ARM.com * 1810388SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 1910388SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 2010388SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 2110388SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 2210388SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 2310388SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 2410388SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 2510388SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 2610388SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 2710388SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 2810388SAndreas.Sandberg@ARM.com * 2910388SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010388SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110388SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210388SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310388SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410388SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510388SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610388SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710388SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810388SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910388SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011793Sbrandon.potter@amd.com * 4111793Sbrandon.potter@amd.com * Authors: Steve Reinhardt 4210388SAndreas.Sandberg@ARM.com * Nathan Binkert 4310388SAndreas.Sandberg@ARM.com * Rick Strong 4410388SAndreas.Sandberg@ARM.com */ 4510388SAndreas.Sandberg@ARM.com 4610388SAndreas.Sandberg@ARM.com#ifndef __CPU_BASE_HH__ 4710559Sandreas.hansson@arm.com#define __CPU_BASE_HH__ 4810559Sandreas.hansson@arm.com 4910388SAndreas.Sandberg@ARM.com#include <vector> 5010388SAndreas.Sandberg@ARM.com 5110388SAndreas.Sandberg@ARM.com// Before we do anything else, check if this build is the NULL ISA, 5210388SAndreas.Sandberg@ARM.com// and if so stop here 5310388SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 5410388SAndreas.Sandberg@ARM.com#if THE_ISA == NULL_ISA 5510388SAndreas.Sandberg@ARM.com#include "arch/null/cpu_dummy.hh" 5610388SAndreas.Sandberg@ARM.com#else 5710388SAndreas.Sandberg@ARM.com#include "arch/interrupts.hh" 5810388SAndreas.Sandberg@ARM.com#include "arch/isa_traits.hh" 5910388SAndreas.Sandberg@ARM.com#include "arch/microcode_rom.hh" 6010388SAndreas.Sandberg@ARM.com#include "base/statistics.hh" 6110388SAndreas.Sandberg@ARM.com#include "mem/mem_object.hh" 6210388SAndreas.Sandberg@ARM.com#include "sim/eventq.hh" 6310388SAndreas.Sandberg@ARM.com#include "sim/full_system.hh" 6410388SAndreas.Sandberg@ARM.com#include "sim/insttracer.hh" 6510388SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh" 6610388SAndreas.Sandberg@ARM.com#include "sim/system.hh" 6710388SAndreas.Sandberg@ARM.com#include "debug/Mwait.hh" 6810388SAndreas.Sandberg@ARM.com 6910388SAndreas.Sandberg@ARM.comclass BaseCPU; 7010388SAndreas.Sandberg@ARM.comstruct BaseCPUParams; 7110388SAndreas.Sandberg@ARM.comclass CheckerCPU; 7210388SAndreas.Sandberg@ARM.comclass ThreadContext; 7310388SAndreas.Sandberg@ARM.com 7410388SAndreas.Sandberg@ARM.comstruct AddressMonitor 7510388SAndreas.Sandberg@ARM.com{ 7610388SAndreas.Sandberg@ARM.com AddressMonitor(); 7710388SAndreas.Sandberg@ARM.com bool doMonitor(PacketPtr pkt); 7810388SAndreas.Sandberg@ARM.com 7910602SAndreas.Sandberg@ARM.com bool armed; 8010602SAndreas.Sandberg@ARM.com Addr vAddr; 8110388SAndreas.Sandberg@ARM.com Addr pAddr; 8210388SAndreas.Sandberg@ARM.com uint64_t val; 8310388SAndreas.Sandberg@ARM.com bool waiting; // 0=normal, 1=mwaiting 8410388SAndreas.Sandberg@ARM.com bool gotWakeup; 8510388SAndreas.Sandberg@ARM.com}; 8610388SAndreas.Sandberg@ARM.com 8710388SAndreas.Sandberg@ARM.comclass CPUProgressEvent : public Event 8810388SAndreas.Sandberg@ARM.com{ 8910388SAndreas.Sandberg@ARM.com protected: 9010388SAndreas.Sandberg@ARM.com Tick _interval; 9110388SAndreas.Sandberg@ARM.com Counter lastNumInst; 9210388SAndreas.Sandberg@ARM.com BaseCPU *cpu; 9310388SAndreas.Sandberg@ARM.com bool _repeatEvent; 9410388SAndreas.Sandberg@ARM.com 9510388SAndreas.Sandberg@ARM.com public: 9610388SAndreas.Sandberg@ARM.com CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 9710388SAndreas.Sandberg@ARM.com 9810388SAndreas.Sandberg@ARM.com void process(); 9910388SAndreas.Sandberg@ARM.com 10010388SAndreas.Sandberg@ARM.com void interval(Tick ival) { _interval = ival; } 10110388SAndreas.Sandberg@ARM.com Tick interval() { return _interval; } 10210388SAndreas.Sandberg@ARM.com 10310388SAndreas.Sandberg@ARM.com void repeatEvent(bool repeat) { _repeatEvent = repeat; } 10410388SAndreas.Sandberg@ARM.com 10510388SAndreas.Sandberg@ARM.com virtual const char *description() const; 10610388SAndreas.Sandberg@ARM.com}; 10710388SAndreas.Sandberg@ARM.com 10810388SAndreas.Sandberg@ARM.comclass BaseCPU : public MemObject 10910388SAndreas.Sandberg@ARM.com{ 11010388SAndreas.Sandberg@ARM.com protected: 11110388SAndreas.Sandberg@ARM.com 11210388SAndreas.Sandberg@ARM.com /// Instruction count used for SPARC misc register 11310388SAndreas.Sandberg@ARM.com /// @todo unify this with the counters that cpus individually keep 11410388SAndreas.Sandberg@ARM.com Tick instCnt; 11510388SAndreas.Sandberg@ARM.com 11610388SAndreas.Sandberg@ARM.com // every cpu has an id, put it in the base cpu 11710388SAndreas.Sandberg@ARM.com // Set at initialization, only time a cpuId might change is during a 11810388SAndreas.Sandberg@ARM.com // takeover (which should be done from within the BaseCPU anyway, 11910388SAndreas.Sandberg@ARM.com // therefore no setCpuId() method is provided 12010388SAndreas.Sandberg@ARM.com int _cpuId; 12110388SAndreas.Sandberg@ARM.com 12210388SAndreas.Sandberg@ARM.com /** Each cpu will have a socket ID that corresponds to its physical location 12310388SAndreas.Sandberg@ARM.com * in the system. This is usually used to bucket cpu cores under single DVFS 12410388SAndreas.Sandberg@ARM.com * domain. This information may also be required by the OS to identify the 12510388SAndreas.Sandberg@ARM.com * cpu core grouping (as in the case of ARM via MPIDR register) 12610388SAndreas.Sandberg@ARM.com */ 12710672SAndreas.Sandberg@ARM.com const uint32_t _socketId; 12810672SAndreas.Sandberg@ARM.com 12910672SAndreas.Sandberg@ARM.com /** instruction side request id that must be placed in all requests */ 13010672SAndreas.Sandberg@ARM.com MasterID _instMasterId; 13110672SAndreas.Sandberg@ARM.com 13210388SAndreas.Sandberg@ARM.com /** data side request id that must be placed in all requests */ 13310388SAndreas.Sandberg@ARM.com MasterID _dataMasterId; 13410388SAndreas.Sandberg@ARM.com 13510388SAndreas.Sandberg@ARM.com /** An intrenal representation of a task identifier within gem5. This is 13610388SAndreas.Sandberg@ARM.com * used so the CPU can add which taskId (which is an internal representation 13710388SAndreas.Sandberg@ARM.com * of the OS process ID) to each request so components in the memory system 13810388SAndreas.Sandberg@ARM.com * can track which process IDs are ultimately interacting with them 13910388SAndreas.Sandberg@ARM.com */ 14010388SAndreas.Sandberg@ARM.com uint32_t _taskId; 14110388SAndreas.Sandberg@ARM.com 14210388SAndreas.Sandberg@ARM.com /** The current OS process ID that is executing on this processor. This is 14310388SAndreas.Sandberg@ARM.com * used to generate a taskId */ 14410388SAndreas.Sandberg@ARM.com uint32_t _pid; 14510388SAndreas.Sandberg@ARM.com 14610388SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 14710388SAndreas.Sandberg@ARM.com bool _switchedOut; 14810388SAndreas.Sandberg@ARM.com 14910388SAndreas.Sandberg@ARM.com /** Cache the cache line size that we get from the system */ 15010388SAndreas.Sandberg@ARM.com const unsigned int _cacheLineSize; 15110388SAndreas.Sandberg@ARM.com 15210388SAndreas.Sandberg@ARM.com public: 15310388SAndreas.Sandberg@ARM.com 15410388SAndreas.Sandberg@ARM.com /** 15510388SAndreas.Sandberg@ARM.com * Purely virtual method that returns a reference to the data 15610388SAndreas.Sandberg@ARM.com * port. All subclasses must implement this method. 15710388SAndreas.Sandberg@ARM.com * 15810388SAndreas.Sandberg@ARM.com * @return a reference to the data port 15910388SAndreas.Sandberg@ARM.com */ 16010602SAndreas.Sandberg@ARM.com virtual MasterPort &getDataPort() = 0; 16110602SAndreas.Sandberg@ARM.com 16210388SAndreas.Sandberg@ARM.com /** 16310388SAndreas.Sandberg@ARM.com * Purely virtual method that returns a reference to the instruction 16410388SAndreas.Sandberg@ARM.com * port. All subclasses must implement this method. 16510388SAndreas.Sandberg@ARM.com * 16610388SAndreas.Sandberg@ARM.com * @return a reference to the instruction port 16710388SAndreas.Sandberg@ARM.com */ 16810388SAndreas.Sandberg@ARM.com virtual MasterPort &getInstPort() = 0; 16910388SAndreas.Sandberg@ARM.com 17010388SAndreas.Sandberg@ARM.com /** Reads this CPU's ID. */ 17110388SAndreas.Sandberg@ARM.com int cpuId() const { return _cpuId; } 17210388SAndreas.Sandberg@ARM.com 17310388SAndreas.Sandberg@ARM.com /** Reads this CPU's Socket ID. */ 17410388SAndreas.Sandberg@ARM.com uint32_t socketId() const { return _socketId; } 17510388SAndreas.Sandberg@ARM.com 17610388SAndreas.Sandberg@ARM.com /** Reads this CPU's unique data requestor ID */ 17710388SAndreas.Sandberg@ARM.com MasterID dataMasterId() { return _dataMasterId; } 17810388SAndreas.Sandberg@ARM.com /** Reads this CPU's unique instruction requestor ID */ 17910388SAndreas.Sandberg@ARM.com MasterID instMasterId() { return _instMasterId; } 18010388SAndreas.Sandberg@ARM.com 18110388SAndreas.Sandberg@ARM.com /** 18210388SAndreas.Sandberg@ARM.com * Get a master port on this CPU. All CPUs have a data and 18310388SAndreas.Sandberg@ARM.com * instruction port, and this method uses getDataPort and 18410388SAndreas.Sandberg@ARM.com * getInstPort of the subclasses to resolve the two ports. 18510388SAndreas.Sandberg@ARM.com * 18610388SAndreas.Sandberg@ARM.com * @param if_name the port name 18710388SAndreas.Sandberg@ARM.com * @param idx ignored index 18810388SAndreas.Sandberg@ARM.com * 18910388SAndreas.Sandberg@ARM.com * @return a reference to the port with the given name 19010388SAndreas.Sandberg@ARM.com */ 19110388SAndreas.Sandberg@ARM.com BaseMasterPort &getMasterPort(const std::string &if_name, 19210388SAndreas.Sandberg@ARM.com PortID idx = InvalidPortID) override; 19310388SAndreas.Sandberg@ARM.com 19410388SAndreas.Sandberg@ARM.com /** Get cpu task id */ 19510388SAndreas.Sandberg@ARM.com uint32_t taskId() const { return _taskId; } 19610388SAndreas.Sandberg@ARM.com /** Set cpu task id */ 19710388SAndreas.Sandberg@ARM.com void taskId(uint32_t id) { _taskId = id; } 19810388SAndreas.Sandberg@ARM.com 19910388SAndreas.Sandberg@ARM.com uint32_t getPid() const { return _pid; } 20010388SAndreas.Sandberg@ARM.com void setPid(uint32_t pid) { _pid = pid; } 20110388SAndreas.Sandberg@ARM.com 20210388SAndreas.Sandberg@ARM.com inline void workItemBegin() { numWorkItemsStarted++; } 20310388SAndreas.Sandberg@ARM.com inline void workItemEnd() { numWorkItemsCompleted++; } 20410388SAndreas.Sandberg@ARM.com // @todo remove me after debugging with legion done 20510388SAndreas.Sandberg@ARM.com Tick instCount() { return instCnt; } 20610388SAndreas.Sandberg@ARM.com 20710388SAndreas.Sandberg@ARM.com TheISA::MicrocodeRom microcodeRom; 20810388SAndreas.Sandberg@ARM.com 20910388SAndreas.Sandberg@ARM.com protected: 21010388SAndreas.Sandberg@ARM.com std::vector<TheISA::Interrupts*> interrupts; 21110388SAndreas.Sandberg@ARM.com 21210388SAndreas.Sandberg@ARM.com public: 21310388SAndreas.Sandberg@ARM.com TheISA::Interrupts * 21410388SAndreas.Sandberg@ARM.com getInterruptController(ThreadID tid) 21510388SAndreas.Sandberg@ARM.com { 21610388SAndreas.Sandberg@ARM.com if (interrupts.empty()) 21710388SAndreas.Sandberg@ARM.com return NULL; 21810388SAndreas.Sandberg@ARM.com 21910388SAndreas.Sandberg@ARM.com assert(interrupts.size() > tid); 22010388SAndreas.Sandberg@ARM.com return interrupts[tid]; 22110388SAndreas.Sandberg@ARM.com } 22210388SAndreas.Sandberg@ARM.com 22310388SAndreas.Sandberg@ARM.com virtual void wakeup(ThreadID tid) = 0; 22410388SAndreas.Sandberg@ARM.com 22510388SAndreas.Sandberg@ARM.com void 22610388SAndreas.Sandberg@ARM.com postInterrupt(ThreadID tid, int int_num, int index) 227 { 228 interrupts[tid]->post(int_num, index); 229 if (FullSystem) 230 wakeup(tid); 231 } 232 233 void 234 clearInterrupt(ThreadID tid, int int_num, int index) 235 { 236 interrupts[tid]->clear(int_num, index); 237 } 238 239 void 240 clearInterrupts(ThreadID tid) 241 { 242 interrupts[tid]->clearAll(); 243 } 244 245 bool 246 checkInterrupts(ThreadContext *tc) const 247 { 248 return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc); 249 } 250 251 class ProfileEvent : public Event 252 { 253 private: 254 BaseCPU *cpu; 255 Tick interval; 256 257 public: 258 ProfileEvent(BaseCPU *cpu, Tick interval); 259 void process(); 260 }; 261 ProfileEvent *profileEvent; 262 263 protected: 264 std::vector<ThreadContext *> threadContexts; 265 266 Trace::InstTracer * tracer; 267 268 public: 269 270 271 /** Invalid or unknown Pid. Possible when operating system is not present 272 * or has not assigned a pid yet */ 273 static const uint32_t invldPid = std::numeric_limits<uint32_t>::max(); 274 275 // Mask to align PCs to MachInst sized boundaries 276 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 277 278 /// Provide access to the tracer pointer 279 Trace::InstTracer * getTracer() { return tracer; } 280 281 /// Notify the CPU that the indicated context is now active. 282 virtual void activateContext(ThreadID thread_num); 283 284 /// Notify the CPU that the indicated context is now suspended. 285 /// Check if possible to enter a lower power state 286 virtual void suspendContext(ThreadID thread_num); 287 288 /// Notify the CPU that the indicated context is now halted. 289 virtual void haltContext(ThreadID thread_num) {} 290 291 /// Given a Thread Context pointer return the thread num 292 int findContext(ThreadContext *tc); 293 294 /// Given a thread num get tho thread context for it 295 virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 296 297 /// Get the number of thread contexts available 298 unsigned numContexts() { return threadContexts.size(); } 299 300 public: 301 typedef BaseCPUParams Params; 302 const Params *params() const 303 { return reinterpret_cast<const Params *>(_params); } 304 BaseCPU(Params *params, bool is_checker = false); 305 virtual ~BaseCPU(); 306 307 void init() override; 308 void startup() override; 309 void regStats() override; 310 311 void regProbePoints() override; 312 313 void registerThreadContexts(); 314 315 /** 316 * Prepare for another CPU to take over execution. 317 * 318 * When this method exits, all internal state should have been 319 * flushed. After the method returns, the simulator calls 320 * takeOverFrom() on the new CPU with this CPU as its parameter. 321 */ 322 virtual void switchOut(); 323 324 /** 325 * Load the state of a CPU from the previous CPU object, invoked 326 * on all new CPUs that are about to be switched in. 327 * 328 * A CPU model implementing this method is expected to initialize 329 * its state from the old CPU and connect its memory (unless they 330 * are already connected) to the memories connected to the old 331 * CPU. 332 * 333 * @param cpu CPU to initialize read state from. 334 */ 335 virtual void takeOverFrom(BaseCPU *cpu); 336 337 /** 338 * Flush all TLBs in the CPU. 339 * 340 * This method is mainly used to flush stale translations when 341 * switching CPUs. It is also exported to the Python world to 342 * allow it to request a TLB flush after draining the CPU to make 343 * it easier to compare traces when debugging 344 * handover/checkpointing. 345 */ 346 void flushTLBs(); 347 348 /** 349 * Determine if the CPU is switched out. 350 * 351 * @return True if the CPU is switched out, false otherwise. 352 */ 353 bool switchedOut() const { return _switchedOut; } 354 355 /** 356 * Verify that the system is in a memory mode supported by the 357 * CPU. 358 * 359 * Implementations are expected to query the system for the 360 * current memory mode and ensure that it is what the CPU model 361 * expects. If the check fails, the implementation should 362 * terminate the simulation using fatal(). 363 */ 364 virtual void verifyMemoryMode() const { }; 365 366 /** 367 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 368 * This is a constant for the duration of the simulation. 369 */ 370 ThreadID numThreads; 371 372 /** 373 * Vector of per-thread instruction-based event queues. Used for 374 * scheduling events based on number of instructions committed by 375 * a particular thread. 376 */ 377 EventQueue **comInstEventQueue; 378 379 /** 380 * Vector of per-thread load-based event queues. Used for 381 * scheduling events based on number of loads committed by 382 *a particular thread. 383 */ 384 EventQueue **comLoadEventQueue; 385 386 System *system; 387 388 /** 389 * Get the cache line size of the system. 390 */ 391 inline unsigned int cacheLineSize() const { return _cacheLineSize; } 392 393 /** 394 * Serialize this object to the given output stream. 395 * 396 * @note CPU models should normally overload the serializeThread() 397 * method instead of the serialize() method as this provides a 398 * uniform data format for all CPU models and promotes better code 399 * reuse. 400 * 401 * @param os The stream to serialize to. 402 */ 403 void serialize(CheckpointOut &cp) const override; 404 405 /** 406 * Reconstruct the state of this object from a checkpoint. 407 * 408 * @note CPU models should normally overload the 409 * unserializeThread() method instead of the unserialize() method 410 * as this provides a uniform data format for all CPU models and 411 * promotes better code reuse. 412 413 * @param cp The checkpoint use. 414 * @param section The section name of this object. 415 */ 416 void unserialize(CheckpointIn &cp) override; 417 418 /** 419 * Serialize a single thread. 420 * 421 * @param os The stream to serialize to. 422 * @param tid ID of the current thread. 423 */ 424 virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {}; 425 426 /** 427 * Unserialize one thread. 428 * 429 * @param cp The checkpoint use. 430 * @param section The section name of this thread. 431 * @param tid ID of the current thread. 432 */ 433 virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {}; 434 435 virtual Counter totalInsts() const = 0; 436 437 virtual Counter totalOps() const = 0; 438 439 /** 440 * Schedule an event that exits the simulation loops after a 441 * predefined number of instructions. 442 * 443 * This method is usually called from the configuration script to 444 * get an exit event some time in the future. It is typically used 445 * when the script wants to simulate for a specific number of 446 * instructions rather than ticks. 447 * 448 * @param tid Thread monitor. 449 * @param insts Number of instructions into the future. 450 * @param cause Cause to signal in the exit event. 451 */ 452 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 453 454 /** 455 * Schedule an event that exits the simulation loops after a 456 * predefined number of load operations. 457 * 458 * This method is usually called from the configuration script to 459 * get an exit event some time in the future. It is typically used 460 * when the script wants to simulate for a specific number of 461 * loads rather than ticks. 462 * 463 * @param tid Thread monitor. 464 * @param loads Number of load instructions into the future. 465 * @param cause Cause to signal in the exit event. 466 */ 467 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 468 469 /** 470 * Get the number of instructions executed by the specified thread 471 * on this CPU. Used by Python to control simulation. 472 * 473 * @param tid Thread monitor 474 * @return Number of instructions executed 475 */ 476 uint64_t getCurrentInstCount(ThreadID tid); 477 478 public: 479 /** 480 * @{ 481 * @name PMU Probe points. 482 */ 483 484 /** 485 * Helper method to trigger PMU probes for a committed 486 * instruction. 487 * 488 * @param inst Instruction that just committed 489 */ 490 virtual void probeInstCommit(const StaticInstPtr &inst); 491 492 /** 493 * Helper method to instantiate probe points belonging to this 494 * object. 495 * 496 * @param name Name of the probe point. 497 * @return A unique_ptr to the new probe point. 498 */ 499 ProbePoints::PMUUPtr pmuProbePoint(const char *name); 500 501 /** CPU cycle counter */ 502 ProbePoints::PMUUPtr ppCycles; 503 504 /** 505 * Instruction commit probe point. 506 * 507 * This probe point is triggered whenever one or more instructions 508 * are committed. It is normally triggered once for every 509 * instruction. However, CPU models committing bundles of 510 * instructions may call notify once for the entire bundle. 511 */ 512 ProbePoints::PMUUPtr ppRetiredInsts; 513 514 /** Retired load instructions */ 515 ProbePoints::PMUUPtr ppRetiredLoads; 516 /** Retired store instructions */ 517 ProbePoints::PMUUPtr ppRetiredStores; 518 519 /** Retired branches (any type) */ 520 ProbePoints::PMUUPtr ppRetiredBranches; 521 522 /** @} */ 523 524 525 526 // Function tracing 527 private: 528 bool functionTracingEnabled; 529 std::ostream *functionTraceStream; 530 Addr currentFunctionStart; 531 Addr currentFunctionEnd; 532 Tick functionEntryTick; 533 void enableFunctionTrace(); 534 void traceFunctionsInternal(Addr pc); 535 536 private: 537 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 538 539 public: 540 void traceFunctions(Addr pc) 541 { 542 if (functionTracingEnabled) 543 traceFunctionsInternal(pc); 544 } 545 546 static int numSimulatedCPUs() { return cpuList.size(); } 547 static Counter numSimulatedInsts() 548 { 549 Counter total = 0; 550 551 int size = cpuList.size(); 552 for (int i = 0; i < size; ++i) 553 total += cpuList[i]->totalInsts(); 554 555 return total; 556 } 557 558 static Counter numSimulatedOps() 559 { 560 Counter total = 0; 561 562 int size = cpuList.size(); 563 for (int i = 0; i < size; ++i) 564 total += cpuList[i]->totalOps(); 565 566 return total; 567 } 568 569 public: 570 // Number of CPU cycles simulated 571 Stats::Scalar numCycles; 572 Stats::Scalar numWorkItemsStarted; 573 Stats::Scalar numWorkItemsCompleted; 574 575 private: 576 std::vector<AddressMonitor> addressMonitor; 577 578 public: 579 void armMonitor(ThreadID tid, Addr address); 580 bool mwait(ThreadID tid, PacketPtr pkt); 581 void mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb); 582 AddressMonitor *getCpuAddrMonitor(ThreadID tid) 583 { 584 assert(tid < numThreads); 585 return &addressMonitor[tid]; 586 } 587}; 588 589#endif // THE_ISA == NULL_ISA 590 591#endif // __CPU_BASE_HH__ 592