base.cc revision 3495
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431977SN/A#include "cpu/profile.hh" 443144Shsul@eecs.umich.edu#include "sim/sim_exit.hh" 45161SN/A#include "sim/param.hh" 462190SN/A#include "sim/process.hh" 4756SN/A#include "sim/sim_events.hh" 482190SN/A#include "sim/system.hh" 492SN/A 501062SN/A#include "base/trace.hh" 511062SN/A 522359SN/A// Hack 532359SN/A#include "sim/stat_control.hh" 542359SN/A 552SN/Ausing namespace std; 562SN/A 572SN/Avector<BaseCPU *> BaseCPU::cpuList; 582SN/A 592SN/A// This variable reflects the max number of threads in any CPU. Be 602SN/A// careful to only use it once all the CPUs that you care about have 612SN/A// been initialized 622SN/Aint maxThreadsPerCPU = 1; 632SN/A 643126Sktlim@umich.eduCPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, 653126Sktlim@umich.edu BaseCPU *_cpu) 663126Sktlim@umich.edu : Event(q, Event::Stat_Event_Pri), interval(ival), 673126Sktlim@umich.edu lastNumInst(0), cpu(_cpu) 683126Sktlim@umich.edu{ 693126Sktlim@umich.edu if (interval) 703126Sktlim@umich.edu schedule(curTick + interval); 713126Sktlim@umich.edu} 723126Sktlim@umich.edu 732356SN/Avoid 742356SN/ACPUProgressEvent::process() 752356SN/A{ 762367SN/A Counter temp = cpu->totalInstructions(); 772356SN/A#ifndef NDEBUG 782356SN/A double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); 792367SN/A 802356SN/A DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 812356SN/A cpu->name(), temp - lastNumInst, ipc); 822356SN/A ipc = 0.0; 832367SN/A#else 842367SN/A cprintf("%lli: %s progress event, instructions committed: %lli\n", 852367SN/A curTick, cpu->name(), temp - lastNumInst); 862367SN/A#endif 872356SN/A lastNumInst = temp; 882356SN/A schedule(curTick + interval); 892356SN/A} 902356SN/A 912356SN/Aconst char * 922356SN/ACPUProgressEvent::description() 932356SN/A{ 942356SN/A return "CPU Progress event"; 952356SN/A} 962356SN/A 971858SN/A#if FULL_SYSTEM 981400SN/ABaseCPU::BaseCPU(Params *p) 992881Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), checkInterrupts(true), 1001400SN/A params(p), number_of_threads(p->numberOfThreads), system(p->system) 1012SN/A#else 1021400SN/ABaseCPU::BaseCPU(Params *p) 1032856Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), params(p), 1042378SN/A number_of_threads(p->numberOfThreads), system(p->system) 1052SN/A#endif 1062SN/A{ 1072359SN/A// currentTick = curTick; 1082831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 1091062SN/A 1102SN/A // add self to global list of CPUs 1112SN/A cpuList.push_back(this); 1122SN/A 1132831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 1141062SN/A this); 1151062SN/A 1162SN/A if (number_of_threads > maxThreadsPerCPU) 1172SN/A maxThreadsPerCPU = number_of_threads; 1182SN/A 1192SN/A // allocate per-thread instruction-based event queues 1201354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 1212SN/A for (int i = 0; i < number_of_threads; ++i) 122503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 1232SN/A 1242SN/A // 1252SN/A // set up instruction-count-based termination events, if any 1262SN/A // 1271400SN/A if (p->max_insts_any_thread != 0) 1282SN/A for (int i = 0; i < number_of_threads; ++i) 1293144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max instruction count", 1303144Shsul@eecs.umich.edu p->max_insts_any_thread, 0, 1313144Shsul@eecs.umich.edu comInstEventQueue[i]); 1322SN/A 1331400SN/A if (p->max_insts_all_threads != 0) { 1342SN/A // allocate & initialize shared downcounter: each event will 1352SN/A // decrement this when triggered; simulation will terminate 1362SN/A // when counter reaches 0 1372SN/A int *counter = new int; 1382SN/A *counter = number_of_threads; 1392SN/A for (int i = 0; i < number_of_threads; ++i) 140503SN/A new CountedExitEvent(comInstEventQueue[i], 1412SN/A "all threads reached the max instruction count", 1421400SN/A p->max_insts_all_threads, *counter); 1432SN/A } 1442SN/A 145124SN/A // allocate per-thread load-based event queues 1461354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 147124SN/A for (int i = 0; i < number_of_threads; ++i) 148124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 149124SN/A 150124SN/A // 151124SN/A // set up instruction-count-based termination events, if any 152124SN/A // 1531400SN/A if (p->max_loads_any_thread != 0) 154124SN/A for (int i = 0; i < number_of_threads; ++i) 1553144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max load count", 1563144Shsul@eecs.umich.edu p->max_loads_any_thread, 0, 1573144Shsul@eecs.umich.edu comLoadEventQueue[i]); 158124SN/A 1591400SN/A if (p->max_loads_all_threads != 0) { 160124SN/A // allocate & initialize shared downcounter: each event will 161124SN/A // decrement this when triggered; simulation will terminate 162124SN/A // when counter reaches 0 163124SN/A int *counter = new int; 164124SN/A *counter = number_of_threads; 165124SN/A for (int i = 0; i < number_of_threads; ++i) 166124SN/A new CountedExitEvent(comLoadEventQueue[i], 167124SN/A "all threads reached the max load count", 1681400SN/A p->max_loads_all_threads, *counter); 169124SN/A } 170124SN/A 1711858SN/A#if FULL_SYSTEM 1722SN/A memset(interrupts, 0, sizeof(interrupts)); 1732SN/A intstatus = 0; 1742SN/A#endif 1751191SN/A 1761191SN/A functionTracingEnabled = false; 1771400SN/A if (p->functionTrace) { 1781388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1791191SN/A currentFunctionStart = currentFunctionEnd = 0; 1801400SN/A functionEntryTick = p->functionTraceStart; 1811191SN/A 1821400SN/A if (p->functionTraceStart == 0) { 1831191SN/A functionTracingEnabled = true; 1841191SN/A } else { 1851191SN/A Event *e = 1861191SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1871191SN/A true); 1881400SN/A e->schedule(p->functionTraceStart); 1891191SN/A } 1901191SN/A } 1911917SN/A#if FULL_SYSTEM 1921917SN/A profileEvent = NULL; 1931917SN/A if (params->profile) 1941917SN/A profileEvent = new ProfileEvent(this, params->profile); 1951917SN/A#endif 1962SN/A} 1972SN/A 1981917SN/ABaseCPU::Params::Params() 1991917SN/A{ 2001917SN/A#if FULL_SYSTEM 2011917SN/A profile = false; 2021917SN/A#endif 2032315SN/A checker = NULL; 2041917SN/A} 2051191SN/A 2061191SN/Avoid 2071191SN/ABaseCPU::enableFunctionTrace() 2081191SN/A{ 2091191SN/A functionTracingEnabled = true; 2101191SN/A} 2111191SN/A 2121191SN/ABaseCPU::~BaseCPU() 2131191SN/A{ 2141191SN/A} 2151191SN/A 2161129SN/Avoid 2171129SN/ABaseCPU::init() 2181129SN/A{ 2191400SN/A if (!params->deferRegistration) 2202680Sktlim@umich.edu registerThreadContexts(); 2211129SN/A} 222180SN/A 2232SN/Avoid 2241917SN/ABaseCPU::startup() 2251917SN/A{ 2261917SN/A#if FULL_SYSTEM 2271917SN/A if (!params->deferRegistration && profileEvent) 2281917SN/A profileEvent->schedule(curTick); 2291917SN/A#endif 2302356SN/A 2312356SN/A if (params->progress_interval) { 2322356SN/A new CPUProgressEvent(&mainEventQueue, params->progress_interval, 2332356SN/A this); 2342356SN/A } 2351917SN/A} 2361917SN/A 2371917SN/A 2381917SN/Avoid 2392SN/ABaseCPU::regStats() 2402SN/A{ 241729SN/A using namespace Stats; 242707SN/A 243707SN/A numCycles 244707SN/A .name(name() + ".numCycles") 245707SN/A .desc("number of cpu cycles simulated") 246707SN/A ; 247707SN/A 2482680Sktlim@umich.edu int size = threadContexts.size(); 2492SN/A if (size > 1) { 2502SN/A for (int i = 0; i < size; ++i) { 2512SN/A stringstream namestr; 2522SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2532680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2542SN/A } 2552SN/A } else if (size == 1) 2562680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2572190SN/A 2582190SN/A#if FULL_SYSTEM 2592190SN/A#endif 2602SN/A} 2612SN/A 2623495Sktlim@umich.eduTick 2633495Sktlim@umich.eduBaseCPU::nextCycle() 2643495Sktlim@umich.edu{ 2653495Sktlim@umich.edu Tick next_tick = curTick + clock - 1; 2663495Sktlim@umich.edu next_tick -= (next_tick % clock); 2673495Sktlim@umich.edu return next_tick; 2683495Sktlim@umich.edu} 2693495Sktlim@umich.edu 2703495Sktlim@umich.eduTick 2713495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 2723495Sktlim@umich.edu{ 2733495Sktlim@umich.edu Tick next_tick = begin_tick; 2743495Sktlim@umich.edu 2753495Sktlim@umich.edu while (next_tick < curTick) 2763495Sktlim@umich.edu next_tick += clock; 2773495Sktlim@umich.edu 2783495Sktlim@umich.edu next_tick -= (next_tick % clock); 2793495Sktlim@umich.edu assert(next_tick >= curTick); 2803495Sktlim@umich.edu return next_tick; 2813495Sktlim@umich.edu} 282180SN/A 283180SN/Avoid 2842680Sktlim@umich.eduBaseCPU::registerThreadContexts() 285180SN/A{ 2862680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2872680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2882378SN/A 2891858SN/A#if FULL_SYSTEM 2901806SN/A int id = params->cpu_id; 2911806SN/A if (id != -1) 2921806SN/A id += i; 293180SN/A 2942680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 295180SN/A#else 2962680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 297180SN/A#endif 298180SN/A } 299180SN/A} 300180SN/A 301180SN/A 302180SN/Avoid 3032798Sktlim@umich.eduBaseCPU::switchOut() 304180SN/A{ 3052359SN/A// panic("This CPU doesn't support sampling!"); 3062359SN/A#if FULL_SYSTEM 3072359SN/A if (profileEvent && profileEvent->scheduled()) 3082359SN/A profileEvent->deschedule(); 3092359SN/A#endif 310180SN/A} 311180SN/A 312180SN/Avoid 313180SN/ABaseCPU::takeOverFrom(BaseCPU *oldCPU) 314180SN/A{ 3152680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 316180SN/A 3172680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3182680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3192680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 320180SN/A 3212680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3222651Ssaidi@eecs.umich.edu 3232680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3242651Ssaidi@eecs.umich.edu 3252680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 3261858SN/A#if FULL_SYSTEM 3272680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 328180SN/A#else 3292680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 3302680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 331180SN/A#endif 3322359SN/A 3332359SN/A// TheISA::compareXCs(oldXC, newXC); 334180SN/A } 335605SN/A 3361858SN/A#if FULL_SYSTEM 3372107SN/A for (int i = 0; i < TheISA::NumInterruptLevels; ++i) 338605SN/A interrupts[i] = oldCPU->interrupts[i]; 339605SN/A intstatus = oldCPU->intstatus; 3402359SN/A checkInterrupts = oldCPU->checkInterrupts; 3412254SN/A 3422680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 3432680Sktlim@umich.edu threadContexts[i]->profileClear(); 3442254SN/A 3452359SN/A // The Sampler must take care of this! 3462359SN/A// if (profileEvent) 3472359SN/A// profileEvent->schedule(curTick); 348612SN/A#endif 349180SN/A} 350180SN/A 351180SN/A 3521858SN/A#if FULL_SYSTEM 3531917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 3541917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 3551917SN/A{ } 3561917SN/A 3571917SN/Avoid 3581917SN/ABaseCPU::ProfileEvent::process() 3591917SN/A{ 3602680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 3612680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 3622680Sktlim@umich.edu tc->profileSample(); 3631917SN/A } 3642254SN/A 3651917SN/A schedule(curTick + interval); 3661917SN/A} 3671917SN/A 3682SN/Avoid 3692SN/ABaseCPU::post_interrupt(int int_num, int index) 3702SN/A{ 3712SN/A DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 3722SN/A 3732107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3742SN/A panic("int_num out of bounds\n"); 3752SN/A 376822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3772SN/A panic("int_num out of bounds\n"); 3782SN/A 3791133SN/A checkInterrupts = true; 3802SN/A interrupts[int_num] |= 1 << index; 3812SN/A intstatus |= (ULL(1) << int_num); 3822SN/A} 3832SN/A 3842SN/Avoid 3852SN/ABaseCPU::clear_interrupt(int int_num, int index) 3862SN/A{ 3872SN/A DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 3882SN/A 3892107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3902SN/A panic("int_num out of bounds\n"); 3912SN/A 392822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3932SN/A panic("int_num out of bounds\n"); 3942SN/A 3952SN/A interrupts[int_num] &= ~(1 << index); 3962SN/A if (interrupts[int_num] == 0) 3972SN/A intstatus &= ~(ULL(1) << int_num); 3982SN/A} 3992SN/A 4002SN/Avoid 4012SN/ABaseCPU::clear_interrupts() 4022SN/A{ 4032SN/A DPRINTF(Interrupt, "Interrupts all cleared\n"); 4042SN/A 4052SN/A memset(interrupts, 0, sizeof(interrupts)); 4062SN/A intstatus = 0; 4072SN/A} 4082SN/A 409921SN/A 410921SN/Avoid 411921SN/ABaseCPU::serialize(std::ostream &os) 412921SN/A{ 4132107SN/A SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 414921SN/A SERIALIZE_SCALAR(intstatus); 415921SN/A} 416921SN/A 417921SN/Avoid 418921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 419921SN/A{ 4202107SN/A UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 421921SN/A UNSERIALIZE_SCALAR(intstatus); 422921SN/A} 423921SN/A 4242SN/A#endif // FULL_SYSTEM 4252SN/A 4261191SN/Avoid 4271191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 4281191SN/A{ 4291191SN/A if (!debugSymbolTable) 4301191SN/A return; 4311191SN/A 4321191SN/A // if pc enters different function, print new function symbol and 4331191SN/A // update saved range. Otherwise do nothing. 4341191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 4351191SN/A string sym_str; 4361191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 4371191SN/A currentFunctionStart, 4381191SN/A currentFunctionEnd); 4391191SN/A 4401191SN/A if (!found) { 4411191SN/A // no symbol found: use addr as label 4421191SN/A sym_str = csprintf("0x%x", pc); 4431191SN/A currentFunctionStart = pc; 4441191SN/A currentFunctionEnd = pc + 1; 4451191SN/A } 4461191SN/A 4471191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 4481191SN/A curTick - functionEntryTick, curTick, sym_str); 4491191SN/A functionEntryTick = curTick; 4501191SN/A } 4511191SN/A} 4521191SN/A 4531191SN/A 4542SN/ADEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 455