base.cc revision 10529
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 481388SN/A#include <iostream> 498229Snate@binkert.org#include <sstream> 502SN/A#include <string> 512SN/A 527781SAli.Saidi@ARM.com#include "arch/tlb.hh" 538229Snate@binkert.org#include "base/loader/symtab.hh" 541191SN/A#include "base/cprintf.hh" 551191SN/A#include "base/misc.hh" 561388SN/A#include "base/output.hh" 575529Snate@binkert.org#include "base/trace.hh" 5810529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 591717SN/A#include "cpu/base.hh" 602651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 618229Snate@binkert.org#include "cpu/profile.hh" 622680Sktlim@umich.edu#include "cpu/thread_context.hh" 6310529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 648232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6510529Smorr@cs.wisc.edu#include "mem/page_table.hh" 665529Snate@binkert.org#include "params/BaseCPU.hh" 678779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 682190SN/A#include "sim/process.hh" 6956SN/A#include "sim/sim_events.hh" 708229Snate@binkert.org#include "sim/sim_exit.hh" 712190SN/A#include "sim/system.hh" 722SN/A 732359SN/A// Hack 742359SN/A#include "sim/stat_control.hh" 752359SN/A 762SN/Ausing namespace std; 772SN/A 782SN/Avector<BaseCPU *> BaseCPU::cpuList; 792SN/A 802SN/A// This variable reflects the max number of threads in any CPU. Be 812SN/A// careful to only use it once all the CPUs that you care about have 822SN/A// been initialized 832SN/Aint maxThreadsPerCPU = 1; 842SN/A 855606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 866144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 876144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 883126Sktlim@umich.edu{ 896144Sksewell@umich.edu if (_interval) 907823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 913126Sktlim@umich.edu} 923126Sktlim@umich.edu 932356SN/Avoid 942356SN/ACPUProgressEvent::process() 952356SN/A{ 968834Satgutier@umich.edu Counter temp = cpu->totalOps(); 972356SN/A#ifndef NDEBUG 989179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 992367SN/A 1006144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1016144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1026144Sksewell@umich.edu ipc); 1032356SN/A ipc = 0.0; 1042367SN/A#else 1056144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1067823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1076144Sksewell@umich.edu temp - lastNumInst); 1082367SN/A#endif 1092356SN/A lastNumInst = temp; 1106144Sksewell@umich.edu 1116144Sksewell@umich.edu if (_repeatEvent) 1127823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1132356SN/A} 1142356SN/A 1152356SN/Aconst char * 1165336Shines@cs.fsu.eduCPUProgressEvent::description() const 1172356SN/A{ 1184873Sstever@eecs.umich.edu return "CPU Progress"; 1192356SN/A} 1202356SN/A 1218876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12210190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1238832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1248832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1259332Sdam.sunwoo@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 1269814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1279220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 12810529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 12910529Smorr@cs.wisc.edu addressMonitor() 1302SN/A{ 1315712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1325712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1335712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1345712Shsul@eecs.umich.edu } 1355712Shsul@eecs.umich.edu 1362SN/A // add self to global list of CPUs 1372SN/A cpuList.push_back(this); 1382SN/A 13910190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 14010190Sakash.bagdia@arm.com _cpuId, _socketId); 1415712Shsul@eecs.umich.edu 1426221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1436221Snate@binkert.org maxThreadsPerCPU = numThreads; 1442SN/A 1452SN/A // allocate per-thread instruction-based event queues 1466221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1486221Snate@binkert.org comInstEventQueue[tid] = 1496221Snate@binkert.org new EventQueue("instruction-based event queue"); 1502SN/A 1512SN/A // 1522SN/A // set up instruction-count-based termination events, if any 1532SN/A // 1545606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1555606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1569749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1579749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1585606Snate@binkert.org } 1592SN/A 1609647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1619647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1629647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1639647Sdam.sunwoo@arm.com // exitting the simulation loop. 1649647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1659647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1669749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1679749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1689647Sdam.sunwoo@arm.com } 1699647Sdam.sunwoo@arm.com 1701400SN/A if (p->max_insts_all_threads != 0) { 1715606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1725606Snate@binkert.org 1732SN/A // allocate & initialize shared downcounter: each event will 1742SN/A // decrement this when triggered; simulation will terminate 1752SN/A // when counter reaches 0 1762SN/A int *counter = new int; 1776221Snate@binkert.org *counter = numThreads; 1786221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1795606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1806670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1815606Snate@binkert.org } 1822SN/A } 1832SN/A 184124SN/A // allocate per-thread load-based event queues 1856221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1866221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1876221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 188124SN/A 189124SN/A // 190124SN/A // set up instruction-count-based termination events, if any 191124SN/A // 1925606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1935606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1949749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1959749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 1965606Snate@binkert.org } 197124SN/A 1981400SN/A if (p->max_loads_all_threads != 0) { 1995606Snate@binkert.org const char *cause = "all threads reached the max load count"; 200124SN/A // allocate & initialize shared downcounter: each event will 201124SN/A // decrement this when triggered; simulation will terminate 202124SN/A // when counter reaches 0 203124SN/A int *counter = new int; 2046221Snate@binkert.org *counter = numThreads; 2056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2065606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2076221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2085606Snate@binkert.org } 209124SN/A } 210124SN/A 2111191SN/A functionTracingEnabled = false; 2125529Snate@binkert.org if (p->function_trace) { 2138634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2148634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2158634Schris.emmons@arm.com if (!functionTraceStream) 2168634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2178634Schris.emmons@arm.com 2181191SN/A currentFunctionStart = currentFunctionEnd = 0; 2195529Snate@binkert.org functionEntryTick = p->function_trace_start; 2201191SN/A 2215529Snate@binkert.org if (p->function_trace_start == 0) { 2221191SN/A functionTracingEnabled = true; 2231191SN/A } else { 2245606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2255606Snate@binkert.org Event *event = new wrap(this, true); 2265606Snate@binkert.org schedule(event, p->function_trace_start); 2271191SN/A } 2281191SN/A } 2298876Sandreas.hansson@arm.com 2308876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2318876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2329433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 2338876Sandreas.hansson@arm.com if (interrupts) { 2348876Sandreas.hansson@arm.com interrupts->setCPU(this); 2358876Sandreas.hansson@arm.com } else { 2368876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2378876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2388876Sandreas.hansson@arm.com } 2398876Sandreas.hansson@arm.com } 2405810Sgblack@eecs.umich.edu 2418779Sgblack@eecs.umich.edu if (FullSystem) { 2428779Sgblack@eecs.umich.edu if (params()->profile) 2438779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2448779Sgblack@eecs.umich.edu } 2455529Snate@binkert.org tracer = params()->tracer; 2469384SAndreas.Sandberg@arm.com 2479384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2489384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2499384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2509384SAndreas.Sandberg@arm.com } 2511917SN/A} 2521191SN/A 2531191SN/Avoid 2541191SN/ABaseCPU::enableFunctionTrace() 2551191SN/A{ 2561191SN/A functionTracingEnabled = true; 2571191SN/A} 2581191SN/A 2591191SN/ABaseCPU::~BaseCPU() 2601191SN/A{ 2619086Sandreas.hansson@arm.com delete profileEvent; 2629086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2639086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2641191SN/A} 2651191SN/A 2661129SN/Avoid 26710529Smorr@cs.wisc.eduBaseCPU::armMonitor(Addr address) 26810529Smorr@cs.wisc.edu{ 26910529Smorr@cs.wisc.edu addressMonitor.armed = true; 27010529Smorr@cs.wisc.edu addressMonitor.vAddr = address; 27110529Smorr@cs.wisc.edu addressMonitor.pAddr = 0x0; 27210529Smorr@cs.wisc.edu DPRINTF(Mwait,"Armed monitor (vAddr=0x%lx)\n", address); 27310529Smorr@cs.wisc.edu} 27410529Smorr@cs.wisc.edu 27510529Smorr@cs.wisc.edubool 27610529Smorr@cs.wisc.eduBaseCPU::mwait(PacketPtr pkt) 27710529Smorr@cs.wisc.edu{ 27810529Smorr@cs.wisc.edu if(addressMonitor.gotWakeup == false) { 27910529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 28010529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 28110529Smorr@cs.wisc.edu 28210529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 28310529Smorr@cs.wisc.edu addressMonitor.pAddr = pkt->getAddr() & mask; 28410529Smorr@cs.wisc.edu addressMonitor.waiting = true; 28510529Smorr@cs.wisc.edu 28610529Smorr@cs.wisc.edu DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 28710529Smorr@cs.wisc.edu addressMonitor.vAddr, addressMonitor.pAddr); 28810529Smorr@cs.wisc.edu return true; 28910529Smorr@cs.wisc.edu } else { 29010529Smorr@cs.wisc.edu addressMonitor.gotWakeup = false; 29110529Smorr@cs.wisc.edu return false; 29210529Smorr@cs.wisc.edu } 29310529Smorr@cs.wisc.edu} 29410529Smorr@cs.wisc.edu 29510529Smorr@cs.wisc.eduvoid 29610529Smorr@cs.wisc.eduBaseCPU::mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb) 29710529Smorr@cs.wisc.edu{ 29810529Smorr@cs.wisc.edu Request req; 29910529Smorr@cs.wisc.edu Addr addr = addressMonitor.vAddr; 30010529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 30110529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 30210529Smorr@cs.wisc.edu int size = block_size; 30310529Smorr@cs.wisc.edu 30410529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 30510529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 30610529Smorr@cs.wisc.edu 30710529Smorr@cs.wisc.edu if (secondAddr > addr) 30810529Smorr@cs.wisc.edu size = secondAddr - addr; 30910529Smorr@cs.wisc.edu 31010529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 31110529Smorr@cs.wisc.edu 31210529Smorr@cs.wisc.edu // translate to physical address 31310529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 31410529Smorr@cs.wisc.edu assert(fault == NoFault); 31510529Smorr@cs.wisc.edu 31610529Smorr@cs.wisc.edu addressMonitor.pAddr = req.getPaddr() & mask; 31710529Smorr@cs.wisc.edu addressMonitor.waiting = true; 31810529Smorr@cs.wisc.edu 31910529Smorr@cs.wisc.edu DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 32010529Smorr@cs.wisc.edu addressMonitor.vAddr, addressMonitor.pAddr); 32110529Smorr@cs.wisc.edu} 32210529Smorr@cs.wisc.edu 32310529Smorr@cs.wisc.eduvoid 3241129SN/ABaseCPU::init() 3251129SN/A{ 3269523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3272680Sktlim@umich.edu registerThreadContexts(); 3289523SAndreas.Sandberg@ARM.com 3299523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3309523SAndreas.Sandberg@ARM.com } 3311129SN/A} 332180SN/A 3332SN/Avoid 3341917SN/ABaseCPU::startup() 3351917SN/A{ 3368779Sgblack@eecs.umich.edu if (FullSystem) { 3379433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3388779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3398779Sgblack@eecs.umich.edu } 3402356SN/A 3415529Snate@binkert.org if (params()->progress_interval) { 3429179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3432356SN/A } 3441917SN/A} 3451917SN/A 34610464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 34710464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 34810464SAndreas.Sandberg@ARM.com{ 34910464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 35010464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 35110464SAndreas.Sandberg@ARM.com 35210464SAndreas.Sandberg@ARM.com return ptr; 35310464SAndreas.Sandberg@ARM.com} 35410464SAndreas.Sandberg@ARM.com 35510464SAndreas.Sandberg@ARM.comvoid 35610464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 35710464SAndreas.Sandberg@ARM.com{ 35810464SAndreas.Sandberg@ARM.com ppCycles = pmuProbePoint("Cycles"); 35910464SAndreas.Sandberg@ARM.com 36010464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 36110464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 36210464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 36310464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 36410464SAndreas.Sandberg@ARM.com} 36510464SAndreas.Sandberg@ARM.com 36610464SAndreas.Sandberg@ARM.comvoid 36710464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 36810464SAndreas.Sandberg@ARM.com{ 36910464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 37010464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 37110464SAndreas.Sandberg@ARM.com 37210464SAndreas.Sandberg@ARM.com 37310464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 37410464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 37510464SAndreas.Sandberg@ARM.com 37610464SAndreas.Sandberg@ARM.com if (inst->isStore()) 37710464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 37810464SAndreas.Sandberg@ARM.com 37910464SAndreas.Sandberg@ARM.com if (inst->isControl()) 38010464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 38110464SAndreas.Sandberg@ARM.com} 3821917SN/A 3831917SN/Avoid 3842SN/ABaseCPU::regStats() 3852SN/A{ 386729SN/A using namespace Stats; 387707SN/A 388707SN/A numCycles 389707SN/A .name(name() + ".numCycles") 390707SN/A .desc("number of cpu cycles simulated") 391707SN/A ; 392707SN/A 3937914SBrad.Beckmann@amd.com numWorkItemsStarted 3947914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 3957914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 3967914SBrad.Beckmann@amd.com ; 3977914SBrad.Beckmann@amd.com 3987914SBrad.Beckmann@amd.com numWorkItemsCompleted 3997914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4007914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4017914SBrad.Beckmann@amd.com ; 4027914SBrad.Beckmann@amd.com 4032680Sktlim@umich.edu int size = threadContexts.size(); 4042SN/A if (size > 1) { 4052SN/A for (int i = 0; i < size; ++i) { 4062SN/A stringstream namestr; 4072SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4082680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4092SN/A } 4102SN/A } else if (size == 1) 4112680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4122SN/A} 4132SN/A 4149294Sandreas.hansson@arm.comBaseMasterPort & 4159294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4168850Sandreas.hansson@arm.com{ 4178850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4188850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4198850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4209608Sandreas.hansson@arm.com // return a MasterPort pointer. 4218850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4228922Swilliam.wang@arm.com return getDataPort(); 4238850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4248922Swilliam.wang@arm.com return getInstPort(); 4258850Sandreas.hansson@arm.com else 4268922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4278850Sandreas.hansson@arm.com} 4288850Sandreas.hansson@arm.com 429180SN/Avoid 4302680Sktlim@umich.eduBaseCPU::registerThreadContexts() 431180SN/A{ 4326221Snate@binkert.org ThreadID size = threadContexts.size(); 4336221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4346221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4352378SN/A 4365718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 4375718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 4385718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 4395718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 4405718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 4415718Shsul@eecs.umich.edu * I'll just do this for now 4425718Shsul@eecs.umich.edu */ 4436221Snate@binkert.org if (numThreads == 1) 4445718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 4455718Shsul@eecs.umich.edu else 4465718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 4478779Sgblack@eecs.umich.edu 4488779Sgblack@eecs.umich.edu if (!FullSystem) 4498779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 450180SN/A } 451180SN/A} 452180SN/A 453180SN/A 4544000Ssaidi@eecs.umich.eduint 4554000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 4564000Ssaidi@eecs.umich.edu{ 4576221Snate@binkert.org ThreadID size = threadContexts.size(); 4586221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4596221Snate@binkert.org if (tc == threadContexts[tid]) 4606221Snate@binkert.org return tid; 4614000Ssaidi@eecs.umich.edu } 4624000Ssaidi@eecs.umich.edu return 0; 4634000Ssaidi@eecs.umich.edu} 4644000Ssaidi@eecs.umich.edu 465180SN/Avoid 4662798Sktlim@umich.eduBaseCPU::switchOut() 467180SN/A{ 4689430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 4699430SAndreas.Sandberg@ARM.com _switchedOut = true; 4702359SN/A if (profileEvent && profileEvent->scheduled()) 4715606Snate@binkert.org deschedule(profileEvent); 4729446SAndreas.Sandberg@ARM.com 4739446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 4749446SAndreas.Sandberg@ARM.com // it gets switched in later. 4759446SAndreas.Sandberg@ARM.com flushTLBs(); 476180SN/A} 477180SN/A 478180SN/Avoid 4798737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 480180SN/A{ 4812680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 4829152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 4839430SAndreas.Sandberg@ARM.com assert(_switchedOut); 4849430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 4859332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 4869332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 4879430SAndreas.Sandberg@ARM.com _switchedOut = false; 4885712Shsul@eecs.umich.edu 4896221Snate@binkert.org ThreadID size = threadContexts.size(); 4906221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4912680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 4922680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 493180SN/A 4942680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 4952651Ssaidi@eecs.umich.edu 4962680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 4972651Ssaidi@eecs.umich.edu 4985714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 4995715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 5005714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 5012359SN/A 5025875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 5035875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 5045875Ssteve.reinhardt@amd.com * point. 5055875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 5065217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 5075875Ssteve.reinhardt@amd.com */ 5087781SAli.Saidi@ARM.com 5099294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 5109294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 5119294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 5129294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 5137781SAli.Saidi@ARM.com 5147781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 5159178Sandreas.hansson@arm.com if (new_itb_port) { 5169178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 5177781SAli.Saidi@ARM.com assert(old_itb_port); 5189178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 5199294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 5209178Sandreas.hansson@arm.com old_itb_port->unbind(); 5218922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 5227781SAli.Saidi@ARM.com } 5239178Sandreas.hansson@arm.com if (new_dtb_port) { 5249178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 5257781SAli.Saidi@ARM.com assert(old_dtb_port); 5269178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 5279294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 5289178Sandreas.hansson@arm.com old_dtb_port->unbind(); 5298922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 5307781SAli.Saidi@ARM.com } 53110194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 53210194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 5338733Sgeoffrey.blake@arm.com 5348887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 5358887Sgeoffrey.blake@arm.com // objects over in the switch 5368887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 5378887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 5388887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 5399294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 5408922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 5419294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 5428922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 5439294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 5448922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 5459294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 5468922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 5478733Sgeoffrey.blake@arm.com 54810194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 54910194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 55010194SGeoffrey.Blake@arm.com 5518887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 5529178Sandreas.hansson@arm.com if (new_checker_itb_port) { 5539178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 5548887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 5559178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 5569294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 5579294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 5589178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 5598922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 5608887Sgeoffrey.blake@arm.com } 5619178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 5629178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 5638887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 5649178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 5659294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 5669294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 5679178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 5688922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 5698887Sgeoffrey.blake@arm.com } 5708733Sgeoffrey.blake@arm.com } 571180SN/A } 572605SN/A 5733520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 5745810Sgblack@eecs.umich.edu interrupts->setCPU(this); 5759152Satgutier@umich.edu oldCPU->interrupts = NULL; 5762254SN/A 5778779Sgblack@eecs.umich.edu if (FullSystem) { 5788779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 5798779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 5802254SN/A 5818779Sgblack@eecs.umich.edu if (profileEvent) 5828779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 5838779Sgblack@eecs.umich.edu } 5844192Sktlim@umich.edu 5859178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 5869178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 5879178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 5889178Sandreas.hansson@arm.com // we are switching to. 5899178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 5909178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 5919294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 5929178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 5939178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 5944192Sktlim@umich.edu 5959178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 5969178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 5979294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 5989178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 5999178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 600180SN/A} 601180SN/A 6029446SAndreas.Sandberg@ARM.comvoid 6039446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 6049446SAndreas.Sandberg@ARM.com{ 6059446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 6069446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 6079446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 6089446SAndreas.Sandberg@ARM.com 6099446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 6109446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 6119446SAndreas.Sandberg@ARM.com if (checker) { 6129446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 6139446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 6149446SAndreas.Sandberg@ARM.com } 6159446SAndreas.Sandberg@ARM.com } 6169446SAndreas.Sandberg@ARM.com} 6179446SAndreas.Sandberg@ARM.com 618180SN/A 6195536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 6205606Snate@binkert.org : cpu(_cpu), interval(_interval) 6211917SN/A{ } 6221917SN/A 6231917SN/Avoid 6241917SN/ABaseCPU::ProfileEvent::process() 6251917SN/A{ 6266221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 6276221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 6282680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 6292680Sktlim@umich.edu tc->profileSample(); 6301917SN/A } 6312254SN/A 6327823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 6331917SN/A} 6341917SN/A 6352SN/Avoid 636921SN/ABaseCPU::serialize(std::ostream &os) 637921SN/A{ 6384000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 6399332Sdam.sunwoo@arm.com 6409448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6419448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 6429448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 6439448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 6449448SAndreas.Sandberg@ARM.com * system. */ 6459448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 6469332Sdam.sunwoo@arm.com 6479448SAndreas.Sandberg@ARM.com interrupts->serialize(os); 6489448SAndreas.Sandberg@ARM.com 6499448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 6509448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 6519448SAndreas.Sandberg@ARM.com nameOut(os, csprintf("%s.xc.%i", name(), i)); 6529448SAndreas.Sandberg@ARM.com serializeThread(os, i); 6539448SAndreas.Sandberg@ARM.com } 6549448SAndreas.Sandberg@ARM.com } 655921SN/A} 656921SN/A 657921SN/Avoid 658921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 659921SN/A{ 6604000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 6619448SAndreas.Sandberg@ARM.com 6629448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6639448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 6649448SAndreas.Sandberg@ARM.com interrupts->unserialize(cp, section); 6659448SAndreas.Sandberg@ARM.com 6669448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 6679448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) 6689448SAndreas.Sandberg@ARM.com unserializeThread(cp, csprintf("%s.xc.%i", section, i), i); 6699448SAndreas.Sandberg@ARM.com } 670921SN/A} 671921SN/A 6721191SN/Avoid 6739749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 6749749Sandreas@sandberg.pp.se{ 6759749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 6769983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 6779749Sandreas@sandberg.pp.se 6789749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 6799749Sandreas@sandberg.pp.se} 6809749Sandreas@sandberg.pp.se 68110529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 68210529Smorr@cs.wisc.edu armed = false; 68310529Smorr@cs.wisc.edu waiting = false; 68410529Smorr@cs.wisc.edu gotWakeup = false; 68510529Smorr@cs.wisc.edu} 68610529Smorr@cs.wisc.edu 68710529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 68810529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 68910529Smorr@cs.wisc.edu if(armed && waiting) { 69010529Smorr@cs.wisc.edu if(pAddr == pkt->getAddr()) { 69110529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 69210529Smorr@cs.wisc.edu pkt->getAddr()); 69310529Smorr@cs.wisc.edu waiting = false; 69410529Smorr@cs.wisc.edu return true; 69510529Smorr@cs.wisc.edu } 69610529Smorr@cs.wisc.edu } 69710529Smorr@cs.wisc.edu return false; 69810529Smorr@cs.wisc.edu} 69910529Smorr@cs.wisc.edu 7009749Sandreas@sandberg.pp.sevoid 7019749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 7029749Sandreas@sandberg.pp.se{ 7039749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 7049983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7059749Sandreas@sandberg.pp.se 7069749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 7079749Sandreas@sandberg.pp.se} 7089749Sandreas@sandberg.pp.se 7099749Sandreas@sandberg.pp.se 7109749Sandreas@sandberg.pp.sevoid 7111191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 7121191SN/A{ 7131191SN/A if (!debugSymbolTable) 7141191SN/A return; 7151191SN/A 7161191SN/A // if pc enters different function, print new function symbol and 7171191SN/A // update saved range. Otherwise do nothing. 7181191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 7191191SN/A string sym_str; 7201191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 7211191SN/A currentFunctionStart, 7221191SN/A currentFunctionEnd); 7231191SN/A 7241191SN/A if (!found) { 7251191SN/A // no symbol found: use addr as label 7261191SN/A sym_str = csprintf("0x%x", pc); 7271191SN/A currentFunctionStart = pc; 7281191SN/A currentFunctionEnd = pc + 1; 7291191SN/A } 7301191SN/A 7311191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 7327823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 7337823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 7341191SN/A } 7351191SN/A} 736