base.cc revision 10529
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * Copyright (c) 2013 Advanced Micro Devices, Inc. 17 * Copyright (c) 2013 Mark D. Hill and David A. Wood 18 * All rights reserved. 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions are 22 * met: redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer; 24 * redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution; 27 * neither the name of the copyright holders nor the names of its 28 * contributors may be used to endorse or promote products derived from 29 * this software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * Authors: Steve Reinhardt 44 * Nathan Binkert 45 * Rick Strong 46 */ 47 48#include <iostream> 49#include <sstream> 50#include <string> 51 52#include "arch/tlb.hh" 53#include "base/loader/symtab.hh" 54#include "base/cprintf.hh" 55#include "base/misc.hh" 56#include "base/output.hh" 57#include "base/trace.hh" 58#include "cpu/checker/cpu.hh" 59#include "cpu/base.hh" 60#include "cpu/cpuevent.hh" 61#include "cpu/profile.hh" 62#include "cpu/thread_context.hh" 63#include "debug/Mwait.hh" 64#include "debug/SyscallVerbose.hh" 65#include "mem/page_table.hh" 66#include "params/BaseCPU.hh" 67#include "sim/full_system.hh" 68#include "sim/process.hh" 69#include "sim/sim_events.hh" 70#include "sim/sim_exit.hh" 71#include "sim/system.hh" 72 73// Hack 74#include "sim/stat_control.hh" 75 76using namespace std; 77 78vector<BaseCPU *> BaseCPU::cpuList; 79 80// This variable reflects the max number of threads in any CPU. Be 81// careful to only use it once all the CPUs that you care about have 82// been initialized 83int maxThreadsPerCPU = 1; 84 85CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 86 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 87 cpu(_cpu), _repeatEvent(true) 88{ 89 if (_interval) 90 cpu->schedule(this, curTick() + _interval); 91} 92 93void 94CPUProgressEvent::process() 95{ 96 Counter temp = cpu->totalOps(); 97#ifndef NDEBUG 98 double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 99 100 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 101 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 102 ipc); 103 ipc = 0.0; 104#else 105 cprintf("%lli: %s progress event, total committed:%i, progress insts " 106 "committed: %lli\n", curTick(), cpu->name(), temp, 107 temp - lastNumInst); 108#endif 109 lastNumInst = temp; 110 111 if (_repeatEvent) 112 cpu->schedule(this, curTick() + _interval); 113} 114 115const char * 116CPUProgressEvent::description() const 117{ 118 return "CPU Progress"; 119} 120 121BaseCPU::BaseCPU(Params *p, bool is_checker) 122 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 123 _instMasterId(p->system->getMasterId(name() + ".inst")), 124 _dataMasterId(p->system->getMasterId(name() + ".data")), 125 _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 126 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 127 interrupts(p->interrupts), profileEvent(NULL), 128 numThreads(p->numThreads), system(p->system), 129 addressMonitor() 130{ 131 // if Python did not provide a valid ID, do it here 132 if (_cpuId == -1 ) { 133 _cpuId = cpuList.size(); 134 } 135 136 // add self to global list of CPUs 137 cpuList.push_back(this); 138 139 DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 140 _cpuId, _socketId); 141 142 if (numThreads > maxThreadsPerCPU) 143 maxThreadsPerCPU = numThreads; 144 145 // allocate per-thread instruction-based event queues 146 comInstEventQueue = new EventQueue *[numThreads]; 147 for (ThreadID tid = 0; tid < numThreads; ++tid) 148 comInstEventQueue[tid] = 149 new EventQueue("instruction-based event queue"); 150 151 // 152 // set up instruction-count-based termination events, if any 153 // 154 if (p->max_insts_any_thread != 0) { 155 const char *cause = "a thread reached the max instruction count"; 156 for (ThreadID tid = 0; tid < numThreads; ++tid) 157 scheduleInstStop(tid, p->max_insts_any_thread, cause); 158 } 159 160 // Set up instruction-count-based termination events for SimPoints 161 // Typically, there are more than one action points. 162 // Simulation.py is responsible to take the necessary actions upon 163 // exitting the simulation loop. 164 if (!p->simpoint_start_insts.empty()) { 165 const char *cause = "simpoint starting point found"; 166 for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 167 scheduleInstStop(0, p->simpoint_start_insts[i], cause); 168 } 169 170 if (p->max_insts_all_threads != 0) { 171 const char *cause = "all threads reached the max instruction count"; 172 173 // allocate & initialize shared downcounter: each event will 174 // decrement this when triggered; simulation will terminate 175 // when counter reaches 0 176 int *counter = new int; 177 *counter = numThreads; 178 for (ThreadID tid = 0; tid < numThreads; ++tid) { 179 Event *event = new CountedExitEvent(cause, *counter); 180 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 181 } 182 } 183 184 // allocate per-thread load-based event queues 185 comLoadEventQueue = new EventQueue *[numThreads]; 186 for (ThreadID tid = 0; tid < numThreads; ++tid) 187 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 188 189 // 190 // set up instruction-count-based termination events, if any 191 // 192 if (p->max_loads_any_thread != 0) { 193 const char *cause = "a thread reached the max load count"; 194 for (ThreadID tid = 0; tid < numThreads; ++tid) 195 scheduleLoadStop(tid, p->max_loads_any_thread, cause); 196 } 197 198 if (p->max_loads_all_threads != 0) { 199 const char *cause = "all threads reached the max load count"; 200 // allocate & initialize shared downcounter: each event will 201 // decrement this when triggered; simulation will terminate 202 // when counter reaches 0 203 int *counter = new int; 204 *counter = numThreads; 205 for (ThreadID tid = 0; tid < numThreads; ++tid) { 206 Event *event = new CountedExitEvent(cause, *counter); 207 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 208 } 209 } 210 211 functionTracingEnabled = false; 212 if (p->function_trace) { 213 const string fname = csprintf("ftrace.%s", name()); 214 functionTraceStream = simout.find(fname); 215 if (!functionTraceStream) 216 functionTraceStream = simout.create(fname); 217 218 currentFunctionStart = currentFunctionEnd = 0; 219 functionEntryTick = p->function_trace_start; 220 221 if (p->function_trace_start == 0) { 222 functionTracingEnabled = true; 223 } else { 224 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 225 Event *event = new wrap(this, true); 226 schedule(event, p->function_trace_start); 227 } 228 } 229 230 // The interrupts should always be present unless this CPU is 231 // switched in later or in case it is a checker CPU 232 if (!params()->switched_out && !is_checker) { 233 if (interrupts) { 234 interrupts->setCPU(this); 235 } else { 236 fatal("CPU %s has no interrupt controller.\n" 237 "Ensure createInterruptController() is called.\n", name()); 238 } 239 } 240 241 if (FullSystem) { 242 if (params()->profile) 243 profileEvent = new ProfileEvent(this, params()->profile); 244 } 245 tracer = params()->tracer; 246 247 if (params()->isa.size() != numThreads) { 248 fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 249 "of threads (%i).\n", params()->isa.size(), numThreads); 250 } 251} 252 253void 254BaseCPU::enableFunctionTrace() 255{ 256 functionTracingEnabled = true; 257} 258 259BaseCPU::~BaseCPU() 260{ 261 delete profileEvent; 262 delete[] comLoadEventQueue; 263 delete[] comInstEventQueue; 264} 265 266void 267BaseCPU::armMonitor(Addr address) 268{ 269 addressMonitor.armed = true; 270 addressMonitor.vAddr = address; 271 addressMonitor.pAddr = 0x0; 272 DPRINTF(Mwait,"Armed monitor (vAddr=0x%lx)\n", address); 273} 274 275bool 276BaseCPU::mwait(PacketPtr pkt) 277{ 278 if(addressMonitor.gotWakeup == false) { 279 int block_size = cacheLineSize(); 280 uint64_t mask = ~((uint64_t)(block_size - 1)); 281 282 assert(pkt->req->hasPaddr()); 283 addressMonitor.pAddr = pkt->getAddr() & mask; 284 addressMonitor.waiting = true; 285 286 DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 287 addressMonitor.vAddr, addressMonitor.pAddr); 288 return true; 289 } else { 290 addressMonitor.gotWakeup = false; 291 return false; 292 } 293} 294 295void 296BaseCPU::mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb) 297{ 298 Request req; 299 Addr addr = addressMonitor.vAddr; 300 int block_size = cacheLineSize(); 301 uint64_t mask = ~((uint64_t)(block_size - 1)); 302 int size = block_size; 303 304 //The address of the next line if it crosses a cache line boundary. 305 Addr secondAddr = roundDown(addr + size - 1, block_size); 306 307 if (secondAddr > addr) 308 size = secondAddr - addr; 309 310 req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 311 312 // translate to physical address 313 Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 314 assert(fault == NoFault); 315 316 addressMonitor.pAddr = req.getPaddr() & mask; 317 addressMonitor.waiting = true; 318 319 DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 320 addressMonitor.vAddr, addressMonitor.pAddr); 321} 322 323void 324BaseCPU::init() 325{ 326 if (!params()->switched_out) { 327 registerThreadContexts(); 328 329 verifyMemoryMode(); 330 } 331} 332 333void 334BaseCPU::startup() 335{ 336 if (FullSystem) { 337 if (!params()->switched_out && profileEvent) 338 schedule(profileEvent, curTick()); 339 } 340 341 if (params()->progress_interval) { 342 new CPUProgressEvent(this, params()->progress_interval); 343 } 344} 345 346ProbePoints::PMUUPtr 347BaseCPU::pmuProbePoint(const char *name) 348{ 349 ProbePoints::PMUUPtr ptr; 350 ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 351 352 return ptr; 353} 354 355void 356BaseCPU::regProbePoints() 357{ 358 ppCycles = pmuProbePoint("Cycles"); 359 360 ppRetiredInsts = pmuProbePoint("RetiredInsts"); 361 ppRetiredLoads = pmuProbePoint("RetiredLoads"); 362 ppRetiredStores = pmuProbePoint("RetiredStores"); 363 ppRetiredBranches = pmuProbePoint("RetiredBranches"); 364} 365 366void 367BaseCPU::probeInstCommit(const StaticInstPtr &inst) 368{ 369 if (!inst->isMicroop() || inst->isLastMicroop()) 370 ppRetiredInsts->notify(1); 371 372 373 if (inst->isLoad()) 374 ppRetiredLoads->notify(1); 375 376 if (inst->isStore()) 377 ppRetiredLoads->notify(1); 378 379 if (inst->isControl()) 380 ppRetiredBranches->notify(1); 381} 382 383void 384BaseCPU::regStats() 385{ 386 using namespace Stats; 387 388 numCycles 389 .name(name() + ".numCycles") 390 .desc("number of cpu cycles simulated") 391 ; 392 393 numWorkItemsStarted 394 .name(name() + ".numWorkItemsStarted") 395 .desc("number of work items this cpu started") 396 ; 397 398 numWorkItemsCompleted 399 .name(name() + ".numWorkItemsCompleted") 400 .desc("number of work items this cpu completed") 401 ; 402 403 int size = threadContexts.size(); 404 if (size > 1) { 405 for (int i = 0; i < size; ++i) { 406 stringstream namestr; 407 ccprintf(namestr, "%s.ctx%d", name(), i); 408 threadContexts[i]->regStats(namestr.str()); 409 } 410 } else if (size == 1) 411 threadContexts[0]->regStats(name()); 412} 413 414BaseMasterPort & 415BaseCPU::getMasterPort(const string &if_name, PortID idx) 416{ 417 // Get the right port based on name. This applies to all the 418 // subclasses of the base CPU and relies on their implementation 419 // of getDataPort and getInstPort. In all cases there methods 420 // return a MasterPort pointer. 421 if (if_name == "dcache_port") 422 return getDataPort(); 423 else if (if_name == "icache_port") 424 return getInstPort(); 425 else 426 return MemObject::getMasterPort(if_name, idx); 427} 428 429void 430BaseCPU::registerThreadContexts() 431{ 432 ThreadID size = threadContexts.size(); 433 for (ThreadID tid = 0; tid < size; ++tid) { 434 ThreadContext *tc = threadContexts[tid]; 435 436 /** This is so that contextId and cpuId match where there is a 437 * 1cpu:1context relationship. Otherwise, the order of registration 438 * could affect the assignment and cpu 1 could have context id 3, for 439 * example. We may even want to do something like this for SMT so that 440 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 441 * I'll just do this for now 442 */ 443 if (numThreads == 1) 444 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 445 else 446 tc->setContextId(system->registerThreadContext(tc)); 447 448 if (!FullSystem) 449 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 450 } 451} 452 453 454int 455BaseCPU::findContext(ThreadContext *tc) 456{ 457 ThreadID size = threadContexts.size(); 458 for (ThreadID tid = 0; tid < size; ++tid) { 459 if (tc == threadContexts[tid]) 460 return tid; 461 } 462 return 0; 463} 464 465void 466BaseCPU::switchOut() 467{ 468 assert(!_switchedOut); 469 _switchedOut = true; 470 if (profileEvent && profileEvent->scheduled()) 471 deschedule(profileEvent); 472 473 // Flush all TLBs in the CPU to avoid having stale translations if 474 // it gets switched in later. 475 flushTLBs(); 476} 477 478void 479BaseCPU::takeOverFrom(BaseCPU *oldCPU) 480{ 481 assert(threadContexts.size() == oldCPU->threadContexts.size()); 482 assert(_cpuId == oldCPU->cpuId()); 483 assert(_switchedOut); 484 assert(oldCPU != this); 485 _pid = oldCPU->getPid(); 486 _taskId = oldCPU->taskId(); 487 _switchedOut = false; 488 489 ThreadID size = threadContexts.size(); 490 for (ThreadID i = 0; i < size; ++i) { 491 ThreadContext *newTC = threadContexts[i]; 492 ThreadContext *oldTC = oldCPU->threadContexts[i]; 493 494 newTC->takeOverFrom(oldTC); 495 496 CpuEvent::replaceThreadContext(oldTC, newTC); 497 498 assert(newTC->contextId() == oldTC->contextId()); 499 assert(newTC->threadId() == oldTC->threadId()); 500 system->replaceThreadContext(newTC, newTC->contextId()); 501 502 /* This code no longer works since the zero register (e.g., 503 * r31 on Alpha) doesn't necessarily contain zero at this 504 * point. 505 if (DTRACE(Context)) 506 ThreadContext::compare(oldTC, newTC); 507 */ 508 509 BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 510 BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 511 BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 512 BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 513 514 // Move over any table walker ports if they exist 515 if (new_itb_port) { 516 assert(!new_itb_port->isConnected()); 517 assert(old_itb_port); 518 assert(old_itb_port->isConnected()); 519 BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 520 old_itb_port->unbind(); 521 new_itb_port->bind(slavePort); 522 } 523 if (new_dtb_port) { 524 assert(!new_dtb_port->isConnected()); 525 assert(old_dtb_port); 526 assert(old_dtb_port->isConnected()); 527 BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 528 old_dtb_port->unbind(); 529 new_dtb_port->bind(slavePort); 530 } 531 newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 532 newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 533 534 // Checker whether or not we have to transfer CheckerCPU 535 // objects over in the switch 536 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 537 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 538 if (oldChecker && newChecker) { 539 BaseMasterPort *old_checker_itb_port = 540 oldChecker->getITBPtr()->getMasterPort(); 541 BaseMasterPort *old_checker_dtb_port = 542 oldChecker->getDTBPtr()->getMasterPort(); 543 BaseMasterPort *new_checker_itb_port = 544 newChecker->getITBPtr()->getMasterPort(); 545 BaseMasterPort *new_checker_dtb_port = 546 newChecker->getDTBPtr()->getMasterPort(); 547 548 newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 549 newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 550 551 // Move over any table walker ports if they exist for checker 552 if (new_checker_itb_port) { 553 assert(!new_checker_itb_port->isConnected()); 554 assert(old_checker_itb_port); 555 assert(old_checker_itb_port->isConnected()); 556 BaseSlavePort &slavePort = 557 old_checker_itb_port->getSlavePort(); 558 old_checker_itb_port->unbind(); 559 new_checker_itb_port->bind(slavePort); 560 } 561 if (new_checker_dtb_port) { 562 assert(!new_checker_dtb_port->isConnected()); 563 assert(old_checker_dtb_port); 564 assert(old_checker_dtb_port->isConnected()); 565 BaseSlavePort &slavePort = 566 old_checker_dtb_port->getSlavePort(); 567 old_checker_dtb_port->unbind(); 568 new_checker_dtb_port->bind(slavePort); 569 } 570 } 571 } 572 573 interrupts = oldCPU->interrupts; 574 interrupts->setCPU(this); 575 oldCPU->interrupts = NULL; 576 577 if (FullSystem) { 578 for (ThreadID i = 0; i < size; ++i) 579 threadContexts[i]->profileClear(); 580 581 if (profileEvent) 582 schedule(profileEvent, curTick()); 583 } 584 585 // All CPUs have an instruction and a data port, and the new CPU's 586 // ports are dangling while the old CPU has its ports connected 587 // already. Unbind the old CPU and then bind the ports of the one 588 // we are switching to. 589 assert(!getInstPort().isConnected()); 590 assert(oldCPU->getInstPort().isConnected()); 591 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 592 oldCPU->getInstPort().unbind(); 593 getInstPort().bind(inst_peer_port); 594 595 assert(!getDataPort().isConnected()); 596 assert(oldCPU->getDataPort().isConnected()); 597 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 598 oldCPU->getDataPort().unbind(); 599 getDataPort().bind(data_peer_port); 600} 601 602void 603BaseCPU::flushTLBs() 604{ 605 for (ThreadID i = 0; i < threadContexts.size(); ++i) { 606 ThreadContext &tc(*threadContexts[i]); 607 CheckerCPU *checker(tc.getCheckerCpuPtr()); 608 609 tc.getITBPtr()->flushAll(); 610 tc.getDTBPtr()->flushAll(); 611 if (checker) { 612 checker->getITBPtr()->flushAll(); 613 checker->getDTBPtr()->flushAll(); 614 } 615 } 616} 617 618 619BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 620 : cpu(_cpu), interval(_interval) 621{ } 622 623void 624BaseCPU::ProfileEvent::process() 625{ 626 ThreadID size = cpu->threadContexts.size(); 627 for (ThreadID i = 0; i < size; ++i) { 628 ThreadContext *tc = cpu->threadContexts[i]; 629 tc->profileSample(); 630 } 631 632 cpu->schedule(this, curTick() + interval); 633} 634 635void 636BaseCPU::serialize(std::ostream &os) 637{ 638 SERIALIZE_SCALAR(instCnt); 639 640 if (!_switchedOut) { 641 /* Unlike _pid, _taskId is not serialized, as they are dynamically 642 * assigned unique ids that are only meaningful for the duration of 643 * a specific run. We will need to serialize the entire taskMap in 644 * system. */ 645 SERIALIZE_SCALAR(_pid); 646 647 interrupts->serialize(os); 648 649 // Serialize the threads, this is done by the CPU implementation. 650 for (ThreadID i = 0; i < numThreads; ++i) { 651 nameOut(os, csprintf("%s.xc.%i", name(), i)); 652 serializeThread(os, i); 653 } 654 } 655} 656 657void 658BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 659{ 660 UNSERIALIZE_SCALAR(instCnt); 661 662 if (!_switchedOut) { 663 UNSERIALIZE_SCALAR(_pid); 664 interrupts->unserialize(cp, section); 665 666 // Unserialize the threads, this is done by the CPU implementation. 667 for (ThreadID i = 0; i < numThreads; ++i) 668 unserializeThread(cp, csprintf("%s.xc.%i", section, i), i); 669 } 670} 671 672void 673BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 674{ 675 const Tick now(comInstEventQueue[tid]->getCurTick()); 676 Event *event(new LocalSimLoopExitEvent(cause, 0)); 677 678 comInstEventQueue[tid]->schedule(event, now + insts); 679} 680 681AddressMonitor::AddressMonitor() { 682 armed = false; 683 waiting = false; 684 gotWakeup = false; 685} 686 687bool AddressMonitor::doMonitor(PacketPtr pkt) { 688 assert(pkt->req->hasPaddr()); 689 if(armed && waiting) { 690 if(pAddr == pkt->getAddr()) { 691 DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 692 pkt->getAddr()); 693 waiting = false; 694 return true; 695 } 696 } 697 return false; 698} 699 700void 701BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 702{ 703 const Tick now(comLoadEventQueue[tid]->getCurTick()); 704 Event *event(new LocalSimLoopExitEvent(cause, 0)); 705 706 comLoadEventQueue[tid]->schedule(event, now + loads); 707} 708 709 710void 711BaseCPU::traceFunctionsInternal(Addr pc) 712{ 713 if (!debugSymbolTable) 714 return; 715 716 // if pc enters different function, print new function symbol and 717 // update saved range. Otherwise do nothing. 718 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 719 string sym_str; 720 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 721 currentFunctionStart, 722 currentFunctionEnd); 723 724 if (!found) { 725 // no symbol found: use addr as label 726 sym_str = csprintf("0x%x", pc); 727 currentFunctionStart = pc; 728 currentFunctionEnd = pc + 1; 729 } 730 731 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 732 curTick() - functionEntryTick, curTick(), sym_str); 733 functionEntryTick = curTick(); 734 } 735} 736