utility.cc revision 5289
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 35086Sgblack@eecs.umich.edu * All rights reserved. 45086Sgblack@eecs.umich.edu * 55086Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65086Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75086Sgblack@eecs.umich.edu * following conditions are met: 85086Sgblack@eecs.umich.edu * 95086Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105086Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115086Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 125086Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 135086Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 145086Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 155086Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 165086Sgblack@eecs.umich.edu * commercial advantage. 175086Sgblack@eecs.umich.edu * 185086Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 195086Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 205086Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 215086Sgblack@eecs.umich.edu * Office of Strategy and Technology 225086Sgblack@eecs.umich.edu * Hewlett-Packard Company 235086Sgblack@eecs.umich.edu * 1501 Page Mill Road 245086Sgblack@eecs.umich.edu * Palo Alto, California 94304 255086Sgblack@eecs.umich.edu * 265086Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 275086Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 285086Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 295086Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 305086Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 315086Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 325086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 335086Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 345086Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 355086Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 365086Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 375086Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385086Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395086Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405086Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415086Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425086Sgblack@eecs.umich.edu * 435086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545086Sgblack@eecs.umich.edu * 555086Sgblack@eecs.umich.edu * Authors: Gabe Black 565086Sgblack@eecs.umich.edu */ 575086Sgblack@eecs.umich.edu 585135Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh" 595135Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh" 605135Sgblack@eecs.umich.edu#include "arch/x86/segmentregs.hh" 615086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh" 625135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 635234Sgblack@eecs.umich.edu#include "sim/system.hh" 645086Sgblack@eecs.umich.edu 655086Sgblack@eecs.umich.edunamespace X86ISA { 665086Sgblack@eecs.umich.edu 675086Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) { 685086Sgblack@eecs.umich.edu#if FULL_SYSTEM 695086Sgblack@eecs.umich.edu panic("getArgument() not implemented for x86!\n"); 705086Sgblack@eecs.umich.edu#else 715086Sgblack@eecs.umich.edu panic("getArgument() only implemented for FULL_SYSTEM\n"); 725086Sgblack@eecs.umich.edu M5_DUMMY_RETURN 735086Sgblack@eecs.umich.edu#endif 745086Sgblack@eecs.umich.edu} 755135Sgblack@eecs.umich.edu 765135Sgblack@eecs.umich.edu# if FULL_SYSTEM 775135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId) 785135Sgblack@eecs.umich.edu{ 795135Sgblack@eecs.umich.edu // The otherwise unmodified integer registers should be set to 0. 805135Sgblack@eecs.umich.edu for (int index = 0; index < NUM_INTREGS; index++) { 815135Sgblack@eecs.umich.edu tc->setIntReg(index, 0); 825135Sgblack@eecs.umich.edu } 835135Sgblack@eecs.umich.edu 845135Sgblack@eecs.umich.edu // These next two loops zero internal microcode and implicit registers. 855135Sgblack@eecs.umich.edu // They aren't specified by the ISA but are used internally by M5's 865135Sgblack@eecs.umich.edu // implementation. 875135Sgblack@eecs.umich.edu for (int index = 0; index < NumMicroIntRegs; index++) { 885135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(index), 0); 895135Sgblack@eecs.umich.edu } 905135Sgblack@eecs.umich.edu 915135Sgblack@eecs.umich.edu for (int index = 0; index < NumImplicitIntRegs; index++) { 925135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_IMPLICIT(index), 0); 935135Sgblack@eecs.umich.edu } 945135Sgblack@eecs.umich.edu 955135Sgblack@eecs.umich.edu // Set integer register EAX to 0 to indicate that the optional BIST 965135Sgblack@eecs.umich.edu // passed. No BIST actually runs, but software may still check this 975135Sgblack@eecs.umich.edu // register for errors. 985135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RAX, 0); 995135Sgblack@eecs.umich.edu 1005135Sgblack@eecs.umich.edu //The following values are dictated by the architecture for after a RESET# 1015264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 1025135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR2, 0); 1035135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR3, 0); 1045135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR4, 0); 1055135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR8, 0); 1065135Sgblack@eecs.umich.edu 1075264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL); 1085135Sgblack@eecs.umich.edu 1095135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, 0); 1105135Sgblack@eecs.umich.edu 1115141Sgblack@eecs.umich.edu SegAttr dataAttr = 0; 1125141Sgblack@eecs.umich.edu dataAttr.writable = 1; 1135141Sgblack@eecs.umich.edu dataAttr.readable = 1; 1145141Sgblack@eecs.umich.edu dataAttr.expandDown = 0; 1155141Sgblack@eecs.umich.edu dataAttr.dpl = 0; 1165141Sgblack@eecs.umich.edu dataAttr.defaultSize = 0; 1175141Sgblack@eecs.umich.edu 1185135Sgblack@eecs.umich.edu for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { 1195135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 1205135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); 1215289Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0); 1225135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); 1235141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr); 1245135Sgblack@eecs.umich.edu } 1255135Sgblack@eecs.umich.edu 1265141Sgblack@eecs.umich.edu SegAttr codeAttr = 0; 1275141Sgblack@eecs.umich.edu codeAttr.writable = 0; 1285141Sgblack@eecs.umich.edu codeAttr.readable = 1; 1295141Sgblack@eecs.umich.edu codeAttr.expandDown = 0; 1305141Sgblack@eecs.umich.edu codeAttr.dpl = 0; 1315141Sgblack@eecs.umich.edu codeAttr.defaultSize = 0; 1325141Sgblack@eecs.umich.edu 1335135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS, 0xf000); 1345289Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_BASE, 1355289Sgblack@eecs.umich.edu 0x00000000ffff0000ULL); 1365289Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_EFF_BASE, 1375289Sgblack@eecs.umich.edu 0x00000000ffff0000ULL); 1385135Sgblack@eecs.umich.edu // This has the base value pre-added. 1395135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); 1405141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_ATTR, codeAttr); 1415135Sgblack@eecs.umich.edu 1425264Sgblack@eecs.umich.edu tc->setPC(0x000000000000fff0ULL + 1435135Sgblack@eecs.umich.edu tc->readMiscReg(MISCREG_CS_BASE)); 1445135Sgblack@eecs.umich.edu tc->setNextPC(tc->readPC() + sizeof(MachInst)); 1455135Sgblack@eecs.umich.edu 1465135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_BASE, 0); 1475135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff); 1485135Sgblack@eecs.umich.edu 1495135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IDTR_BASE, 0); 1505135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 1515135Sgblack@eecs.umich.edu 1525135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR, 0); 1535135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_BASE, 0); 1545135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff); 1555135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_ATTR, 0); 1565135Sgblack@eecs.umich.edu 1575135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR, 0); 1585135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_BASE, 0); 1595135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); 1605135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_ATTR, 0); 1615135Sgblack@eecs.umich.edu 1625135Sgblack@eecs.umich.edu // This value should be the family/model/stepping of the processor. 1635135Sgblack@eecs.umich.edu // (page 418). It should be consistent with the value from CPUID, but the 1645135Sgblack@eecs.umich.edu // actual value probably doesn't matter much. 1655135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RDX, 0); 1665135Sgblack@eecs.umich.edu 1675135Sgblack@eecs.umich.edu // TODO initialize x87, 64 bit, and 128 bit media state 1685135Sgblack@eecs.umich.edu 1695141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 1705141Sgblack@eecs.umich.edu for (int i = 0; i < 8; i++) { 1715141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 1725141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 1735141Sgblack@eecs.umich.edu } 1745141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 1755141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 1765141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 1775141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 1785182Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 1795141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 1805141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 1815141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 1825141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 1835141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 1845141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 1855135Sgblack@eecs.umich.edu 1865141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEF_TYPE, 0); 1875141Sgblack@eecs.umich.edu 1885141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 1895141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_STATUS, 0); 1905141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CTL, 0); 1915141Sgblack@eecs.umich.edu 1925141Sgblack@eecs.umich.edu for (int i = 0; i < 5; i++) { 1935141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_CTL(i), 0); 1945141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 1955141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 1965141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_MISC(i), 0); 1975141Sgblack@eecs.umich.edu } 1985135Sgblack@eecs.umich.edu 1995135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR0, 0); 2005135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR1, 0); 2015135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR2, 0); 2025135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR3, 0); 2035135Sgblack@eecs.umich.edu 2045264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL); 2055264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL); 2065135Sgblack@eecs.umich.edu 2075141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC, 0); 2085141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC_AUX, 0); 2095135Sgblack@eecs.umich.edu 2105141Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 2115141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 2125141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 2135141Sgblack@eecs.umich.edu } 2145135Sgblack@eecs.umich.edu 2155141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STAR, 0); 2165141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LSTAR, 0); 2175141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CSTAR, 0); 2185141Sgblack@eecs.umich.edu 2195141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SF_MASK, 0); 2205141Sgblack@eecs.umich.edu 2215141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 2225141Sgblack@eecs.umich.edu 2235141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 2245141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 2255141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 2265141Sgblack@eecs.umich.edu 2275264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 2285141Sgblack@eecs.umich.edu 2295141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 2305141Sgblack@eecs.umich.edu 2315141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE0, 0); 2325141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE1, 0); 2335141Sgblack@eecs.umich.edu 2345141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK0, 0); 2355141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK1, 0); 2365141Sgblack@eecs.umich.edu 2375141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 2385141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 2395141Sgblack@eecs.umich.edu 2405141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 2415141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 2425141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 2435141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 2445141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 2455135Sgblack@eecs.umich.edu 2465135Sgblack@eecs.umich.edu // Invalidate the caches (this should already be done for us) 2475135Sgblack@eecs.umich.edu 2485135Sgblack@eecs.umich.edu // TODO Turn on the APIC. This should be handled elsewhere but it isn't 2495135Sgblack@eecs.umich.edu // currently being handled at all. 2505135Sgblack@eecs.umich.edu 2515141Sgblack@eecs.umich.edu // TODO Set the SMRAM base address (SMBASE) to 0x00030000 2525141Sgblack@eecs.umich.edu 2535141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_CR, 0); 2545141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IGNNE, 0); 2555141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SMM_CTL, 0); 2565141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 2575135Sgblack@eecs.umich.edu} 2585135Sgblack@eecs.umich.edu 2595135Sgblack@eecs.umich.edu#endif 2605135Sgblack@eecs.umich.edu 2615234Sgblack@eecs.umich.edu#if FULL_SYSTEM 2625135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId) 2635135Sgblack@eecs.umich.edu{ 2645135Sgblack@eecs.umich.edu if (cpuId == 0) { 2655135Sgblack@eecs.umich.edu // This is the boot strap processor (BSP). Initialize it to look like 2665234Sgblack@eecs.umich.edu // the boot loader has just turned control over to the 64 bit OS. We 2675234Sgblack@eecs.umich.edu // won't actually set up real mode or legacy protected mode descriptor 2685234Sgblack@eecs.umich.edu // tables because we aren't executing any code that would require 2695234Sgblack@eecs.umich.edu // them. We do, however toggle the control bits in the correct order 2705234Sgblack@eecs.umich.edu // while allowing consistency checks and the underlying mechansims 2715234Sgblack@eecs.umich.edu // just to be safe. 2725135Sgblack@eecs.umich.edu 2735234Sgblack@eecs.umich.edu const int NumPDTs = 4; 2745234Sgblack@eecs.umich.edu 2755234Sgblack@eecs.umich.edu const Addr PageMapLevel4 = 0x70000; 2765234Sgblack@eecs.umich.edu const Addr PageDirPtrTable = 0x71000; 2775234Sgblack@eecs.umich.edu const Addr PageDirTable[NumPDTs] = 2785234Sgblack@eecs.umich.edu {0x72000, 0x73000, 0x74000, 0x75000}; 2795234Sgblack@eecs.umich.edu const Addr GDTBase = 0x76000; 2805234Sgblack@eecs.umich.edu 2815234Sgblack@eecs.umich.edu const int PML4Bits = 9; 2825234Sgblack@eecs.umich.edu const int PDPTBits = 9; 2835234Sgblack@eecs.umich.edu const int PDTBits = 9; 2845234Sgblack@eecs.umich.edu 2855234Sgblack@eecs.umich.edu // Get a port to write the page tables and descriptor tables. 2865234Sgblack@eecs.umich.edu FunctionalPort * physPort = tc->getPhysPort(); 2875234Sgblack@eecs.umich.edu 2885234Sgblack@eecs.umich.edu /* 2895234Sgblack@eecs.umich.edu * Set up the gdt. 2905234Sgblack@eecs.umich.edu */ 2915234Sgblack@eecs.umich.edu // Place holder at selector 0 2925234Sgblack@eecs.umich.edu uint64_t nullDescriptor = 0; 2935234Sgblack@eecs.umich.edu physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8); 2945234Sgblack@eecs.umich.edu 2955234Sgblack@eecs.umich.edu //64 bit code segment 2965234Sgblack@eecs.umich.edu SegDescriptor csDesc = 0; 2975234Sgblack@eecs.umich.edu csDesc.type.c = 0; // Not conforming 2985234Sgblack@eecs.umich.edu csDesc.dpl = 0; // Privelege level 0 2995234Sgblack@eecs.umich.edu csDesc.p = 1; // Present 3005234Sgblack@eecs.umich.edu csDesc.l = 1; // 64 bit 3015234Sgblack@eecs.umich.edu csDesc.d = 0; // default operand size 3025234Sgblack@eecs.umich.edu //Because we're dealing with a pointer and I don't think it's 3035234Sgblack@eecs.umich.edu //guaranteed that there isn't anything in a nonvirtual class between 3045234Sgblack@eecs.umich.edu //it's beginning in memory and it's actual data, we'll use an 3055234Sgblack@eecs.umich.edu //intermediary. 3065234Sgblack@eecs.umich.edu uint64_t csDescVal = csDesc; 3075234Sgblack@eecs.umich.edu physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8); 3085234Sgblack@eecs.umich.edu 3095234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_BASE, GDTBase); 3105234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xF); 3115234Sgblack@eecs.umich.edu 3125234Sgblack@eecs.umich.edu /* 3135234Sgblack@eecs.umich.edu * Identity map the first 4GB of memory. In order to map this region 3145234Sgblack@eecs.umich.edu * of memory in long mode, there needs to be one actual page map level 3155234Sgblack@eecs.umich.edu * 4 entry which points to one page directory pointer table which 3165234Sgblack@eecs.umich.edu * points to 4 different page directory tables which are full of two 3175234Sgblack@eecs.umich.edu * megabyte pages. All of the other entries in valid tables are set 3185234Sgblack@eecs.umich.edu * to indicate that they don't pertain to anything valid and will 3195234Sgblack@eecs.umich.edu * cause a fault if used. 3205234Sgblack@eecs.umich.edu */ 3215234Sgblack@eecs.umich.edu 3225234Sgblack@eecs.umich.edu // Put valid values in all of the various table entries which indicate 3235234Sgblack@eecs.umich.edu // that those entries don't point to further tables or pages. Then 3245234Sgblack@eecs.umich.edu // set the values of those entries which are needed. 3255234Sgblack@eecs.umich.edu 3265234Sgblack@eecs.umich.edu // Page Map Level 4 3275234Sgblack@eecs.umich.edu 3285234Sgblack@eecs.umich.edu // read/write, user, not present 3295234Sgblack@eecs.umich.edu uint64_t pml4e = X86ISA::htog(0x6); 3305234Sgblack@eecs.umich.edu for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 3315234Sgblack@eecs.umich.edu physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 3325234Sgblack@eecs.umich.edu } 3335234Sgblack@eecs.umich.edu // Point to the only PDPT 3345234Sgblack@eecs.umich.edu pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 3355234Sgblack@eecs.umich.edu physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 3365234Sgblack@eecs.umich.edu 3375234Sgblack@eecs.umich.edu // Page Directory Pointer Table 3385234Sgblack@eecs.umich.edu 3395234Sgblack@eecs.umich.edu // read/write, user, not present 3405234Sgblack@eecs.umich.edu uint64_t pdpe = X86ISA::htog(0x6); 3415234Sgblack@eecs.umich.edu for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 3425234Sgblack@eecs.umich.edu physPort->writeBlob(PageDirPtrTable + offset, 3435234Sgblack@eecs.umich.edu (uint8_t *)(&pdpe), 8); 3445234Sgblack@eecs.umich.edu } 3455234Sgblack@eecs.umich.edu // Point to the PDTs 3465234Sgblack@eecs.umich.edu for (int table = 0; table < NumPDTs; table++) { 3475234Sgblack@eecs.umich.edu pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 3485234Sgblack@eecs.umich.edu physPort->writeBlob(PageDirPtrTable + table * 8, 3495234Sgblack@eecs.umich.edu (uint8_t *)(&pdpe), 8); 3505234Sgblack@eecs.umich.edu } 3515234Sgblack@eecs.umich.edu 3525234Sgblack@eecs.umich.edu // Page Directory Tables 3535234Sgblack@eecs.umich.edu 3545234Sgblack@eecs.umich.edu Addr base = 0; 3555234Sgblack@eecs.umich.edu const Addr pageSize = 2 << 20; 3565234Sgblack@eecs.umich.edu for (int table = 0; table < NumPDTs; table++) { 3575234Sgblack@eecs.umich.edu for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 3585234Sgblack@eecs.umich.edu // read/write, user, present, 4MB 3595234Sgblack@eecs.umich.edu uint64_t pdte = X86ISA::htog(0x87 | base); 3605234Sgblack@eecs.umich.edu physPort->writeBlob(PageDirTable[table] + offset, 3615234Sgblack@eecs.umich.edu (uint8_t *)(&pdte), 8); 3625234Sgblack@eecs.umich.edu base += pageSize; 3635234Sgblack@eecs.umich.edu } 3645234Sgblack@eecs.umich.edu } 3655234Sgblack@eecs.umich.edu 3665234Sgblack@eecs.umich.edu /* 3675234Sgblack@eecs.umich.edu * Transition from real mode all the way up to Long mode 3685234Sgblack@eecs.umich.edu */ 3695234Sgblack@eecs.umich.edu CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 3705234Sgblack@eecs.umich.edu //Turn off paging. 3715234Sgblack@eecs.umich.edu cr0.pg = 0; 3725234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 3735234Sgblack@eecs.umich.edu //Turn on protected mode. 3745234Sgblack@eecs.umich.edu cr0.pe = 1; 3755234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 3765234Sgblack@eecs.umich.edu 3775234Sgblack@eecs.umich.edu CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 3785234Sgblack@eecs.umich.edu //Turn on pae. 3795234Sgblack@eecs.umich.edu cr4.pae = 1; 3805234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR4, cr4); 3815234Sgblack@eecs.umich.edu 3825234Sgblack@eecs.umich.edu //Point to the page tables. 3835234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 3845234Sgblack@eecs.umich.edu 3855234Sgblack@eecs.umich.edu Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 3865234Sgblack@eecs.umich.edu //Enable long mode. 3875234Sgblack@eecs.umich.edu efer.lme = 1; 3885234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, efer); 3895234Sgblack@eecs.umich.edu 3905234Sgblack@eecs.umich.edu //Activate long mode. 3915234Sgblack@eecs.umich.edu cr0.pg = 1; 3925234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 3935234Sgblack@eecs.umich.edu 3945234Sgblack@eecs.umich.edu /* 3955234Sgblack@eecs.umich.edu * Far jump into 64 bit mode. 3965234Sgblack@eecs.umich.edu */ 3975234Sgblack@eecs.umich.edu // Set the selector 3985234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS, 1); 3995234Sgblack@eecs.umich.edu // Manually set up the segment attributes. In the future when there's 4005234Sgblack@eecs.umich.edu // other existing functionality to do this, that could be used 4015234Sgblack@eecs.umich.edu // instead. 4025234Sgblack@eecs.umich.edu SegAttr csAttr = 0; 4035234Sgblack@eecs.umich.edu csAttr.writable = 0; 4045234Sgblack@eecs.umich.edu csAttr.readable = 1; 4055234Sgblack@eecs.umich.edu csAttr.expandDown = 0; 4065234Sgblack@eecs.umich.edu csAttr.dpl = 0; 4075234Sgblack@eecs.umich.edu csAttr.defaultSize = 0; 4085234Sgblack@eecs.umich.edu csAttr.longMode = 1; 4095234Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_ATTR, csAttr); 4105234Sgblack@eecs.umich.edu 4115234Sgblack@eecs.umich.edu tc->setPC(tc->getSystemPtr()->kernelEntry); 4125234Sgblack@eecs.umich.edu tc->setNextPC(tc->readPC()); 4135234Sgblack@eecs.umich.edu 4145234Sgblack@eecs.umich.edu // We should now be in long mode. Yay! 4155135Sgblack@eecs.umich.edu 4165135Sgblack@eecs.umich.edu tc->activate(0); 4175135Sgblack@eecs.umich.edu } else { 4185135Sgblack@eecs.umich.edu // This is an application processor (AP). It should be initialized to 4195135Sgblack@eecs.umich.edu // look like only the BIOS POST has run on it and put then put it into 4205135Sgblack@eecs.umich.edu // a halted state. 4215234Sgblack@eecs.umich.edu tc->suspend(); 4225135Sgblack@eecs.umich.edu } 4235135Sgblack@eecs.umich.edu} 4245135Sgblack@eecs.umich.edu 4255234Sgblack@eecs.umich.edu#else 4265234Sgblack@eecs.umich.edu 4275234Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId) 4285234Sgblack@eecs.umich.edu{ 4295234Sgblack@eecs.umich.edu tc->activate(0); 4305234Sgblack@eecs.umich.edu} 4315234Sgblack@eecs.umich.edu 4325234Sgblack@eecs.umich.edu#endif 4335234Sgblack@eecs.umich.edu 4345086Sgblack@eecs.umich.edu} //namespace X86_ISA 435