utility.cc revision 5289
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#include "arch/x86/intregs.hh" 59#include "arch/x86/miscregs.hh" 60#include "arch/x86/segmentregs.hh" 61#include "arch/x86/utility.hh" 62#include "arch/x86/x86_traits.hh" 63#include "sim/system.hh" 64 65namespace X86ISA { 66 67uint64_t getArgument(ThreadContext *tc, int number, bool fp) { 68#if FULL_SYSTEM 69 panic("getArgument() not implemented for x86!\n"); 70#else 71 panic("getArgument() only implemented for FULL_SYSTEM\n"); 72 M5_DUMMY_RETURN 73#endif 74} 75 76# if FULL_SYSTEM 77void initCPU(ThreadContext *tc, int cpuId) 78{ 79 // The otherwise unmodified integer registers should be set to 0. 80 for (int index = 0; index < NUM_INTREGS; index++) { 81 tc->setIntReg(index, 0); 82 } 83 84 // These next two loops zero internal microcode and implicit registers. 85 // They aren't specified by the ISA but are used internally by M5's 86 // implementation. 87 for (int index = 0; index < NumMicroIntRegs; index++) { 88 tc->setIntReg(INTREG_MICRO(index), 0); 89 } 90 91 for (int index = 0; index < NumImplicitIntRegs; index++) { 92 tc->setIntReg(INTREG_IMPLICIT(index), 0); 93 } 94 95 // Set integer register EAX to 0 to indicate that the optional BIST 96 // passed. No BIST actually runs, but software may still check this 97 // register for errors. 98 tc->setIntReg(INTREG_RAX, 0); 99 100 //The following values are dictated by the architecture for after a RESET# 101 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 102 tc->setMiscReg(MISCREG_CR2, 0); 103 tc->setMiscReg(MISCREG_CR3, 0); 104 tc->setMiscReg(MISCREG_CR4, 0); 105 tc->setMiscReg(MISCREG_CR8, 0); 106 107 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL); 108 109 tc->setMiscReg(MISCREG_EFER, 0); 110 111 SegAttr dataAttr = 0; 112 dataAttr.writable = 1; 113 dataAttr.readable = 1; 114 dataAttr.expandDown = 0; 115 dataAttr.dpl = 0; 116 dataAttr.defaultSize = 0; 117 118 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { 119 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 120 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); 121 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0); 122 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); 123 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr); 124 } 125 126 SegAttr codeAttr = 0; 127 codeAttr.writable = 0; 128 codeAttr.readable = 1; 129 codeAttr.expandDown = 0; 130 codeAttr.dpl = 0; 131 codeAttr.defaultSize = 0; 132 133 tc->setMiscReg(MISCREG_CS, 0xf000); 134 tc->setMiscReg(MISCREG_CS_BASE, 135 0x00000000ffff0000ULL); 136 tc->setMiscReg(MISCREG_CS_EFF_BASE, 137 0x00000000ffff0000ULL); 138 // This has the base value pre-added. 139 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); 140 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr); 141 142 tc->setPC(0x000000000000fff0ULL + 143 tc->readMiscReg(MISCREG_CS_BASE)); 144 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 145 146 tc->setMiscReg(MISCREG_GDTR_BASE, 0); 147 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff); 148 149 tc->setMiscReg(MISCREG_IDTR_BASE, 0); 150 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 151 152 tc->setMiscReg(MISCREG_LDTR, 0); 153 tc->setMiscReg(MISCREG_LDTR_BASE, 0); 154 tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff); 155 tc->setMiscReg(MISCREG_LDTR_ATTR, 0); 156 157 tc->setMiscReg(MISCREG_TR, 0); 158 tc->setMiscReg(MISCREG_TR_BASE, 0); 159 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); 160 tc->setMiscReg(MISCREG_TR_ATTR, 0); 161 162 // This value should be the family/model/stepping of the processor. 163 // (page 418). It should be consistent with the value from CPUID, but the 164 // actual value probably doesn't matter much. 165 tc->setIntReg(INTREG_RDX, 0); 166 167 // TODO initialize x87, 64 bit, and 128 bit media state 168 169 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 170 for (int i = 0; i < 8; i++) { 171 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 172 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 173 } 174 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 175 tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 176 tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 177 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 178 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 179 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 180 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 181 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 182 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 183 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 184 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 185 186 tc->setMiscReg(MISCREG_DEF_TYPE, 0); 187 188 tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 189 tc->setMiscReg(MISCREG_MCG_STATUS, 0); 190 tc->setMiscReg(MISCREG_MCG_CTL, 0); 191 192 for (int i = 0; i < 5; i++) { 193 tc->setMiscReg(MISCREG_MC_CTL(i), 0); 194 tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 195 tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 196 tc->setMiscReg(MISCREG_MC_MISC(i), 0); 197 } 198 199 tc->setMiscReg(MISCREG_DR0, 0); 200 tc->setMiscReg(MISCREG_DR1, 0); 201 tc->setMiscReg(MISCREG_DR2, 0); 202 tc->setMiscReg(MISCREG_DR3, 0); 203 204 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL); 205 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL); 206 207 tc->setMiscReg(MISCREG_TSC, 0); 208 tc->setMiscReg(MISCREG_TSC_AUX, 0); 209 210 for (int i = 0; i < 4; i++) { 211 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 212 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 213 } 214 215 tc->setMiscReg(MISCREG_STAR, 0); 216 tc->setMiscReg(MISCREG_LSTAR, 0); 217 tc->setMiscReg(MISCREG_CSTAR, 0); 218 219 tc->setMiscReg(MISCREG_SF_MASK, 0); 220 221 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 222 223 tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 224 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 225 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 226 227 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 228 229 tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 230 231 tc->setMiscReg(MISCREG_IORR_BASE0, 0); 232 tc->setMiscReg(MISCREG_IORR_BASE1, 0); 233 234 tc->setMiscReg(MISCREG_IORR_MASK0, 0); 235 tc->setMiscReg(MISCREG_IORR_MASK1, 0); 236 237 tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 238 tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 239 240 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 241 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 242 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 243 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 244 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 245 246 // Invalidate the caches (this should already be done for us) 247 248 // TODO Turn on the APIC. This should be handled elsewhere but it isn't 249 // currently being handled at all. 250 251 // TODO Set the SMRAM base address (SMBASE) to 0x00030000 252 253 tc->setMiscReg(MISCREG_VM_CR, 0); 254 tc->setMiscReg(MISCREG_IGNNE, 0); 255 tc->setMiscReg(MISCREG_SMM_CTL, 0); 256 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 257} 258 259#endif 260 261#if FULL_SYSTEM 262void startupCPU(ThreadContext *tc, int cpuId) 263{ 264 if (cpuId == 0) { 265 // This is the boot strap processor (BSP). Initialize it to look like 266 // the boot loader has just turned control over to the 64 bit OS. We 267 // won't actually set up real mode or legacy protected mode descriptor 268 // tables because we aren't executing any code that would require 269 // them. We do, however toggle the control bits in the correct order 270 // while allowing consistency checks and the underlying mechansims 271 // just to be safe. 272 273 const int NumPDTs = 4; 274 275 const Addr PageMapLevel4 = 0x70000; 276 const Addr PageDirPtrTable = 0x71000; 277 const Addr PageDirTable[NumPDTs] = 278 {0x72000, 0x73000, 0x74000, 0x75000}; 279 const Addr GDTBase = 0x76000; 280 281 const int PML4Bits = 9; 282 const int PDPTBits = 9; 283 const int PDTBits = 9; 284 285 // Get a port to write the page tables and descriptor tables. 286 FunctionalPort * physPort = tc->getPhysPort(); 287 288 /* 289 * Set up the gdt. 290 */ 291 // Place holder at selector 0 292 uint64_t nullDescriptor = 0; 293 physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8); 294 295 //64 bit code segment 296 SegDescriptor csDesc = 0; 297 csDesc.type.c = 0; // Not conforming 298 csDesc.dpl = 0; // Privelege level 0 299 csDesc.p = 1; // Present 300 csDesc.l = 1; // 64 bit 301 csDesc.d = 0; // default operand size 302 //Because we're dealing with a pointer and I don't think it's 303 //guaranteed that there isn't anything in a nonvirtual class between 304 //it's beginning in memory and it's actual data, we'll use an 305 //intermediary. 306 uint64_t csDescVal = csDesc; 307 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8); 308 309 tc->setMiscReg(MISCREG_GDTR_BASE, GDTBase); 310 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xF); 311 312 /* 313 * Identity map the first 4GB of memory. In order to map this region 314 * of memory in long mode, there needs to be one actual page map level 315 * 4 entry which points to one page directory pointer table which 316 * points to 4 different page directory tables which are full of two 317 * megabyte pages. All of the other entries in valid tables are set 318 * to indicate that they don't pertain to anything valid and will 319 * cause a fault if used. 320 */ 321 322 // Put valid values in all of the various table entries which indicate 323 // that those entries don't point to further tables or pages. Then 324 // set the values of those entries which are needed. 325 326 // Page Map Level 4 327 328 // read/write, user, not present 329 uint64_t pml4e = X86ISA::htog(0x6); 330 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 331 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 332 } 333 // Point to the only PDPT 334 pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 335 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 336 337 // Page Directory Pointer Table 338 339 // read/write, user, not present 340 uint64_t pdpe = X86ISA::htog(0x6); 341 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 342 physPort->writeBlob(PageDirPtrTable + offset, 343 (uint8_t *)(&pdpe), 8); 344 } 345 // Point to the PDTs 346 for (int table = 0; table < NumPDTs; table++) { 347 pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 348 physPort->writeBlob(PageDirPtrTable + table * 8, 349 (uint8_t *)(&pdpe), 8); 350 } 351 352 // Page Directory Tables 353 354 Addr base = 0; 355 const Addr pageSize = 2 << 20; 356 for (int table = 0; table < NumPDTs; table++) { 357 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 358 // read/write, user, present, 4MB 359 uint64_t pdte = X86ISA::htog(0x87 | base); 360 physPort->writeBlob(PageDirTable[table] + offset, 361 (uint8_t *)(&pdte), 8); 362 base += pageSize; 363 } 364 } 365 366 /* 367 * Transition from real mode all the way up to Long mode 368 */ 369 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 370 //Turn off paging. 371 cr0.pg = 0; 372 tc->setMiscReg(MISCREG_CR0, cr0); 373 //Turn on protected mode. 374 cr0.pe = 1; 375 tc->setMiscReg(MISCREG_CR0, cr0); 376 377 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 378 //Turn on pae. 379 cr4.pae = 1; 380 tc->setMiscReg(MISCREG_CR4, cr4); 381 382 //Point to the page tables. 383 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 384 385 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 386 //Enable long mode. 387 efer.lme = 1; 388 tc->setMiscReg(MISCREG_EFER, efer); 389 390 //Activate long mode. 391 cr0.pg = 1; 392 tc->setMiscReg(MISCREG_CR0, cr0); 393 394 /* 395 * Far jump into 64 bit mode. 396 */ 397 // Set the selector 398 tc->setMiscReg(MISCREG_CS, 1); 399 // Manually set up the segment attributes. In the future when there's 400 // other existing functionality to do this, that could be used 401 // instead. 402 SegAttr csAttr = 0; 403 csAttr.writable = 0; 404 csAttr.readable = 1; 405 csAttr.expandDown = 0; 406 csAttr.dpl = 0; 407 csAttr.defaultSize = 0; 408 csAttr.longMode = 1; 409 tc->setMiscReg(MISCREG_CS_ATTR, csAttr); 410 411 tc->setPC(tc->getSystemPtr()->kernelEntry); 412 tc->setNextPC(tc->readPC()); 413 414 // We should now be in long mode. Yay! 415 416 tc->activate(0); 417 } else { 418 // This is an application processor (AP). It should be initialized to 419 // look like only the BIOS POST has run on it and put then put it into 420 // a halted state. 421 tc->suspend(); 422 } 423} 424 425#else 426 427void startupCPU(ThreadContext *tc, int cpuId) 428{ 429 tc->activate(0); 430} 431 432#endif 433 434} //namespace X86_ISA 435