misc.hh revision 5426
1955SN/A/* 2955SN/A * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * Redistribution and use of this software in source and binary forms, 6955SN/A * with or without modification, are permitted provided that the 7955SN/A * following conditions are met: 8955SN/A * 9955SN/A * The software must be used only for Non-Commercial Use which means any 10955SN/A * use which is NOT directed to receiving any direct monetary 11955SN/A * compensation for, or commercial advantage from such use. Illustrative 12955SN/A * examples of non-commercial use are academic research, personal study, 13955SN/A * teaching, education and corporate research & development. 14955SN/A * Illustrative examples of commercial use are distributing products for 15955SN/A * commercial advantage and providing services using the software for 16955SN/A * commercial advantage. 17955SN/A * 18955SN/A * If you wish to use this software or functionality therein that may be 19955SN/A * covered by patents for commercial use, please contact: 20955SN/A * Director of Intellectual Property Licensing 21955SN/A * Office of Strategy and Technology 22955SN/A * Hewlett-Packard Company 23955SN/A * 1501 Page Mill Road 24955SN/A * Palo Alto, California 94304 25955SN/A * 26955SN/A * Redistributions of source code must retain the above copyright notice, 27955SN/A * this list of conditions and the following disclaimer. Redistributions 282665Ssaidi@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 292665Ssaidi@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 30955SN/A * other materials provided with the distribution. Neither the name of 31955SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32955SN/A * contributors may be used to endorse or promote products derived from 33955SN/A * this software without specific prior written permission. No right of 34955SN/A * sublicense is granted herewith. Derivatives of the software and 352632Sstever@eecs.umich.edu * output created using the software may be prepared, but only for 362632Sstever@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 372632Sstever@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 382632Sstever@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 39955SN/A * and (ii) such Derivatives of the software include the above copyright 402632Sstever@eecs.umich.edu * notice to acknowledge the contribution from this software where 412632Sstever@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 422761Sstever@eecs.umich.edu * 432632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 442632Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 452632Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 462761Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 472761Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 482761Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 492632Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 502632Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 512761Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 522761Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 532761Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 542761Sstever@eecs.umich.edu * 552761Sstever@eecs.umich.edu * Authors: Gabe Black 562632Sstever@eecs.umich.edu */ 572632Sstever@eecs.umich.edu 582632Sstever@eecs.umich.edu#ifndef __ARCH_X86_MISCREGS_HH__ 592632Sstever@eecs.umich.edu#define __ARCH_X86_MISCREGS_HH__ 602632Sstever@eecs.umich.edu 612632Sstever@eecs.umich.edu#include "arch/x86/segmentregs.hh" 622632Sstever@eecs.umich.edu#include "arch/x86/x86_traits.hh" 63955SN/A#include "base/bitunion.hh" 64955SN/A 65955SN/A//These get defined in some system headers (at least termbits.h). That confuses 66955SN/A//things here significantly. 67955SN/A#undef CR0 684202Sbinkertn@umich.edu#undef CR2 695342Sstever@gmail.com#undef CR3 70955SN/A 715273Sstever@gmail.comnamespace X86ISA 725273Sstever@gmail.com{ 732656Sstever@eecs.umich.edu enum CondFlagBit { 742656Sstever@eecs.umich.edu CFBit = 1 << 0, 752656Sstever@eecs.umich.edu PFBit = 1 << 2, 762656Sstever@eecs.umich.edu ECFBit = 1 << 3, 772656Sstever@eecs.umich.edu AFBit = 1 << 4, 782656Sstever@eecs.umich.edu EZFBit = 1 << 5, 792656Sstever@eecs.umich.edu ZFBit = 1 << 6, 802653Sstever@eecs.umich.edu SFBit = 1 << 7, 815227Ssaidi@eecs.umich.edu DFBit = 1 << 10, 825227Ssaidi@eecs.umich.edu OFBit = 1 << 11 835227Ssaidi@eecs.umich.edu }; 845227Ssaidi@eecs.umich.edu 852653Sstever@eecs.umich.edu enum RFLAGBit { 862653Sstever@eecs.umich.edu TFBit = 1 << 8, 872653Sstever@eecs.umich.edu IFBit = 1 << 9, 882653Sstever@eecs.umich.edu NTBit = 1 << 14, 892653Sstever@eecs.umich.edu RFBit = 1 << 16, 902653Sstever@eecs.umich.edu VMBit = 1 << 17, 912653Sstever@eecs.umich.edu ACBit = 1 << 18, 922653Sstever@eecs.umich.edu VIFBit = 1 << 19, 932653Sstever@eecs.umich.edu VIPBit = 1 << 20, 944781Snate@binkert.org IDBit = 1 << 21 951852SN/A }; 96955SN/A 97955SN/A enum MiscRegIndex 98955SN/A { 993717Sstever@eecs.umich.edu // Control registers 1003716Sstever@eecs.umich.edu // Most of these are invalid. 101955SN/A MISCREG_CR_BASE, 1021533SN/A MISCREG_CR0 = MISCREG_CR_BASE, 1033716Sstever@eecs.umich.edu MISCREG_CR1, 1041533SN/A MISCREG_CR2, 1054678Snate@binkert.org MISCREG_CR3, 1064678Snate@binkert.org MISCREG_CR4, 1074678Snate@binkert.org MISCREG_CR5, 1084678Snate@binkert.org MISCREG_CR6, 1094678Snate@binkert.org MISCREG_CR7, 1104678Snate@binkert.org MISCREG_CR8, 1114678Snate@binkert.org MISCREG_CR9, 1124678Snate@binkert.org MISCREG_CR10, 1134678Snate@binkert.org MISCREG_CR11, 1144678Snate@binkert.org MISCREG_CR12, 1154678Snate@binkert.org MISCREG_CR13, 1164678Snate@binkert.org MISCREG_CR14, 1174678Snate@binkert.org MISCREG_CR15, 1184678Snate@binkert.org 1194678Snate@binkert.org // Debug registers 1204678Snate@binkert.org MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 1214678Snate@binkert.org MISCREG_DR0 = MISCREG_DR_BASE, 1224678Snate@binkert.org MISCREG_DR1, 1234678Snate@binkert.org MISCREG_DR2, 1244678Snate@binkert.org MISCREG_DR3, 1254678Snate@binkert.org MISCREG_DR4, 1264973Ssaidi@eecs.umich.edu MISCREG_DR5, 1274678Snate@binkert.org MISCREG_DR6, 1284678Snate@binkert.org MISCREG_DR7, 1294678Snate@binkert.org 1304678Snate@binkert.org // Flags register 1314678Snate@binkert.org MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 1324678Snate@binkert.org 133955SN/A /* 134955SN/A * Model Specific Registers 1352632Sstever@eecs.umich.edu */ 1362632Sstever@eecs.umich.edu // Time stamp counter 137955SN/A MISCREG_TSC, 138955SN/A 139955SN/A MISCREG_MTRRCAP, 140955SN/A 1412632Sstever@eecs.umich.edu MISCREG_SYSENTER_CS, 142955SN/A MISCREG_SYSENTER_ESP, 1432632Sstever@eecs.umich.edu MISCREG_SYSENTER_EIP, 1442632Sstever@eecs.umich.edu 1452632Sstever@eecs.umich.edu MISCREG_MCG_CAP, 1462632Sstever@eecs.umich.edu MISCREG_MCG_STATUS, 1472632Sstever@eecs.umich.edu MISCREG_MCG_CTL, 1482632Sstever@eecs.umich.edu 1492632Sstever@eecs.umich.edu MISCREG_DEBUG_CTL_MSR, 1503053Sstever@eecs.umich.edu 1513053Sstever@eecs.umich.edu MISCREG_LAST_BRANCH_FROM_IP, 1523053Sstever@eecs.umich.edu MISCREG_LAST_BRANCH_TO_IP, 1533053Sstever@eecs.umich.edu MISCREG_LAST_EXCEPTION_FROM_IP, 1543053Sstever@eecs.umich.edu MISCREG_LAST_EXCEPTION_TO_IP, 1553053Sstever@eecs.umich.edu 1563053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_BASE, 1573053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 1583053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_1, 1593053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_2, 1603053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_3, 1613053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_4, 1623053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_5, 1633053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_6, 1643053Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_7, 1653053Sstever@eecs.umich.edu 1662632Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_BASE, 1672632Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 1682632Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_1, 1692632Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_2, 1702632Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_3, 1712632Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_4, 1723718Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_5, 1733718Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_6, 1743718Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_7, 1753718Sstever@eecs.umich.edu 1763718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_64K_00000, 1773718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_16K_80000, 1783718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_16K_A0000, 1793718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_C0000, 1803718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_C8000, 1813718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_D0000, 1823718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_D8000, 1833718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_E0000, 1843718Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_E8000, 1852634Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_F0000, 1862634Sstever@eecs.umich.edu MISCREG_MTRR_FIX_4K_F8000, 1872632Sstever@eecs.umich.edu 1882638Sstever@eecs.umich.edu MISCREG_PAT, 1892632Sstever@eecs.umich.edu 1902632Sstever@eecs.umich.edu MISCREG_DEF_TYPE, 1912632Sstever@eecs.umich.edu 1922632Sstever@eecs.umich.edu MISCREG_MC_CTL_BASE, 1932632Sstever@eecs.umich.edu MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 1942632Sstever@eecs.umich.edu MISCREG_MC1_CTL, 1951858SN/A MISCREG_MC2_CTL, 1963716Sstever@eecs.umich.edu MISCREG_MC3_CTL, 1972638Sstever@eecs.umich.edu MISCREG_MC4_CTL, 1982638Sstever@eecs.umich.edu MISCREG_MC5_CTL, 1992638Sstever@eecs.umich.edu MISCREG_MC6_CTL, 2002638Sstever@eecs.umich.edu MISCREG_MC7_CTL, 2012638Sstever@eecs.umich.edu 2022638Sstever@eecs.umich.edu MISCREG_MC_STATUS_BASE, 2032638Sstever@eecs.umich.edu MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 2043716Sstever@eecs.umich.edu MISCREG_MC1_STATUS, 2052634Sstever@eecs.umich.edu MISCREG_MC2_STATUS, 2062634Sstever@eecs.umich.edu MISCREG_MC3_STATUS, 207955SN/A MISCREG_MC4_STATUS, 2085341Sstever@gmail.com MISCREG_MC5_STATUS, 2095341Sstever@gmail.com MISCREG_MC6_STATUS, 2105341Sstever@gmail.com MISCREG_MC7_STATUS, 2115341Sstever@gmail.com 212955SN/A MISCREG_MC_ADDR_BASE, 213955SN/A MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 214955SN/A MISCREG_MC1_ADDR, 215955SN/A MISCREG_MC2_ADDR, 216955SN/A MISCREG_MC3_ADDR, 217955SN/A MISCREG_MC4_ADDR, 218955SN/A MISCREG_MC5_ADDR, 2191858SN/A MISCREG_MC6_ADDR, 2201858SN/A MISCREG_MC7_ADDR, 2212632Sstever@eecs.umich.edu 222955SN/A MISCREG_MC_MISC_BASE, 2234494Ssaidi@eecs.umich.edu MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 2244494Ssaidi@eecs.umich.edu MISCREG_MC1_MISC, 2253716Sstever@eecs.umich.edu MISCREG_MC2_MISC, 2261105SN/A MISCREG_MC3_MISC, 2272667Sstever@eecs.umich.edu MISCREG_MC4_MISC, 2282667Sstever@eecs.umich.edu MISCREG_MC5_MISC, 2292667Sstever@eecs.umich.edu MISCREG_MC6_MISC, 2302667Sstever@eecs.umich.edu MISCREG_MC7_MISC, 2312667Sstever@eecs.umich.edu 2322667Sstever@eecs.umich.edu // Extended feature enable register 2331869SN/A MISCREG_EFER, 2341869SN/A 2351869SN/A MISCREG_STAR, 2361869SN/A MISCREG_LSTAR, 2371869SN/A MISCREG_CSTAR, 2381065SN/A 2395341Sstever@gmail.com MISCREG_SF_MASK, 2405341Sstever@gmail.com 2415341Sstever@gmail.com MISCREG_KERNEL_GS_BASE, 2425341Sstever@gmail.com 2435341Sstever@gmail.com MISCREG_TSC_AUX, 2445341Sstever@gmail.com 2455341Sstever@gmail.com MISCREG_PERF_EVT_SEL_BASE, 2465341Sstever@gmail.com MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 2475341Sstever@gmail.com MISCREG_PERF_EVT_SEL1, 2485341Sstever@gmail.com MISCREG_PERF_EVT_SEL2, 2495341Sstever@gmail.com MISCREG_PERF_EVT_SEL3, 2505341Sstever@gmail.com 2515341Sstever@gmail.com MISCREG_PERF_EVT_CTR_BASE, 2525341Sstever@gmail.com MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 2535341Sstever@gmail.com MISCREG_PERF_EVT_CTR1, 2545341Sstever@gmail.com MISCREG_PERF_EVT_CTR2, 2555341Sstever@gmail.com MISCREG_PERF_EVT_CTR3, 2565341Sstever@gmail.com 2575341Sstever@gmail.com MISCREG_SYSCFG, 2585341Sstever@gmail.com 2595341Sstever@gmail.com MISCREG_IORR_BASE_BASE, 2605341Sstever@gmail.com MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 2615341Sstever@gmail.com MISCREG_IORR_BASE1, 2625341Sstever@gmail.com 2635341Sstever@gmail.com MISCREG_IORR_MASK_BASE, 2645341Sstever@gmail.com MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 2655341Sstever@gmail.com MISCREG_IORR_MASK1, 2665341Sstever@gmail.com 2675341Sstever@gmail.com MISCREG_TOP_MEM, 2685341Sstever@gmail.com MISCREG_TOP_MEM2, 2695341Sstever@gmail.com 2705341Sstever@gmail.com MISCREG_VM_CR, 2715341Sstever@gmail.com MISCREG_IGNNE, 2725341Sstever@gmail.com MISCREG_SMM_CTL, 2735341Sstever@gmail.com MISCREG_VM_HSAVE_PA, 2745341Sstever@gmail.com 2755341Sstever@gmail.com /* 2765341Sstever@gmail.com * Segment registers 2775341Sstever@gmail.com */ 2785341Sstever@gmail.com // Segment selectors 2795341Sstever@gmail.com MISCREG_SEG_SEL_BASE, 2805341Sstever@gmail.com MISCREG_ES = MISCREG_SEG_SEL_BASE, 2815341Sstever@gmail.com MISCREG_CS, 2825341Sstever@gmail.com MISCREG_SS, 2835341Sstever@gmail.com MISCREG_DS, 2845341Sstever@gmail.com MISCREG_FS, 2855341Sstever@gmail.com MISCREG_GS, 2865341Sstever@gmail.com MISCREG_HS, 2875341Sstever@gmail.com MISCREG_TSL, 2885344Sstever@gmail.com MISCREG_TSG, 2895341Sstever@gmail.com MISCREG_LS, 2905341Sstever@gmail.com MISCREG_MS, 2915341Sstever@gmail.com MISCREG_TR, 2925341Sstever@gmail.com MISCREG_IDTR, 2935341Sstever@gmail.com 2942632Sstever@eecs.umich.edu // Hidden segment base field 2955199Sstever@gmail.com MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 2963918Ssaidi@eecs.umich.edu MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 2973918Ssaidi@eecs.umich.edu MISCREG_CS_BASE, 2983940Ssaidi@eecs.umich.edu MISCREG_SS_BASE, 2994781Snate@binkert.org MISCREG_DS_BASE, 3004781Snate@binkert.org MISCREG_FS_BASE, 3013918Ssaidi@eecs.umich.edu MISCREG_GS_BASE, 3024781Snate@binkert.org MISCREG_HS_BASE, 3034781Snate@binkert.org MISCREG_TSL_BASE, 3043918Ssaidi@eecs.umich.edu MISCREG_TSG_BASE, 3054781Snate@binkert.org MISCREG_LS_BASE, 3064781Snate@binkert.org MISCREG_MS_BASE, 3073940Ssaidi@eecs.umich.edu MISCREG_TR_BASE, 3083942Ssaidi@eecs.umich.edu MISCREG_IDTR_BASE, 3093940Ssaidi@eecs.umich.edu 3103918Ssaidi@eecs.umich.edu // The effective segment base, ie what is actually added to an 3113918Ssaidi@eecs.umich.edu // address. In 64 bit mode this can be different from the above, 312955SN/A // namely 0. 3131858SN/A MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 3143918Ssaidi@eecs.umich.edu MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 3153918Ssaidi@eecs.umich.edu MISCREG_CS_EFF_BASE, 3163918Ssaidi@eecs.umich.edu MISCREG_SS_EFF_BASE, 3173918Ssaidi@eecs.umich.edu MISCREG_DS_EFF_BASE, 3183940Ssaidi@eecs.umich.edu MISCREG_FS_EFF_BASE, 3193940Ssaidi@eecs.umich.edu MISCREG_GS_EFF_BASE, 3203918Ssaidi@eecs.umich.edu MISCREG_HS_EFF_BASE, 3213918Ssaidi@eecs.umich.edu MISCREG_TSL_EFF_BASE, 3223918Ssaidi@eecs.umich.edu MISCREG_TSG_EFF_BASE, 3233918Ssaidi@eecs.umich.edu MISCREG_LS_EFF_BASE, 3243918Ssaidi@eecs.umich.edu MISCREG_MS_EFF_BASE, 3253918Ssaidi@eecs.umich.edu MISCREG_TR_EFF_BASE, 3263918Ssaidi@eecs.umich.edu MISCREG_IDTR_EFF_BASE, 3273918Ssaidi@eecs.umich.edu 3283918Ssaidi@eecs.umich.edu // Hidden segment limit field 3293940Ssaidi@eecs.umich.edu MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 3303918Ssaidi@eecs.umich.edu MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 3313918Ssaidi@eecs.umich.edu MISCREG_CS_LIMIT, 3321851SN/A MISCREG_SS_LIMIT, 3331851SN/A MISCREG_DS_LIMIT, 3341858SN/A MISCREG_FS_LIMIT, 3355200Sstever@gmail.com MISCREG_GS_LIMIT, 336955SN/A MISCREG_HS_LIMIT, 3373053Sstever@eecs.umich.edu MISCREG_TSL_LIMIT, 3383053Sstever@eecs.umich.edu MISCREG_TSG_LIMIT, 3393053Sstever@eecs.umich.edu MISCREG_LS_LIMIT, 3403053Sstever@eecs.umich.edu MISCREG_MS_LIMIT, 3413053Sstever@eecs.umich.edu MISCREG_TR_LIMIT, 3423053Sstever@eecs.umich.edu MISCREG_IDTR_LIMIT, 3433053Sstever@eecs.umich.edu 3443053Sstever@eecs.umich.edu // Hidden segment limit attributes 3453053Sstever@eecs.umich.edu MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 3464742Sstever@eecs.umich.edu MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 3474742Sstever@eecs.umich.edu MISCREG_CS_ATTR, 3483053Sstever@eecs.umich.edu MISCREG_SS_ATTR, 3493053Sstever@eecs.umich.edu MISCREG_DS_ATTR, 3503053Sstever@eecs.umich.edu MISCREG_FS_ATTR, 3513053Sstever@eecs.umich.edu MISCREG_GS_ATTR, 3523053Sstever@eecs.umich.edu MISCREG_HS_ATTR, 3533053Sstever@eecs.umich.edu MISCREG_TSL_ATTR, 3543053Sstever@eecs.umich.edu MISCREG_TSG_ATTR, 3553053Sstever@eecs.umich.edu MISCREG_LS_ATTR, 3563053Sstever@eecs.umich.edu MISCREG_MS_ATTR, 3572667Sstever@eecs.umich.edu MISCREG_TR_ATTR, 3584554Sbinkertn@umich.edu MISCREG_IDTR_ATTR, 3594554Sbinkertn@umich.edu 3602667Sstever@eecs.umich.edu // Floating point control registers 3614554Sbinkertn@umich.edu MISCREG_X87_TOP = 3624554Sbinkertn@umich.edu MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 3634554Sbinkertn@umich.edu 3644554Sbinkertn@umich.edu //XXX Add "Model-Specific Registers" 3654554Sbinkertn@umich.edu 3664554Sbinkertn@umich.edu MISCREG_APIC_BASE, 3674554Sbinkertn@umich.edu 3684781Snate@binkert.org MISCREG_APIC_START, 3694554Sbinkertn@umich.edu MISCREG_APIC_ID = MISCREG_APIC_START, 3704554Sbinkertn@umich.edu MISCREG_APIC_VERSION, 3712667Sstever@eecs.umich.edu MISCREG_APIC_TASK_PRIORITY, 3724554Sbinkertn@umich.edu MISCREG_APIC_ARBITRATION_PRIORITY, 3734554Sbinkertn@umich.edu MISCREG_APIC_PROCESSOR_PRIORITY, 3744554Sbinkertn@umich.edu MISCREG_APIC_EOI, 3754554Sbinkertn@umich.edu MISCREG_APIC_LOGICAL_DESTINATION, 3762667Sstever@eecs.umich.edu MISCREG_APIC_DESTINATION_FORMAT, 3774554Sbinkertn@umich.edu MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR, 3782667Sstever@eecs.umich.edu 3794554Sbinkertn@umich.edu MISCREG_APIC_IN_SERVICE_BASE, 3804554Sbinkertn@umich.edu 3812667Sstever@eecs.umich.edu MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16, 3822638Sstever@eecs.umich.edu 3832638Sstever@eecs.umich.edu MISCREG_APIC_INTERRUPT_REQUEST_BASE = 3842638Sstever@eecs.umich.edu MISCREG_APIC_TRIGGER_MODE_BASE + 16, 3853716Sstever@eecs.umich.edu 3863716Sstever@eecs.umich.edu MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16, 3871858SN/A MISCREG_APIC_INTERRUPT_COMMAND_LOW, 3885227Ssaidi@eecs.umich.edu MISCREG_APIC_INTERRUPT_COMMAND_HIGH, 3895227Ssaidi@eecs.umich.edu MISCREG_APIC_LVT_TIMER, 3905227Ssaidi@eecs.umich.edu MISCREG_APIC_LVT_THERMAL_SENSOR, 3915227Ssaidi@eecs.umich.edu MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, 3925227Ssaidi@eecs.umich.edu MISCREG_APIC_LVT_LINT0, 3935227Ssaidi@eecs.umich.edu MISCREG_APIC_LVT_LINT1, 3945227Ssaidi@eecs.umich.edu MISCREG_APIC_LVT_ERROR, 3955227Ssaidi@eecs.umich.edu MISCREG_APIC_INITIAL_COUNT, 3965227Ssaidi@eecs.umich.edu MISCREG_APIC_CURRENT_COUNT, 3975227Ssaidi@eecs.umich.edu MISCREG_APIC_DIVIDE_COUNT, 3985227Ssaidi@eecs.umich.edu MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT, 3995227Ssaidi@eecs.umich.edu 4005274Ssaidi@eecs.umich.edu MISCREG_APIC_INTERNAL_STATE, 4015227Ssaidi@eecs.umich.edu 4025227Ssaidi@eecs.umich.edu // "Fake" MSRs for internally implemented devices 4035227Ssaidi@eecs.umich.edu MISCREG_PCI_CONFIG_ADDRESS, 4045204Sstever@gmail.com 4055204Sstever@gmail.com NUM_MISCREGS 4065204Sstever@gmail.com }; 4075204Sstever@gmail.com 4085204Sstever@gmail.com static inline MiscRegIndex 4095204Sstever@gmail.com MISCREG_CR(int index) 4105204Sstever@gmail.com { 4115204Sstever@gmail.com return (MiscRegIndex)(MISCREG_CR_BASE + index); 4125204Sstever@gmail.com } 4135204Sstever@gmail.com 4145204Sstever@gmail.com static inline MiscRegIndex 4155204Sstever@gmail.com MISCREG_DR(int index) 4165204Sstever@gmail.com { 4175204Sstever@gmail.com return (MiscRegIndex)(MISCREG_DR_BASE + index); 4185204Sstever@gmail.com } 4195204Sstever@gmail.com 4205204Sstever@gmail.com static inline MiscRegIndex 4215204Sstever@gmail.com MISCREG_MTRR_PHYS_BASE(int index) 4225204Sstever@gmail.com { 4233118Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 4243118Sstever@eecs.umich.edu } 4253118Sstever@eecs.umich.edu 4263118Sstever@eecs.umich.edu static inline MiscRegIndex 4273118Sstever@eecs.umich.edu MISCREG_MTRR_PHYS_MASK(int index) 4283118Sstever@eecs.umich.edu { 4293118Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 4303118Sstever@eecs.umich.edu } 4313118Sstever@eecs.umich.edu 4323118Sstever@eecs.umich.edu static inline MiscRegIndex 4333118Sstever@eecs.umich.edu MISCREG_MC_CTL(int index) 4343716Sstever@eecs.umich.edu { 4353118Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 4363118Sstever@eecs.umich.edu } 4373118Sstever@eecs.umich.edu 4383118Sstever@eecs.umich.edu static inline MiscRegIndex 4393118Sstever@eecs.umich.edu MISCREG_MC_STATUS(int index) 4403118Sstever@eecs.umich.edu { 4413118Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 4423118Sstever@eecs.umich.edu } 4433118Sstever@eecs.umich.edu 4443716Sstever@eecs.umich.edu static inline MiscRegIndex 4453118Sstever@eecs.umich.edu MISCREG_MC_ADDR(int index) 4463118Sstever@eecs.umich.edu { 4473118Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 4483118Sstever@eecs.umich.edu } 4493118Sstever@eecs.umich.edu 4503118Sstever@eecs.umich.edu static inline MiscRegIndex 4513118Sstever@eecs.umich.edu MISCREG_MC_MISC(int index) 4523118Sstever@eecs.umich.edu { 4533118Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 4543118Sstever@eecs.umich.edu } 4553483Ssaidi@eecs.umich.edu 4563494Ssaidi@eecs.umich.edu static inline MiscRegIndex 4573494Ssaidi@eecs.umich.edu MISCREG_PERF_EVT_SEL(int index) 4583483Ssaidi@eecs.umich.edu { 4593483Ssaidi@eecs.umich.edu return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 4603483Ssaidi@eecs.umich.edu } 4613053Sstever@eecs.umich.edu 4623053Sstever@eecs.umich.edu static inline MiscRegIndex 4633918Ssaidi@eecs.umich.edu MISCREG_PERF_EVT_CTR(int index) 4643053Sstever@eecs.umich.edu { 4653053Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 4663053Sstever@eecs.umich.edu } 4673053Sstever@eecs.umich.edu 4683053Sstever@eecs.umich.edu static inline MiscRegIndex 4691858SN/A MISCREG_IORR_BASE(int index) 4701858SN/A { 4711858SN/A return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 4721858SN/A } 4731858SN/A 4741858SN/A static inline MiscRegIndex 4751859SN/A MISCREG_IORR_MASK(int index) 4761858SN/A { 4771858SN/A return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 4781858SN/A } 4791859SN/A 4801859SN/A static inline MiscRegIndex 4811862SN/A MISCREG_SEG_SEL(int index) 4823053Sstever@eecs.umich.edu { 4833053Sstever@eecs.umich.edu return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 4843053Sstever@eecs.umich.edu } 4853053Sstever@eecs.umich.edu 4861859SN/A static inline MiscRegIndex 4871859SN/A MISCREG_SEG_BASE(int index) 4881859SN/A { 4891859SN/A return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 4901859SN/A } 4911859SN/A 4921859SN/A static inline MiscRegIndex 4931859SN/A MISCREG_SEG_EFF_BASE(int index) 4941862SN/A { 4951859SN/A return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 4961859SN/A } 4971859SN/A 4981858SN/A static inline MiscRegIndex 4991858SN/A MISCREG_SEG_LIMIT(int index) 5002139SN/A { 5014202Sbinkertn@umich.edu return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 5024202Sbinkertn@umich.edu } 5032139SN/A 5042155SN/A static inline MiscRegIndex 5054202Sbinkertn@umich.edu MISCREG_SEG_ATTR(int index) 5064202Sbinkertn@umich.edu { 5074202Sbinkertn@umich.edu return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 5082155SN/A } 5091869SN/A 5101869SN/A static inline MiscRegIndex 5111869SN/A MISCREG_APIC_IN_SERVICE(int index) 5121869SN/A { 5134202Sbinkertn@umich.edu return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index); 5144202Sbinkertn@umich.edu } 5154202Sbinkertn@umich.edu 5164202Sbinkertn@umich.edu static inline MiscRegIndex 5174202Sbinkertn@umich.edu MISCREG_APIC_TRIGGER_MODE(int index) 5184202Sbinkertn@umich.edu { 5194202Sbinkertn@umich.edu return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index); 5204202Sbinkertn@umich.edu } 5215341Sstever@gmail.com 5225341Sstever@gmail.com static inline MiscRegIndex 5235341Sstever@gmail.com MISCREG_APIC_INTERRUPT_REQUEST(int index) 5245342Sstever@gmail.com { 5255342Sstever@gmail.com return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index); 5264202Sbinkertn@umich.edu } 5274202Sbinkertn@umich.edu 5284202Sbinkertn@umich.edu /** 5294202Sbinkertn@umich.edu * A type to describe the condition code bits of the RFLAGS register, 5304202Sbinkertn@umich.edu * plus two flags, EZF and ECF, which are only visible to microcode. 5311869SN/A */ 5324202Sbinkertn@umich.edu BitUnion64(CCFlagBits) 5331869SN/A Bitfield<11> of; 5342508SN/A Bitfield<7> sf; 5352508SN/A Bitfield<6> zf; 5362508SN/A Bitfield<5> ezf; 5372508SN/A Bitfield<4> af; 5384202Sbinkertn@umich.edu Bitfield<3> ecf; 5391869SN/A Bitfield<2> pf; 5405385Sstever@gmail.com Bitfield<0> cf; 5415385Sstever@gmail.com EndBitUnion(CCFlagBits) 5425385Sstever@gmail.com 5435385Sstever@gmail.com /** 5441869SN/A * RFLAGS 5451869SN/A */ 5461869SN/A BitUnion64(RFLAGS) 5471869SN/A Bitfield<21> id; // ID Flag 5481869SN/A Bitfield<20> vip; // Virtual Interrupt Pending 5491965SN/A Bitfield<19> vif; // Virtual Interrupt Flag 5501965SN/A Bitfield<18> ac; // Alignment Check 5511965SN/A Bitfield<17> vm; // Virtual-8086 Mode 5521869SN/A Bitfield<16> rf; // Resume Flag 5531869SN/A Bitfield<14> nt; // Nested Task 5542733Sktlim@umich.edu Bitfield<13, 12> iopl; // I/O Privilege Level 5551884SN/A Bitfield<11> of; // Overflow Flag 5563356Sbinkertn@umich.edu Bitfield<10> df; // Direction Flag 5573356Sbinkertn@umich.edu Bitfield<9> intf; // Interrupt Flag 5583356Sbinkertn@umich.edu Bitfield<8> tf; // Trap Flag 5594773Snate@binkert.org Bitfield<7> sf; // Sign Flag 5601869SN/A Bitfield<6> zf; // Zero Flag 5611858SN/A Bitfield<4> af; // Auxiliary Flag 5621869SN/A Bitfield<2> pf; // Parity Flag 5631869SN/A Bitfield<0> cf; // Carry Flag 5641869SN/A EndBitUnion(RFLAGS) 5651858SN/A 5662761Sstever@eecs.umich.edu /** 5671869SN/A * Control registers 5685385Sstever@gmail.com */ 5695385Sstever@gmail.com BitUnion64(CR0) 5703584Ssaidi@eecs.umich.edu Bitfield<31> pg; // Paging 5711869SN/A Bitfield<30> cd; // Cache Disable 5721869SN/A Bitfield<29> nw; // Not Writethrough 5731869SN/A Bitfield<18> am; // Alignment Mask 5741869SN/A Bitfield<16> wp; // Write Protect 5751869SN/A Bitfield<5> ne; // Numeric Error 5761869SN/A Bitfield<4> et; // Extension Type 5771858SN/A Bitfield<3> ts; // Task Switched 578955SN/A Bitfield<2> em; // Emulation 579955SN/A Bitfield<1> mp; // Monitor Coprocessor 5801869SN/A Bitfield<0> pe; // Protection Enabled 5811869SN/A EndBitUnion(CR0) 5821869SN/A 5831869SN/A // Page Fault Virtual Address 5841869SN/A BitUnion64(CR2) 5851869SN/A Bitfield<31, 0> legacy; 5861869SN/A EndBitUnion(CR2) 5871869SN/A 5881869SN/A BitUnion64(CR3) 5891869SN/A Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 5901869SN/A // Base Address 5911869SN/A Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 5921869SN/A // Base Address 5931869SN/A Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 5941869SN/A // Base Address 5951869SN/A Bitfield<4> pcd; // Page-Level Cache Disable 5961869SN/A Bitfield<3> pwt; // Page-Level Writethrough 5971869SN/A EndBitUnion(CR3) 5981869SN/A 5991869SN/A BitUnion64(CR4) 6001869SN/A Bitfield<10> osxmmexcpt; // Operating System Unmasked 6011869SN/A // Exception Support 6021869SN/A Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 6031869SN/A Bitfield<8> pce; // Performance-Monitoring Counter Enable 6041869SN/A Bitfield<7> pge; // Page-Global Enable 6051869SN/A Bitfield<6> mce; // Machine Check Enable 6061869SN/A Bitfield<5> pae; // Physical-Address Extension 6071869SN/A Bitfield<4> pse; // Page Size Extensions 6081869SN/A Bitfield<3> de; // Debugging Extensions 6093716Sstever@eecs.umich.edu Bitfield<2> tsd; // Time Stamp Disable 6103356Sbinkertn@umich.edu Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 6113356Sbinkertn@umich.edu Bitfield<0> vme; // Virtual-8086 Mode Extensions 6123356Sbinkertn@umich.edu EndBitUnion(CR4) 6133356Sbinkertn@umich.edu 6143356Sbinkertn@umich.edu BitUnion64(CR8) 6153356Sbinkertn@umich.edu Bitfield<3, 0> tpr; // Task Priority Register 6164781Snate@binkert.org EndBitUnion(CR8) 6171869SN/A 6181869SN/A // MTRR capabilities 6191869SN/A BitUnion64(MTRRcap) 6201869SN/A Bitfield<7, 0> vcnt; // Variable-Range Register Count 6211869SN/A Bitfield<8> fix; // Fixed-Range Registers 6221869SN/A Bitfield<10> wc; // Write-Combining 6231869SN/A EndBitUnion(MTRRcap) 6242655Sstever@eecs.umich.edu 6252655Sstever@eecs.umich.edu /** 6262655Sstever@eecs.umich.edu * SYSENTER configuration registers 6272655Sstever@eecs.umich.edu */ 6282655Sstever@eecs.umich.edu BitUnion64(SysenterCS) 6292655Sstever@eecs.umich.edu Bitfield<15, 0> targetCS; 6302655Sstever@eecs.umich.edu EndBitUnion(SysenterCS) 6312655Sstever@eecs.umich.edu 6322655Sstever@eecs.umich.edu BitUnion64(SysenterESP) 6332655Sstever@eecs.umich.edu Bitfield<31, 0> targetESP; 6342655Sstever@eecs.umich.edu EndBitUnion(SysenterESP) 6352655Sstever@eecs.umich.edu 6362655Sstever@eecs.umich.edu BitUnion64(SysenterEIP) 6372655Sstever@eecs.umich.edu Bitfield<31, 0> targetEIP; 6382655Sstever@eecs.umich.edu EndBitUnion(SysenterEIP) 6392655Sstever@eecs.umich.edu 6402655Sstever@eecs.umich.edu /** 6412655Sstever@eecs.umich.edu * Global machine check registers 6422655Sstever@eecs.umich.edu */ 6432655Sstever@eecs.umich.edu BitUnion64(McgCap) 6442655Sstever@eecs.umich.edu Bitfield<7, 0> count; // Number of error reporting register banks 6452655Sstever@eecs.umich.edu Bitfield<8> MCGCP; // MCG_CTL register present. 6462655Sstever@eecs.umich.edu EndBitUnion(McgCap) 6472655Sstever@eecs.umich.edu 6482655Sstever@eecs.umich.edu BitUnion64(McgStatus) 6492655Sstever@eecs.umich.edu Bitfield<0> ripv; // Restart-IP valid 6502638Sstever@eecs.umich.edu Bitfield<1> eipv; // Error-IP valid 6512638Sstever@eecs.umich.edu Bitfield<2> mcip; // Machine check in-progress 6523716Sstever@eecs.umich.edu EndBitUnion(McgStatus) 6532638Sstever@eecs.umich.edu 6542638Sstever@eecs.umich.edu BitUnion64(DebugCtlMsr) 6551869SN/A Bitfield<0> lbr; // Last-branch record 6561869SN/A Bitfield<1> btf; // Branch single step 6573546Sgblack@eecs.umich.edu Bitfield<2> pb0; // Performance monitoring pin control 0 6583546Sgblack@eecs.umich.edu Bitfield<3> pb1; // Performance monitoring pin control 1 6593546Sgblack@eecs.umich.edu Bitfield<4> pb2; // Performance monitoring pin control 2 6603546Sgblack@eecs.umich.edu Bitfield<5> pb3; // Performance monitoring pin control 3 6614202Sbinkertn@umich.edu /*uint64_t pb(int index) 6623546Sgblack@eecs.umich.edu { 6633546Sgblack@eecs.umich.edu return bits(__data, index + 2); 6643546Sgblack@eecs.umich.edu }*/ 6653546Sgblack@eecs.umich.edu EndBitUnion(DebugCtlMsr) 6663546Sgblack@eecs.umich.edu 6674781Snate@binkert.org BitUnion64(MtrrPhysBase) 6684781Snate@binkert.org Bitfield<7, 0> type; // Default memory type 6694781Snate@binkert.org Bitfield<51, 12> physbase; // Range physical base address 6704781Snate@binkert.org EndBitUnion(MtrrPhysBase) 6714781Snate@binkert.org 6724781Snate@binkert.org BitUnion64(MtrrPhysMask) 6734781Snate@binkert.org Bitfield<11> valid; // MTRR pair enable 6744781Snate@binkert.org Bitfield<51, 12> physmask; // Range physical mask 6754781Snate@binkert.org EndBitUnion(MtrrPhysMask) 6764781Snate@binkert.org 6774781Snate@binkert.org BitUnion64(MtrrFixed) 6784781Snate@binkert.org /*uint64_t type(int index) 6793546Sgblack@eecs.umich.edu { 6803546Sgblack@eecs.umich.edu return bits(__data, index * 8 + 7, index * 8); 6813546Sgblack@eecs.umich.edu }*/ 6824781Snate@binkert.org EndBitUnion(MtrrFixed) 6833546Sgblack@eecs.umich.edu 6843546Sgblack@eecs.umich.edu BitUnion64(Pat) 6853546Sgblack@eecs.umich.edu /*uint64_t pa(int index) 6863546Sgblack@eecs.umich.edu { 6873546Sgblack@eecs.umich.edu return bits(__data, index * 8 + 2, index * 8); 6883546Sgblack@eecs.umich.edu }*/ 6893546Sgblack@eecs.umich.edu EndBitUnion(Pat) 6903546Sgblack@eecs.umich.edu 6913546Sgblack@eecs.umich.edu BitUnion64(MtrrDefType) 6923546Sgblack@eecs.umich.edu Bitfield<7, 0> type; // Default type 6934202Sbinkertn@umich.edu Bitfield<10> fe; // Fixed range enable 6943546Sgblack@eecs.umich.edu Bitfield<11> e; // MTRR enable 6953546Sgblack@eecs.umich.edu EndBitUnion(MtrrDefType) 6963546Sgblack@eecs.umich.edu 697955SN/A /** 698955SN/A * Machine check 699955SN/A */ 700955SN/A BitUnion64(McStatus) 7011858SN/A Bitfield<15,0> mcaErrorCode; 7021858SN/A Bitfield<31,16> modelSpecificCode; 7031858SN/A Bitfield<56,32> otherInfo; 7042632Sstever@eecs.umich.edu Bitfield<57> pcc; // Processor-context corrupt 7052632Sstever@eecs.umich.edu Bitfield<58> addrv; // Error-address register valid 7065343Sstever@gmail.com Bitfield<59> miscv; // Miscellaneous-error register valid 7075343Sstever@gmail.com Bitfield<60> en; // Error condition enabled 7085343Sstever@gmail.com Bitfield<61> uc; // Uncorrected error 7094773Snate@binkert.org Bitfield<62> over; // Status register overflow 7104773Snate@binkert.org Bitfield<63> val; // Valid 7112632Sstever@eecs.umich.edu EndBitUnion(McStatus) 7122632Sstever@eecs.umich.edu 7132632Sstever@eecs.umich.edu BitUnion64(McCtl) 7142023SN/A /*uint64_t en(int index) 7152632Sstever@eecs.umich.edu { 7162632Sstever@eecs.umich.edu return bits(__data, index); 7172632Sstever@eecs.umich.edu }*/ 7182632Sstever@eecs.umich.edu EndBitUnion(McCtl) 7192632Sstever@eecs.umich.edu 7203716Sstever@eecs.umich.edu // Extended feature enable register 7215342Sstever@gmail.com BitUnion64(Efer) 7222632Sstever@eecs.umich.edu Bitfield<0> sce; // System call extensions 7232632Sstever@eecs.umich.edu Bitfield<8> lme; // Long mode enable 7242632Sstever@eecs.umich.edu Bitfield<10> lma; // Long mode active 7252632Sstever@eecs.umich.edu Bitfield<11> nxe; // No-execute enable 7262023SN/A Bitfield<12> svme; // Secure virtual machine enable 7272632Sstever@eecs.umich.edu Bitfield<14> ffxsr; // Fast fxsave/fxrstor 7282632Sstever@eecs.umich.edu EndBitUnion(Efer) 7295342Sstever@gmail.com 7301889SN/A BitUnion64(Star) 7312632Sstever@eecs.umich.edu Bitfield<31,0> targetEip; 7322632Sstever@eecs.umich.edu Bitfield<47,32> syscallCsAndSs; 7332632Sstever@eecs.umich.edu Bitfield<63,48> sysretCsAndSs; 7342632Sstever@eecs.umich.edu EndBitUnion(Star) 7353716Sstever@eecs.umich.edu 7363716Sstever@eecs.umich.edu BitUnion64(SfMask) 7375342Sstever@gmail.com Bitfield<31,0> mask; 7382632Sstever@eecs.umich.edu EndBitUnion(SfMask) 7392632Sstever@eecs.umich.edu 7402632Sstever@eecs.umich.edu BitUnion64(PerfEvtSel) 7412632Sstever@eecs.umich.edu Bitfield<7,0> eventMask; 7422632Sstever@eecs.umich.edu Bitfield<15,8> unitMask; 7432632Sstever@eecs.umich.edu Bitfield<16> usr; // User mode 7442632Sstever@eecs.umich.edu Bitfield<17> os; // Operating-system mode 7451888SN/A Bitfield<18> e; // Edge detect 7461888SN/A Bitfield<19> pc; // Pin control 7471869SN/A Bitfield<20> intEn; // Interrupt enable 7481869SN/A Bitfield<22> en; // Counter enable 7491858SN/A Bitfield<23> inv; // Invert mask 7505341Sstever@gmail.com Bitfield<31,24> counterMask; 7512598SN/A EndBitUnion(PerfEvtSel) 7522598SN/A 7532598SN/A BitUnion32(Syscfg) 7542598SN/A Bitfield<18> mfde; // MtrrFixDramEn 7551858SN/A Bitfield<19> mfdm; // MtrrFixDramModEn 7561858SN/A Bitfield<20> mvdm; // MtrrVarDramEn 7571858SN/A Bitfield<21> tom2; // MtrrTom2En 7581858SN/A EndBitUnion(Syscfg) 7591858SN/A 7601858SN/A BitUnion64(IorrBase) 7611858SN/A Bitfield<3> wr; // WrMem Enable 7621858SN/A Bitfield<4> rd; // RdMem Enable 7631858SN/A Bitfield<51,12> physbase; // Range physical base address 7641871SN/A EndBitUnion(IorrBase) 7651858SN/A 7661858SN/A BitUnion64(IorrMask) 7671858SN/A Bitfield<11> v; // I/O register pair enable (valid) 7681858SN/A Bitfield<51,12> physmask; // Range physical mask 7691858SN/A EndBitUnion(IorrMask) 7701858SN/A 7711858SN/A BitUnion64(Tom) 7721858SN/A Bitfield<51,23> physAddr; // Top of memory physical address 7731858SN/A EndBitUnion(Tom) 7741858SN/A 7751858SN/A BitUnion64(VmCrMsr) 7761859SN/A Bitfield<0> dpd; 7771859SN/A Bitfield<1> rInit; 7781869SN/A Bitfield<2> disA20M; 7791888SN/A EndBitUnion(VmCrMsr) 7802632Sstever@eecs.umich.edu 7811869SN/A BitUnion64(IgnneMsr) 7821884SN/A Bitfield<0> ignne; 7831884SN/A EndBitUnion(IgnneMsr) 7841884SN/A 7851884SN/A BitUnion64(SmmCtlMsr) 7861884SN/A Bitfield<0> dismiss; 7871884SN/A Bitfield<1> enter; 7881965SN/A Bitfield<2> smiCycle; 7891965SN/A Bitfield<3> exit; 7901965SN/A Bitfield<4> rsmCycle; 7912761Sstever@eecs.umich.edu EndBitUnion(SmmCtlMsr) 7921869SN/A 7931869SN/A /** 7942632Sstever@eecs.umich.edu * Segment Selector 7952667Sstever@eecs.umich.edu */ 7961869SN/A BitUnion64(SegSelector) 7971869SN/A // The following bitfield is not defined in the ISA, but it's useful 7982929Sktlim@umich.edu // when checking selectors in larger data types to make sure they 7992929Sktlim@umich.edu // aren't too large. 8003716Sstever@eecs.umich.edu Bitfield<63, 3> esi; // Extended selector 8012929Sktlim@umich.edu Bitfield<15, 3> si; // Selector Index 802955SN/A Bitfield<2> ti; // Table Indicator 8032598SN/A Bitfield<1, 0> rpl; // Requestor Privilege Level 8042598SN/A EndBitUnion(SegSelector) 8053546Sgblack@eecs.umich.edu 806955SN/A /** 807955SN/A * Segment Descriptors 808955SN/A */ 8091530SN/A 810955SN/A BitUnion64(SegDescriptor) 811955SN/A Bitfield<63, 56> baseHigh; 812955SN/A Bitfield<39, 16> baseLow; 813 Bitfield<55> g; // Granularity 814 Bitfield<54> d; // Default Operand Size 815 Bitfield<54> b; // Default Operand Size 816 Bitfield<53> l; // Long Attribute Bit 817 Bitfield<52> avl; // Available To Software 818 Bitfield<51, 48> limitHigh; 819 Bitfield<15, 0> limitLow; 820 Bitfield<47> p; // Present 821 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 822 Bitfield<44> s; // System 823 SubBitUnion(type, 43, 40) 824 // Specifies whether this descriptor is for code or data. 825 Bitfield<43> codeOrData; 826 827 // These bit fields are for code segments 828 Bitfield<42> c; // Conforming 829 Bitfield<41> r; // Readable 830 831 // These bit fields are for data segments 832 Bitfield<42> e; // Expand-Down 833 Bitfield<41> w; // Writable 834 835 // This is used for both code and data segments. 836 Bitfield<40> a; // Accessed 837 EndSubBitUnion(type) 838 EndBitUnion(SegDescriptor) 839 840 BitUnion64(SegAttr) 841 Bitfield<0> writable; 842 Bitfield<1> readable; 843 Bitfield<2> expandDown; 844 Bitfield<4, 3> dpl; 845 Bitfield<5> defaultSize; 846 Bitfield<6> longMode; 847 EndBitUnion(SegAttr) 848 849 BitUnion64(GateDescriptor) 850 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 851 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 852 Bitfield<31, 16> selector; // Target Code-Segment Selector 853 Bitfield<47> p; // Present 854 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 855 Bitfield<43, 40> type; 856 Bitfield<36, 32> count; // Parameter Count 857 EndBitUnion(GateDescriptor) 858 859 /** 860 * Descriptor-Table Registers 861 */ 862 BitUnion64(GDTR) 863 EndBitUnion(GDTR) 864 865 BitUnion64(IDTR) 866 EndBitUnion(IDTR) 867 868 BitUnion64(LDTR) 869 EndBitUnion(LDTR) 870 871 /** 872 * Task Register 873 */ 874 BitUnion64(TR) 875 EndBitUnion(TR) 876 877 878 /** 879 * Local APIC Base Register 880 */ 881 BitUnion64(LocalApicBase) 882 Bitfield<51, 12> base; 883 Bitfield<11> enable; 884 Bitfield<8> bsp; 885 EndBitUnion(LocalApicBase) 886}; 887 888#endif // __ARCH_X86_INTREGS_HH__ 889