misc.hh revision 5426 
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_MISCREGS_HH__
59#define __ARCH_X86_MISCREGS_HH__
60
61#include "arch/x86/segmentregs.hh"
62#include "arch/x86/x86_traits.hh"
63#include "base/bitunion.hh"
64
65//These get defined in some system headers (at least termbits.h). That confuses
66//things here significantly.
67#undef CR0
68#undef CR2
69#undef CR3
70
71namespace X86ISA
72{
73    enum CondFlagBit {
74        CFBit = 1 << 0,
75        PFBit = 1 << 2,
76        ECFBit = 1 << 3,
77        AFBit = 1 << 4,
78        EZFBit = 1 << 5,
79        ZFBit = 1 << 6,
80        SFBit = 1 << 7,
81        DFBit = 1 << 10,
82        OFBit = 1 << 11
83    };
84
85    enum RFLAGBit {
86        TFBit = 1 << 8,
87        IFBit = 1 << 9,
88        NTBit = 1 << 14,
89        RFBit = 1 << 16,
90        VMBit = 1 << 17,
91        ACBit = 1 << 18,
92        VIFBit = 1 << 19,
93        VIPBit = 1 << 20,
94        IDBit = 1 << 21
95    };
96
97    enum MiscRegIndex
98    {
99        // Control registers
100        // Most of these are invalid.
101        MISCREG_CR_BASE,
102        MISCREG_CR0 = MISCREG_CR_BASE,
103        MISCREG_CR1,
104        MISCREG_CR2,
105        MISCREG_CR3,
106        MISCREG_CR4,
107        MISCREG_CR5,
108        MISCREG_CR6,
109        MISCREG_CR7,
110        MISCREG_CR8,
111        MISCREG_CR9,
112        MISCREG_CR10,
113        MISCREG_CR11,
114        MISCREG_CR12,
115        MISCREG_CR13,
116        MISCREG_CR14,
117        MISCREG_CR15,
118
119        // Debug registers
120        MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
121        MISCREG_DR0 = MISCREG_DR_BASE,
122        MISCREG_DR1,
123        MISCREG_DR2,
124        MISCREG_DR3,
125        MISCREG_DR4,
126        MISCREG_DR5,
127        MISCREG_DR6,
128        MISCREG_DR7,
129
130        // Flags register
131        MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
132
133        /*
134         * Model Specific Registers
135         */
136        // Time stamp counter
137        MISCREG_TSC,
138
139        MISCREG_MTRRCAP,
140
141        MISCREG_SYSENTER_CS,
142        MISCREG_SYSENTER_ESP,
143        MISCREG_SYSENTER_EIP,
144
145        MISCREG_MCG_CAP,
146        MISCREG_MCG_STATUS,
147        MISCREG_MCG_CTL,
148
149        MISCREG_DEBUG_CTL_MSR,
150
151        MISCREG_LAST_BRANCH_FROM_IP,
152        MISCREG_LAST_BRANCH_TO_IP,
153        MISCREG_LAST_EXCEPTION_FROM_IP,
154        MISCREG_LAST_EXCEPTION_TO_IP,
155
156        MISCREG_MTRR_PHYS_BASE_BASE,
157        MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
158        MISCREG_MTRR_PHYS_BASE_1,
159        MISCREG_MTRR_PHYS_BASE_2,
160        MISCREG_MTRR_PHYS_BASE_3,
161        MISCREG_MTRR_PHYS_BASE_4,
162        MISCREG_MTRR_PHYS_BASE_5,
163        MISCREG_MTRR_PHYS_BASE_6,
164        MISCREG_MTRR_PHYS_BASE_7,
165
166        MISCREG_MTRR_PHYS_MASK_BASE,
167        MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
168        MISCREG_MTRR_PHYS_MASK_1,
169        MISCREG_MTRR_PHYS_MASK_2,
170        MISCREG_MTRR_PHYS_MASK_3,
171        MISCREG_MTRR_PHYS_MASK_4,
172        MISCREG_MTRR_PHYS_MASK_5,
173        MISCREG_MTRR_PHYS_MASK_6,
174        MISCREG_MTRR_PHYS_MASK_7,
175
176        MISCREG_MTRR_FIX_64K_00000,
177        MISCREG_MTRR_FIX_16K_80000,
178        MISCREG_MTRR_FIX_16K_A0000,
179        MISCREG_MTRR_FIX_4K_C0000,
180        MISCREG_MTRR_FIX_4K_C8000,
181        MISCREG_MTRR_FIX_4K_D0000,
182        MISCREG_MTRR_FIX_4K_D8000,
183        MISCREG_MTRR_FIX_4K_E0000,
184        MISCREG_MTRR_FIX_4K_E8000,
185        MISCREG_MTRR_FIX_4K_F0000,
186        MISCREG_MTRR_FIX_4K_F8000,
187
188        MISCREG_PAT,
189
190        MISCREG_DEF_TYPE,
191
192        MISCREG_MC_CTL_BASE,
193        MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
194        MISCREG_MC1_CTL,
195        MISCREG_MC2_CTL,
196        MISCREG_MC3_CTL,
197        MISCREG_MC4_CTL,
198        MISCREG_MC5_CTL,
199        MISCREG_MC6_CTL,
200        MISCREG_MC7_CTL,
201
202        MISCREG_MC_STATUS_BASE,
203        MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
204        MISCREG_MC1_STATUS,
205        MISCREG_MC2_STATUS,
206        MISCREG_MC3_STATUS,
207        MISCREG_MC4_STATUS,
208        MISCREG_MC5_STATUS,
209        MISCREG_MC6_STATUS,
210        MISCREG_MC7_STATUS,
211
212        MISCREG_MC_ADDR_BASE,
213        MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
214        MISCREG_MC1_ADDR,
215        MISCREG_MC2_ADDR,
216        MISCREG_MC3_ADDR,
217        MISCREG_MC4_ADDR,
218        MISCREG_MC5_ADDR,
219        MISCREG_MC6_ADDR,
220        MISCREG_MC7_ADDR,
221
222        MISCREG_MC_MISC_BASE,
223        MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
224        MISCREG_MC1_MISC,
225        MISCREG_MC2_MISC,
226        MISCREG_MC3_MISC,
227        MISCREG_MC4_MISC,
228        MISCREG_MC5_MISC,
229        MISCREG_MC6_MISC,
230        MISCREG_MC7_MISC,
231
232        // Extended feature enable register
233        MISCREG_EFER,
234
235        MISCREG_STAR,
236        MISCREG_LSTAR,
237        MISCREG_CSTAR,
238
239        MISCREG_SF_MASK,
240
241        MISCREG_KERNEL_GS_BASE,
242
243        MISCREG_TSC_AUX,
244
245        MISCREG_PERF_EVT_SEL_BASE,
246        MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
247        MISCREG_PERF_EVT_SEL1,
248        MISCREG_PERF_EVT_SEL2,
249        MISCREG_PERF_EVT_SEL3,
250
251        MISCREG_PERF_EVT_CTR_BASE,
252        MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
253        MISCREG_PERF_EVT_CTR1,
254        MISCREG_PERF_EVT_CTR2,
255        MISCREG_PERF_EVT_CTR3,
256
257        MISCREG_SYSCFG,
258
259        MISCREG_IORR_BASE_BASE,
260        MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
261        MISCREG_IORR_BASE1,
262
263        MISCREG_IORR_MASK_BASE,
264        MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
265        MISCREG_IORR_MASK1,
266
267        MISCREG_TOP_MEM,
268        MISCREG_TOP_MEM2,
269
270        MISCREG_VM_CR,
271        MISCREG_IGNNE,
272        MISCREG_SMM_CTL,
273        MISCREG_VM_HSAVE_PA,
274
275        /*
276         * Segment registers
277         */
278        // Segment selectors
279        MISCREG_SEG_SEL_BASE,
280        MISCREG_ES = MISCREG_SEG_SEL_BASE,
281        MISCREG_CS,
282        MISCREG_SS,
283        MISCREG_DS,
284        MISCREG_FS,
285        MISCREG_GS,
286        MISCREG_HS,
287        MISCREG_TSL,
288        MISCREG_TSG,
289        MISCREG_LS,
290        MISCREG_MS,
291        MISCREG_TR,
292        MISCREG_IDTR,
293
294        // Hidden segment base field
295        MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
296        MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
297        MISCREG_CS_BASE,
298        MISCREG_SS_BASE,
299        MISCREG_DS_BASE,
300        MISCREG_FS_BASE,
301        MISCREG_GS_BASE,
302        MISCREG_HS_BASE,
303        MISCREG_TSL_BASE,
304        MISCREG_TSG_BASE,
305        MISCREG_LS_BASE,
306        MISCREG_MS_BASE,
307        MISCREG_TR_BASE,
308        MISCREG_IDTR_BASE,
309
310        // The effective segment base, ie what is actually added to an
311        // address. In 64 bit mode this can be different from the above,
312        // namely 0.
313        MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
314        MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
315        MISCREG_CS_EFF_BASE,
316        MISCREG_SS_EFF_BASE,
317        MISCREG_DS_EFF_BASE,
318        MISCREG_FS_EFF_BASE,
319        MISCREG_GS_EFF_BASE,
320        MISCREG_HS_EFF_BASE,
321        MISCREG_TSL_EFF_BASE,
322        MISCREG_TSG_EFF_BASE,
323        MISCREG_LS_EFF_BASE,
324        MISCREG_MS_EFF_BASE,
325        MISCREG_TR_EFF_BASE,
326        MISCREG_IDTR_EFF_BASE,
327
328        // Hidden segment limit field
329        MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
330        MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
331        MISCREG_CS_LIMIT,
332        MISCREG_SS_LIMIT,
333        MISCREG_DS_LIMIT,
334        MISCREG_FS_LIMIT,
335        MISCREG_GS_LIMIT,
336        MISCREG_HS_LIMIT,
337        MISCREG_TSL_LIMIT,
338        MISCREG_TSG_LIMIT,
339        MISCREG_LS_LIMIT,
340        MISCREG_MS_LIMIT,
341        MISCREG_TR_LIMIT,
342        MISCREG_IDTR_LIMIT,
343
344        // Hidden segment limit attributes
345        MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
346        MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
347        MISCREG_CS_ATTR,
348        MISCREG_SS_ATTR,
349        MISCREG_DS_ATTR,
350        MISCREG_FS_ATTR,
351        MISCREG_GS_ATTR,
352        MISCREG_HS_ATTR,
353        MISCREG_TSL_ATTR,
354        MISCREG_TSG_ATTR,
355        MISCREG_LS_ATTR,
356        MISCREG_MS_ATTR,
357        MISCREG_TR_ATTR,
358        MISCREG_IDTR_ATTR,
359
360        // Floating point control registers
361        MISCREG_X87_TOP =
362            MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
363
364        //XXX Add "Model-Specific Registers"
365
366        MISCREG_APIC_BASE,
367
368        MISCREG_APIC_START,
369        MISCREG_APIC_ID = MISCREG_APIC_START,
370        MISCREG_APIC_VERSION,
371        MISCREG_APIC_TASK_PRIORITY,
372        MISCREG_APIC_ARBITRATION_PRIORITY,
373        MISCREG_APIC_PROCESSOR_PRIORITY,
374        MISCREG_APIC_EOI,
375        MISCREG_APIC_LOGICAL_DESTINATION,
376        MISCREG_APIC_DESTINATION_FORMAT,
377        MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR,
378
379        MISCREG_APIC_IN_SERVICE_BASE,
380
381        MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16,
382
383        MISCREG_APIC_INTERRUPT_REQUEST_BASE =
384            MISCREG_APIC_TRIGGER_MODE_BASE + 16,
385
386        MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16,
387        MISCREG_APIC_INTERRUPT_COMMAND_LOW,
388        MISCREG_APIC_INTERRUPT_COMMAND_HIGH,
389        MISCREG_APIC_LVT_TIMER,
390        MISCREG_APIC_LVT_THERMAL_SENSOR,
391        MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
392        MISCREG_APIC_LVT_LINT0,
393        MISCREG_APIC_LVT_LINT1,
394        MISCREG_APIC_LVT_ERROR,
395        MISCREG_APIC_INITIAL_COUNT,
396        MISCREG_APIC_CURRENT_COUNT,
397        MISCREG_APIC_DIVIDE_COUNT,
398        MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT,
399
400        MISCREG_APIC_INTERNAL_STATE,
401
402        // "Fake" MSRs for internally implemented devices
403        MISCREG_PCI_CONFIG_ADDRESS,
404
405        NUM_MISCREGS
406    };
407
408    static inline MiscRegIndex
409    MISCREG_CR(int index)
410    {
411        return (MiscRegIndex)(MISCREG_CR_BASE + index);
412    }
413
414    static inline MiscRegIndex
415    MISCREG_DR(int index)
416    {
417        return (MiscRegIndex)(MISCREG_DR_BASE + index);
418    }
419
420    static inline MiscRegIndex
421    MISCREG_MTRR_PHYS_BASE(int index)
422    {
423        return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
424    }
425
426    static inline MiscRegIndex
427    MISCREG_MTRR_PHYS_MASK(int index)
428    {
429        return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
430    }
431
432    static inline MiscRegIndex
433    MISCREG_MC_CTL(int index)
434    {
435        return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
436    }
437
438    static inline MiscRegIndex
439    MISCREG_MC_STATUS(int index)
440    {
441        return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
442    }
443
444    static inline MiscRegIndex
445    MISCREG_MC_ADDR(int index)
446    {
447        return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
448    }
449
450    static inline MiscRegIndex
451    MISCREG_MC_MISC(int index)
452    {
453        return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
454    }
455
456    static inline MiscRegIndex
457    MISCREG_PERF_EVT_SEL(int index)
458    {
459        return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
460    }
461
462    static inline MiscRegIndex
463    MISCREG_PERF_EVT_CTR(int index)
464    {
465        return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
466    }
467
468    static inline MiscRegIndex
469    MISCREG_IORR_BASE(int index)
470    {
471        return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
472    }
473
474    static inline MiscRegIndex
475    MISCREG_IORR_MASK(int index)
476    {
477        return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
478    }
479
480    static inline MiscRegIndex
481    MISCREG_SEG_SEL(int index)
482    {
483        return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
484    }
485
486    static inline MiscRegIndex
487    MISCREG_SEG_BASE(int index)
488    {
489        return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
490    }
491
492    static inline MiscRegIndex
493    MISCREG_SEG_EFF_BASE(int index)
494    {
495        return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
496    }
497
498    static inline MiscRegIndex
499    MISCREG_SEG_LIMIT(int index)
500    {
501        return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
502    }
503
504    static inline MiscRegIndex
505    MISCREG_SEG_ATTR(int index)
506    {
507        return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
508    }
509
510    static inline MiscRegIndex
511    MISCREG_APIC_IN_SERVICE(int index)
512    {
513        return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index);
514    }
515
516    static inline MiscRegIndex
517    MISCREG_APIC_TRIGGER_MODE(int index)
518    {
519        return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index);
520    }
521
522    static inline MiscRegIndex
523    MISCREG_APIC_INTERRUPT_REQUEST(int index)
524    {
525        return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index);
526    }
527
528    /**
529     * A type to describe the condition code bits of the RFLAGS register,
530     * plus two flags, EZF and ECF, which are only visible to microcode.
531     */
532    BitUnion64(CCFlagBits)
533        Bitfield<11> of;
534        Bitfield<7> sf;
535        Bitfield<6> zf;
536        Bitfield<5> ezf;
537        Bitfield<4> af;
538        Bitfield<3> ecf;
539        Bitfield<2> pf;
540        Bitfield<0> cf;
541    EndBitUnion(CCFlagBits)
542
543    /**
544     * RFLAGS
545     */
546    BitUnion64(RFLAGS)
547        Bitfield<21> id; // ID Flag
548        Bitfield<20> vip; // Virtual Interrupt Pending
549        Bitfield<19> vif; // Virtual Interrupt Flag
550        Bitfield<18> ac; // Alignment Check
551        Bitfield<17> vm; // Virtual-8086 Mode
552        Bitfield<16> rf; // Resume Flag
553        Bitfield<14> nt; // Nested Task
554        Bitfield<13, 12> iopl; // I/O Privilege Level
555        Bitfield<11> of; // Overflow Flag
556        Bitfield<10> df; // Direction Flag
557        Bitfield<9> intf; // Interrupt Flag
558        Bitfield<8> tf; // Trap Flag
559        Bitfield<7> sf; // Sign Flag
560        Bitfield<6> zf; // Zero Flag
561        Bitfield<4> af; // Auxiliary Flag
562        Bitfield<2> pf; // Parity Flag
563        Bitfield<0> cf; // Carry Flag
564    EndBitUnion(RFLAGS)
565
566    /**
567     * Control registers
568     */
569    BitUnion64(CR0)
570        Bitfield<31> pg; // Paging
571        Bitfield<30> cd; // Cache Disable
572        Bitfield<29> nw; // Not Writethrough
573        Bitfield<18> am; // Alignment Mask
574        Bitfield<16> wp; // Write Protect
575        Bitfield<5> ne; // Numeric Error
576        Bitfield<4> et; // Extension Type
577        Bitfield<3> ts; // Task Switched
578        Bitfield<2> em; // Emulation
579        Bitfield<1> mp; // Monitor Coprocessor
580        Bitfield<0> pe; // Protection Enabled
581    EndBitUnion(CR0)
582
583    // Page Fault Virtual Address
584    BitUnion64(CR2)
585        Bitfield<31, 0> legacy;
586    EndBitUnion(CR2)
587
588    BitUnion64(CR3)
589        Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
590                                   // Base Address
591        Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
592                               // Base Address
593        Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
594                                 // Base Address
595        Bitfield<4> pcd; // Page-Level Cache Disable
596        Bitfield<3> pwt; // Page-Level Writethrough
597    EndBitUnion(CR3)
598
599    BitUnion64(CR4)
600        Bitfield<10> osxmmexcpt; // Operating System Unmasked
601                                 // Exception Support
602        Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
603        Bitfield<8> pce; // Performance-Monitoring Counter Enable
604        Bitfield<7> pge; // Page-Global Enable
605        Bitfield<6> mce; // Machine Check Enable
606        Bitfield<5> pae; // Physical-Address Extension
607        Bitfield<4> pse; // Page Size Extensions
608        Bitfield<3> de; // Debugging Extensions
609        Bitfield<2> tsd; // Time Stamp Disable
610        Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
611        Bitfield<0> vme; // Virtual-8086 Mode Extensions
612    EndBitUnion(CR4)
613
614    BitUnion64(CR8)
615        Bitfield<3, 0> tpr; // Task Priority Register
616    EndBitUnion(CR8)
617
618    // MTRR capabilities
619    BitUnion64(MTRRcap)
620        Bitfield<7, 0> vcnt; // Variable-Range Register Count
621        Bitfield<8> fix; // Fixed-Range Registers
622        Bitfield<10> wc; // Write-Combining
623    EndBitUnion(MTRRcap)
624
625    /**
626     * SYSENTER configuration registers
627     */
628    BitUnion64(SysenterCS)
629        Bitfield<15, 0> targetCS;
630    EndBitUnion(SysenterCS)
631
632    BitUnion64(SysenterESP)
633        Bitfield<31, 0> targetESP;
634    EndBitUnion(SysenterESP)
635
636    BitUnion64(SysenterEIP)
637        Bitfield<31, 0> targetEIP;
638    EndBitUnion(SysenterEIP)
639
640    /**
641     * Global machine check registers
642     */
643    BitUnion64(McgCap)
644        Bitfield<7, 0> count; // Number of error reporting register banks
645        Bitfield<8> MCGCP; // MCG_CTL register present.
646    EndBitUnion(McgCap)
647
648    BitUnion64(McgStatus)
649        Bitfield<0> ripv; // Restart-IP valid
650        Bitfield<1> eipv; // Error-IP valid
651        Bitfield<2> mcip; // Machine check in-progress
652    EndBitUnion(McgStatus)
653
654    BitUnion64(DebugCtlMsr)
655        Bitfield<0> lbr; // Last-branch record
656        Bitfield<1> btf; // Branch single step
657        Bitfield<2> pb0; // Performance monitoring pin control 0
658        Bitfield<3> pb1; // Performance monitoring pin control 1
659        Bitfield<4> pb2; // Performance monitoring pin control 2
660        Bitfield<5> pb3; // Performance monitoring pin control 3
661        /*uint64_t pb(int index)
662        {
663            return bits(__data, index + 2);
664        }*/
665    EndBitUnion(DebugCtlMsr)
666
667    BitUnion64(MtrrPhysBase)
668        Bitfield<7, 0> type; // Default memory type
669        Bitfield<51, 12> physbase; // Range physical base address
670    EndBitUnion(MtrrPhysBase)
671
672    BitUnion64(MtrrPhysMask)
673        Bitfield<11> valid; // MTRR pair enable
674        Bitfield<51, 12> physmask; // Range physical mask
675    EndBitUnion(MtrrPhysMask)
676
677    BitUnion64(MtrrFixed)
678        /*uint64_t type(int index)
679        {
680            return bits(__data, index * 8 + 7, index * 8);
681        }*/
682    EndBitUnion(MtrrFixed)
683
684    BitUnion64(Pat)
685        /*uint64_t pa(int index)
686        {
687            return bits(__data, index * 8 + 2, index * 8);
688        }*/
689    EndBitUnion(Pat)
690
691    BitUnion64(MtrrDefType)
692        Bitfield<7, 0> type; // Default type
693        Bitfield<10> fe; // Fixed range enable
694        Bitfield<11> e; // MTRR enable
695    EndBitUnion(MtrrDefType)
696
697    /**
698     * Machine check
699     */
700    BitUnion64(McStatus)
701        Bitfield<15,0> mcaErrorCode;
702        Bitfield<31,16> modelSpecificCode;
703        Bitfield<56,32> otherInfo;
704        Bitfield<57> pcc; // Processor-context corrupt
705        Bitfield<58> addrv; // Error-address register valid
706        Bitfield<59> miscv; // Miscellaneous-error register valid
707        Bitfield<60> en; // Error condition enabled
708        Bitfield<61> uc; // Uncorrected error
709        Bitfield<62> over; // Status register overflow
710        Bitfield<63> val; // Valid
711    EndBitUnion(McStatus)
712
713    BitUnion64(McCtl)
714        /*uint64_t en(int index)
715        {
716            return bits(__data, index);
717        }*/
718    EndBitUnion(McCtl)
719
720    // Extended feature enable register
721    BitUnion64(Efer)
722        Bitfield<0> sce; // System call extensions
723        Bitfield<8> lme; // Long mode enable
724        Bitfield<10> lma; // Long mode active
725        Bitfield<11> nxe; // No-execute enable
726        Bitfield<12> svme; // Secure virtual machine enable
727        Bitfield<14> ffxsr; // Fast fxsave/fxrstor
728    EndBitUnion(Efer)
729
730    BitUnion64(Star)
731        Bitfield<31,0> targetEip;
732        Bitfield<47,32> syscallCsAndSs;
733        Bitfield<63,48> sysretCsAndSs;
734    EndBitUnion(Star)
735
736    BitUnion64(SfMask)
737        Bitfield<31,0> mask;
738    EndBitUnion(SfMask)
739
740    BitUnion64(PerfEvtSel)
741        Bitfield<7,0> eventMask;
742        Bitfield<15,8> unitMask;
743        Bitfield<16> usr; // User mode
744        Bitfield<17> os; // Operating-system mode
745        Bitfield<18> e; // Edge detect
746        Bitfield<19> pc; // Pin control
747        Bitfield<20> intEn; // Interrupt enable
748        Bitfield<22> en; // Counter enable
749        Bitfield<23> inv; // Invert mask
750        Bitfield<31,24> counterMask;
751    EndBitUnion(PerfEvtSel)
752
753    BitUnion32(Syscfg)
754        Bitfield<18> mfde; // MtrrFixDramEn
755        Bitfield<19> mfdm; // MtrrFixDramModEn
756        Bitfield<20> mvdm; // MtrrVarDramEn
757        Bitfield<21> tom2; // MtrrTom2En
758    EndBitUnion(Syscfg)
759
760    BitUnion64(IorrBase)
761        Bitfield<3> wr; // WrMem Enable
762        Bitfield<4> rd; // RdMem Enable
763        Bitfield<51,12> physbase; // Range physical base address
764    EndBitUnion(IorrBase)
765
766    BitUnion64(IorrMask)
767        Bitfield<11> v; // I/O register pair enable (valid)
768        Bitfield<51,12> physmask; // Range physical mask
769    EndBitUnion(IorrMask)
770
771    BitUnion64(Tom)
772        Bitfield<51,23> physAddr; // Top of memory physical address
773    EndBitUnion(Tom)
774
775    BitUnion64(VmCrMsr)
776        Bitfield<0> dpd;
777        Bitfield<1> rInit;
778        Bitfield<2> disA20M;
779    EndBitUnion(VmCrMsr)
780
781    BitUnion64(IgnneMsr)
782        Bitfield<0> ignne;
783    EndBitUnion(IgnneMsr)
784
785    BitUnion64(SmmCtlMsr)
786        Bitfield<0> dismiss;
787        Bitfield<1> enter;
788        Bitfield<2> smiCycle;
789        Bitfield<3> exit;
790        Bitfield<4> rsmCycle;
791    EndBitUnion(SmmCtlMsr)
792
793    /**
794     * Segment Selector
795     */
796    BitUnion64(SegSelector)
797        // The following bitfield is not defined in the ISA, but it's useful
798        // when checking selectors in larger data types to make sure they
799        // aren't too large.
800        Bitfield<63, 3> esi; // Extended selector
801        Bitfield<15, 3> si; // Selector Index
802        Bitfield<2> ti; // Table Indicator
803        Bitfield<1, 0> rpl; // Requestor Privilege Level
804    EndBitUnion(SegSelector)
805
806    /**
807     * Segment Descriptors
808     */
809
810    BitUnion64(SegDescriptor)
811        Bitfield<63, 56> baseHigh;
812        Bitfield<39, 16> baseLow;
813        Bitfield<55> g; // Granularity
814        Bitfield<54> d; // Default Operand Size
815        Bitfield<54> b; // Default Operand Size
816        Bitfield<53> l; // Long Attribute Bit
817        Bitfield<52> avl; // Available To Software
818        Bitfield<51, 48> limitHigh;
819        Bitfield<15, 0> limitLow;
820        Bitfield<47> p; // Present
821        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
822        Bitfield<44> s; // System
823        SubBitUnion(type, 43, 40)
824            // Specifies whether this descriptor is for code or data.
825            Bitfield<43> codeOrData;
826
827            // These bit fields are for code segments
828            Bitfield<42> c; // Conforming
829            Bitfield<41> r; // Readable
830
831            // These bit fields are for data segments
832            Bitfield<42> e; // Expand-Down
833            Bitfield<41> w; // Writable
834
835            // This is used for both code and data segments.
836            Bitfield<40> a; // Accessed
837        EndSubBitUnion(type)
838    EndBitUnion(SegDescriptor)
839
840    BitUnion64(SegAttr)
841        Bitfield<0> writable;
842        Bitfield<1> readable;
843        Bitfield<2> expandDown;
844        Bitfield<4, 3> dpl;
845        Bitfield<5> defaultSize;
846        Bitfield<6> longMode;
847    EndBitUnion(SegAttr)
848
849    BitUnion64(GateDescriptor)
850        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
851        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
852        Bitfield<31, 16> selector; // Target Code-Segment Selector
853        Bitfield<47> p; // Present
854        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
855        Bitfield<43, 40> type;
856        Bitfield<36, 32> count; // Parameter Count
857    EndBitUnion(GateDescriptor)
858
859    /**
860     * Descriptor-Table Registers
861     */
862    BitUnion64(GDTR)
863    EndBitUnion(GDTR)
864
865    BitUnion64(IDTR)
866    EndBitUnion(IDTR)
867
868    BitUnion64(LDTR)
869    EndBitUnion(LDTR)
870
871    /**
872     * Task Register
873     */
874    BitUnion64(TR)
875    EndBitUnion(TR)
876
877
878    /**
879     * Local APIC Base Register
880     */
881    BitUnion64(LocalApicBase)
882        Bitfield<51, 12> base;
883        Bitfield<11> enable;
884        Bitfield<8> bsp;
885    EndBitUnion(LocalApicBase)
886};
887
888#endif // __ARCH_X86_INTREGS_HH__
889