microasm.isa revision 4620
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24309Sgblack@eecs.umich.edu
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564309Sgblack@eecs.umich.edu// Authors: Gabe Black
574309Sgblack@eecs.umich.edu
584533Sgblack@eecs.umich.edu//Include the definitions of the micro ops.
594533Sgblack@eecs.umich.edu//These are StaticInst classes which stand on their own and make up an
604537Sgblack@eecs.umich.edu//internal instruction set, and also python representations which are passed
614537Sgblack@eecs.umich.edu//into the microcode assembler.
624533Sgblack@eecs.umich.edu##include "microops/microops.isa"
634533Sgblack@eecs.umich.edu
644537Sgblack@eecs.umich.edu//Include code to build macroops in both C++ and python.
654533Sgblack@eecs.umich.edu##include "macroop.isa"
664528Sgblack@eecs.umich.edu
674528Sgblack@eecs.umich.edulet {{
684528Sgblack@eecs.umich.edu    import sys
694528Sgblack@eecs.umich.edu    sys.path[0:0] = ["src/arch/x86/isa/"]
704528Sgblack@eecs.umich.edu    from insts import microcode
714605Sgblack@eecs.umich.edu    # print microcode
724528Sgblack@eecs.umich.edu    from micro_asm import MicroAssembler, Rom_Macroop, Rom
734528Sgblack@eecs.umich.edu    mainRom = Rom('main ROM')
744528Sgblack@eecs.umich.edu    assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
754615Sgblack@eecs.umich.edu    # Add in symbols for the microcode registers
764615Sgblack@eecs.umich.edu    for num in range(15):
774615Sgblack@eecs.umich.edu        assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
784615Sgblack@eecs.umich.edu    # Add in symbols for the segment descriptor registers
794615Sgblack@eecs.umich.edu    for letter in ("C", "D", "E", "F", "G", "S"):
804615Sgblack@eecs.umich.edu        assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
814615Sgblack@eecs.umich.edu    # Miscellaneous symbols
824615Sgblack@eecs.umich.edu    symbols = {
834615Sgblack@eecs.umich.edu        "reg" : "env.reg",
844615Sgblack@eecs.umich.edu        "regm" : "env.regm",
854615Sgblack@eecs.umich.edu        "imm" : "IMMEDIATE",
864615Sgblack@eecs.umich.edu        "disp" : "DISPLACEMENT",
874615Sgblack@eecs.umich.edu        "scale" : "env.scale",
884615Sgblack@eecs.umich.edu        "index" : "env.index",
894615Sgblack@eecs.umich.edu        "base" : "env.base",
904615Sgblack@eecs.umich.edu        "dsz" : "env.dataSize",
914615Sgblack@eecs.umich.edu        "osz" : "env.operandSize",
924615Sgblack@eecs.umich.edu        "ssz" : "env.stackSize"
934615Sgblack@eecs.umich.edu    }
944620Sgblack@eecs.umich.edu
954620Sgblack@eecs.umich.edu    for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
964620Sgblack@eecs.umich.edu        assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
974615Sgblack@eecs.umich.edu    assembler.symbols.update(symbols)
984615Sgblack@eecs.umich.edu
994615Sgblack@eecs.umich.edu    # Code literal which forces a default 64 bit operand size in 64 bit mode.
1004615Sgblack@eecs.umich.edu    assembler.symbols["oszIn64Override"] = '''
1014615Sgblack@eecs.umich.edu    if (machInst.mode.submode == SixtyFourBitMode &&
1024615Sgblack@eecs.umich.edu            env.dataSize == 4)
1034615Sgblack@eecs.umich.edu        env.dataSize = 8;
1044615Sgblack@eecs.umich.edu    '''
1054615Sgblack@eecs.umich.edu
1064528Sgblack@eecs.umich.edu    macroopDict = assembler.assemble(microcode)
1074528Sgblack@eecs.umich.edu}};
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