xref: /gem5/src/arch/x86/isa/microasm.isa

// -*- mode:c++ -*-

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// Authors: Gabe Black

//Include the definitions of the micro ops.
//These are StaticInst classes which stand on their own and make up an
//internal instruction set, and also python representations which are passed
//into the microcode assembler.
##include "microops/microops.isa"

//Include code to build macroops in both C++ and python.
##include "macroop.isa"

let {{
    import sys
    sys.path[0:0] = ["src/arch/x86/isa/"]
    from insts import microcode
    # print microcode
    from micro_asm import MicroAssembler, Rom_Macroop, Rom
    mainRom = Rom('main ROM')
    assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
    # Add in symbols for the microcode registers
    for num in range(15):
        assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
    # Add in symbols for the segment descriptor registers
    for letter in ("C", "D", "E", "F", "G", "S"):
        assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
    # Miscellaneous symbols
    symbols = {
        "reg" : "env.reg",
        "regm" : "env.regm",
        "imm" : "IMMEDIATE",
        "disp" : "DISPLACEMENT",
        "scale" : "env.scale",
        "index" : "env.index",
        "base" : "env.base",
        "dsz" : "env.dataSize",
        "osz" : "env.operandSize",
        "ssz" : "env.stackSize"
    }

    for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
        assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
    assembler.symbols.update(symbols)

    # Code literal which forces a default 64 bit operand size in 64 bit mode.
    assembler.symbols["oszIn64Override"] = '''
    if (machInst.mode.submode == SixtyFourBitMode &&
            env.dataSize == 4)
        env.dataSize = 8;
    '''

    macroopDict = assembler.assemble(microcode)
}};