logical.py revision 8610 
110611SAndreas.Sandberg@ARM.com# Copyright (c) 2007 The Hewlett-Packard Development Company
210611SAndreas.Sandberg@ARM.com# All rights reserved.
310611SAndreas.Sandberg@ARM.com#
410611SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall
510611SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual
610611SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating
710611SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software
810611SAndreas.Sandberg@ARM.com# licensed hereunder.  You may use the software subject to the license
910611SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated
1010611SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software,
1110611SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form.
1210611SAndreas.Sandberg@ARM.com#
1310611SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without
1410611SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are
1510696SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright
1610696SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer;
1710696SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright
1810611SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the
1910611SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution;
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2210611SAndreas.Sandberg@ARM.com# this software without specific prior written permission.
2310611SAndreas.Sandberg@ARM.com#
2410611SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2510611SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
2610611SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2710611SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2810611SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2910611SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
3010611SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
3110611SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
3210611SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3310611SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3410611SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3510611SAndreas.Sandberg@ARM.com#
3610611SAndreas.Sandberg@ARM.com# Authors: Gabe Black
3710611SAndreas.Sandberg@ARM.com
3810611SAndreas.Sandberg@ARM.commicrocode = '''
3910611SAndreas.Sandberg@ARM.comdef macroop OR_R_R
4010611SAndreas.Sandberg@ARM.com{
4110611SAndreas.Sandberg@ARM.com    or reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
4210696SAndreas.Sandberg@ARM.com};
4310696SAndreas.Sandberg@ARM.com
4410696SAndreas.Sandberg@ARM.comdef macroop OR_M_I
4510696SAndreas.Sandberg@ARM.com{
4610696SAndreas.Sandberg@ARM.com    limm t2, imm
4710696SAndreas.Sandberg@ARM.com    ldst t1, seg, sib, disp
4810696SAndreas.Sandberg@ARM.com    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
4910611SAndreas.Sandberg@ARM.com    st t1, seg, sib, disp
5010611SAndreas.Sandberg@ARM.com};
5110611SAndreas.Sandberg@ARM.com
5210611SAndreas.Sandberg@ARM.comdef macroop OR_P_I
5310611SAndreas.Sandberg@ARM.com{
5410611SAndreas.Sandberg@ARM.com    limm t2, imm
5510696SAndreas.Sandberg@ARM.com    rdip t7
5610696SAndreas.Sandberg@ARM.com    ldst t1, seg, riprel, disp
5710696SAndreas.Sandberg@ARM.com    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
5810696SAndreas.Sandberg@ARM.com    st t1, seg, riprel, disp
5910696SAndreas.Sandberg@ARM.com};
6010696SAndreas.Sandberg@ARM.com
6110696SAndreas.Sandberg@ARM.comdef macroop OR_LOCKED_M_I
6210696SAndreas.Sandberg@ARM.com{
6310696SAndreas.Sandberg@ARM.com    limm t2, imm
6410696SAndreas.Sandberg@ARM.com    mfence
6510696SAndreas.Sandberg@ARM.com    ldstl t1, seg, sib, disp
6610696SAndreas.Sandberg@ARM.com    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
6710696SAndreas.Sandberg@ARM.com    stul t1, seg, sib, disp
6810696SAndreas.Sandberg@ARM.com    mfence
6910696SAndreas.Sandberg@ARM.com};
7010696SAndreas.Sandberg@ARM.com
7110696SAndreas.Sandberg@ARM.comdef macroop OR_LOCKED_P_I
7210696SAndreas.Sandberg@ARM.com{
7310696SAndreas.Sandberg@ARM.com    limm t2, imm
7410696SAndreas.Sandberg@ARM.com    rdip t7
7510696SAndreas.Sandberg@ARM.com    mfence
7610696SAndreas.Sandberg@ARM.com    ldstl t1, seg, riprel, disp
7710696SAndreas.Sandberg@ARM.com    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
7810696SAndreas.Sandberg@ARM.com    stul t1, seg, riprel, disp
79    mfence
80};
81
82def macroop OR_M_R
83{
84    ldst t1, seg, sib, disp
85    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
86    st t1, seg, sib, disp
87};
88
89def macroop OR_P_R
90{
91    rdip t7
92    ldst t1, seg, riprel, disp
93    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
94    st t1, seg, riprel, disp
95};
96
97def macroop OR_LOCKED_M_R
98{
99    mfence
100    ldstl t1, seg, sib, disp
101    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
102    stul t1, seg, sib, disp
103    mfence
104};
105
106def macroop OR_LOCKED_P_R
107{
108    rdip t7
109    mfence
110    ldstl t1, seg, riprel, disp
111    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
112    stul t1, seg, riprel, disp
113    mfence
114};
115
116def macroop OR_R_M
117{
118    ld t1, seg, sib, disp
119    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
120};
121
122def macroop OR_R_P
123{
124    rdip t7
125    ld t1, seg, riprel, disp
126    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
127};
128
129def macroop OR_R_I
130{
131    limm t1, imm
132    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
133};
134
135def macroop XOR_R_R
136{
137    xor reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
138};
139
140def macroop XOR_R_I
141{
142    limm t1, imm
143    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
144};
145
146def macroop XOR_M_I
147{
148    limm t2, imm
149    ldst t1, seg, sib, disp
150    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
151    st t1, seg, sib, disp
152};
153
154def macroop XOR_P_I
155{
156    limm t2, imm
157    rdip t7
158    ldst t1, seg, riprel, disp
159    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
160    st t1, seg, riprel, disp
161};
162
163def macroop XOR_LOCKED_M_I
164{
165    limm t2, imm
166    mfence
167    ldstl t1, seg, sib, disp
168    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
169    stul t1, seg, sib, disp
170    mfence
171};
172
173def macroop XOR_LOCKED_P_I
174{
175    limm t2, imm
176    rdip t7
177    mfence
178    ldstl t1, seg, riprel, disp
179    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
180    stul t1, seg, riprel, disp
181    mfence
182};
183
184def macroop XOR_M_R
185{
186    ldst t1, seg, sib, disp
187    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
188    st t1, seg, sib, disp
189};
190
191def macroop XOR_P_R
192{
193    rdip t7
194    ldst t1, seg, riprel, disp
195    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
196    st t1, seg, riprel, disp
197};
198
199def macroop XOR_LOCKED_M_R
200{
201    mfence
202    ldstl t1, seg, sib, disp
203    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
204    stul t1, seg, sib, disp
205    mfence
206};
207
208def macroop XOR_LOCKED_P_R
209{
210    rdip t7
211    mfence
212    ldstl t1, seg, riprel, disp
213    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
214    stul t1, seg, riprel, disp
215    mfence
216};
217
218def macroop XOR_R_M
219{
220    ld t1, seg, sib, disp
221    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
222};
223
224def macroop XOR_R_P
225{
226    rdip t7
227    ld t1, seg, riprel, disp
228    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
229};
230
231def macroop AND_R_R
232{
233    and reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
234};
235
236def macroop AND_R_M
237{
238    ld t1, seg, sib, disp
239    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
240};
241
242def macroop AND_R_P
243{
244    rdip t7
245    ld t1, seg, riprel, disp
246    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
247};
248
249def macroop AND_R_I
250{
251    limm t1, imm
252    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
253};
254
255def macroop AND_M_I
256{
257    ldst t2, seg, sib, disp
258    limm t1, imm
259    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
260    st t2, seg, sib, disp
261};
262
263def macroop AND_P_I
264{
265    rdip t7
266    ldst t2, seg, riprel, disp
267    limm t1, imm
268    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
269    st t2, seg, riprel, disp
270};
271
272def macroop AND_LOCKED_M_I
273{
274    mfence
275    ldstl t2, seg, sib, disp
276    limm t1, imm
277    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
278    stul t2, seg, sib, disp
279    mfence
280};
281
282def macroop AND_LOCKED_P_I
283{
284    rdip t7
285    mfence
286    ldstl t2, seg, riprel, disp
287    limm t1, imm
288    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
289    stul t2, seg, riprel, disp
290    mfence
291};
292
293def macroop AND_M_R
294{
295    ldst t1, seg, sib, disp
296    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
297    st t1, seg, sib, disp
298};
299
300def macroop AND_P_R
301{
302    rdip t7
303    ldst t1, seg, riprel, disp
304    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
305    st t1, seg, riprel, disp
306};
307
308def macroop AND_LOCKED_M_R
309{
310    mfence
311    ldstl t1, seg, sib, disp
312    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
313    stul t1, seg, sib, disp
314    mfence
315};
316
317def macroop AND_LOCKED_P_R
318{
319    rdip t7
320    mfence
321    ldstl t1, seg, riprel, disp
322    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
323    stul t1, seg, riprel, disp
324    mfence
325};
326
327def macroop NOT_R
328{
329    limm t1, -1
330    xor reg, reg, t1
331};
332
333def macroop NOT_M
334{
335    limm t1, -1
336    ldst t2, seg, sib, disp
337    xor t2, t2, t1
338    st t2, seg, sib, disp
339};
340
341def macroop NOT_P
342{
343    limm t1, -1
344    rdip t7
345    ldst t2, seg, riprel, disp
346    xor t2, t2, t1
347    st t2, seg, riprel, disp
348};
349
350def macroop NOT_LOCKED_M
351{
352    limm t1, -1
353    mfence
354    ldstl t2, seg, sib, disp
355    xor t2, t2, t1
356    stul t2, seg, sib, disp
357    mfence
358};
359
360def macroop NOT_LOCKED_P
361{
362    limm t1, -1
363    rdip t7
364    mfence
365    ldstl t2, seg, riprel, disp
366    xor t2, t2, t1
367    stul t2, seg, riprel, disp
368    mfence
369};
370'''
371