xchg.py revision 6088
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IN NO EVENT SHALL THE COPYRIGHT 465081Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 475081Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 485081Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 495081Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 505081Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 515081Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 525081Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 535081Sgblack@eecs.umich.edu# 545081Sgblack@eecs.umich.edu# Authors: Gabe Black 555081Sgblack@eecs.umich.edu 565081Sgblack@eecs.umich.edumicrocode = ''' 575081Sgblack@eecs.umich.edu 585081Sgblack@eecs.umich.edu# All the memory versions need to use LOCK, regardless of if it was set 595081Sgblack@eecs.umich.edu 605081Sgblack@eecs.umich.edudef macroop XCHG_R_R 615081Sgblack@eecs.umich.edu{ 625081Sgblack@eecs.umich.edu # Use the xor trick instead of moves to reduce register pressure. 635081Sgblack@eecs.umich.edu # This probably doesn't make much of a difference, but it's easy. 645081Sgblack@eecs.umich.edu xor reg, reg, regm 655081Sgblack@eecs.umich.edu xor regm, regm, reg 665081Sgblack@eecs.umich.edu xor reg, reg, regm 675081Sgblack@eecs.umich.edu}; 685081Sgblack@eecs.umich.edu 695081Sgblack@eecs.umich.edudef macroop XCHG_R_M 705081Sgblack@eecs.umich.edu{ 715119Sgblack@eecs.umich.edu ldst t1, seg, sib, disp 725081Sgblack@eecs.umich.edu st reg, seg, sib, disp 735081Sgblack@eecs.umich.edu mov reg, reg, t1 745081Sgblack@eecs.umich.edu}; 755081Sgblack@eecs.umich.edu 765081Sgblack@eecs.umich.edudef macroop XCHG_R_P 775081Sgblack@eecs.umich.edu{ 785081Sgblack@eecs.umich.edu rdip t7 795119Sgblack@eecs.umich.edu ldst t1, seg, riprel, disp 805081Sgblack@eecs.umich.edu st reg, seg, riprel, disp 815081Sgblack@eecs.umich.edu mov reg, reg, t1 825081Sgblack@eecs.umich.edu}; 835081Sgblack@eecs.umich.edu 845081Sgblack@eecs.umich.edudef macroop XCHG_M_R 855081Sgblack@eecs.umich.edu{ 865119Sgblack@eecs.umich.edu ldst t1, seg, sib, disp 875081Sgblack@eecs.umich.edu st reg, seg, sib, disp 885081Sgblack@eecs.umich.edu mov reg, reg, t1 895081Sgblack@eecs.umich.edu}; 905081Sgblack@eecs.umich.edu 915081Sgblack@eecs.umich.edudef macroop XCHG_P_R 925081Sgblack@eecs.umich.edu{ 935081Sgblack@eecs.umich.edu rdip t7 945119Sgblack@eecs.umich.edu ldst t1, seg, riprel, disp 955081Sgblack@eecs.umich.edu st reg, seg, riprel, disp 965081Sgblack@eecs.umich.edu mov reg, reg, t1 975081Sgblack@eecs.umich.edu}; 986088Sgblack@eecs.umich.edu 996088Sgblack@eecs.umich.edudef macroop XCHG_LOCKED_M_R 1006088Sgblack@eecs.umich.edu{ 1016088Sgblack@eecs.umich.edu ldstl t1, seg, sib, disp 1026088Sgblack@eecs.umich.edu stul reg, seg, sib, disp 1036088Sgblack@eecs.umich.edu mov reg, reg, t1 1046088Sgblack@eecs.umich.edu}; 1056088Sgblack@eecs.umich.edu 1066088Sgblack@eecs.umich.edudef macroop XCHG_LOCKED_P_R 1076088Sgblack@eecs.umich.edu{ 1086088Sgblack@eecs.umich.edu rdip t7 1096088Sgblack@eecs.umich.edu ldstl t1, seg, riprel, disp 1106088Sgblack@eecs.umich.edu stul reg, seg, riprel, disp 1116088Sgblack@eecs.umich.edu mov reg, reg, t1 1126088Sgblack@eecs.umich.edu}; 1135081Sgblack@eecs.umich.edu''' 114