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8610:9bdd52a2214c |
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03-Nov-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
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7501:a75564db03c3 |
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21-Jul-2010 |
Tushar Krishna <Tushar.Krishna@amd.com> |
Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses
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7087:fb8d5786ff30 |
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24-May-2010 |
Nathan Binkert <nate@binkert.org> |
copyright: Change HP copyright on x86 code to be more friendly
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6088:c698cbf56cf1 |
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19-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Implement a locking version of XCHG.
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5119:a4469f2919f3 |
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03-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
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5081:2ccce8600a9d |
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19-Sep-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
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