interrupts.hh revision 6066
14120Sgblack@eecs.umich.edu/*
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544120Sgblack@eecs.umich.edu *
554120Sgblack@eecs.umich.edu * Authors: Gabe Black
564120Sgblack@eecs.umich.edu */
574120Sgblack@eecs.umich.edu
584120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_INTERRUPTS_HH__
594120Sgblack@eecs.umich.edu#define __ARCH_X86_INTERRUPTS_HH__
604120Sgblack@eecs.umich.edu
615647Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh"
625086Sgblack@eecs.umich.edu#include "arch/x86/faults.hh"
635655Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh"
645654Sgblack@eecs.umich.edu#include "base/bitfield.hh"
655086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
665648Sgblack@eecs.umich.edu#include "dev/io_device.hh"
675651Sgblack@eecs.umich.edu#include "dev/x86/intdev.hh"
685647Sgblack@eecs.umich.edu#include "params/X86LocalApic.hh"
695647Sgblack@eecs.umich.edu#include "sim/eventq.hh"
705647Sgblack@eecs.umich.edu
715647Sgblack@eecs.umich.educlass ThreadContext;
725810Sgblack@eecs.umich.educlass BaseCPU;
734120Sgblack@eecs.umich.edu
745704Snate@binkert.orgnamespace X86ISA {
755086Sgblack@eecs.umich.edu
765651Sgblack@eecs.umich.educlass Interrupts : public BasicPioDevice, IntDev
775086Sgblack@eecs.umich.edu{
785647Sgblack@eecs.umich.edu  protected:
795654Sgblack@eecs.umich.edu    // Storage for the APIC registers
805647Sgblack@eecs.umich.edu    uint32_t regs[NUM_APIC_REGS];
815654Sgblack@eecs.umich.edu
825691Sgblack@eecs.umich.edu    BitUnion32(LVTEntry)
835691Sgblack@eecs.umich.edu        Bitfield<7, 0> vector;
845691Sgblack@eecs.umich.edu        Bitfield<10, 8> deliveryMode;
855691Sgblack@eecs.umich.edu        Bitfield<12> status;
865691Sgblack@eecs.umich.edu        Bitfield<13> polarity;
875691Sgblack@eecs.umich.edu        Bitfield<14> remoteIRR;
885691Sgblack@eecs.umich.edu        Bitfield<15> trigger;
895691Sgblack@eecs.umich.edu        Bitfield<16> masked;
905691Sgblack@eecs.umich.edu        Bitfield<17> periodic;
915691Sgblack@eecs.umich.edu    EndBitUnion(LVTEntry)
925691Sgblack@eecs.umich.edu
935654Sgblack@eecs.umich.edu    /*
945654Sgblack@eecs.umich.edu     * Timing related stuff.
955654Sgblack@eecs.umich.edu     */
965648Sgblack@eecs.umich.edu    Tick latency;
975648Sgblack@eecs.umich.edu    Tick clock;
985647Sgblack@eecs.umich.edu
995647Sgblack@eecs.umich.edu    class ApicTimerEvent : public Event
1005647Sgblack@eecs.umich.edu    {
1015691Sgblack@eecs.umich.edu      private:
1025691Sgblack@eecs.umich.edu        Interrupts *localApic;
1035647Sgblack@eecs.umich.edu      public:
1045691Sgblack@eecs.umich.edu        ApicTimerEvent(Interrupts *_localApic) :
1055691Sgblack@eecs.umich.edu            Event(), localApic(_localApic)
1065647Sgblack@eecs.umich.edu        {}
1075647Sgblack@eecs.umich.edu
1085647Sgblack@eecs.umich.edu        void process()
1095647Sgblack@eecs.umich.edu        {
1105691Sgblack@eecs.umich.edu            assert(localApic);
1115691Sgblack@eecs.umich.edu            if (localApic->triggerTimerInterrupt()) {
1125691Sgblack@eecs.umich.edu                localApic->setReg(APIC_INITIAL_COUNT,
1135691Sgblack@eecs.umich.edu                        localApic->readReg(APIC_INITIAL_COUNT));
1145691Sgblack@eecs.umich.edu            }
1155647Sgblack@eecs.umich.edu        }
1165647Sgblack@eecs.umich.edu    };
1175647Sgblack@eecs.umich.edu
1185647Sgblack@eecs.umich.edu    ApicTimerEvent apicTimerEvent;
1195647Sgblack@eecs.umich.edu
1205654Sgblack@eecs.umich.edu    /*
1215655Sgblack@eecs.umich.edu     * A set of variables to keep track of interrupts that don't go through
1225655Sgblack@eecs.umich.edu     * the IRR.
1235655Sgblack@eecs.umich.edu     */
1245655Sgblack@eecs.umich.edu    bool pendingSmi;
1255691Sgblack@eecs.umich.edu    uint8_t smiVector;
1265655Sgblack@eecs.umich.edu    bool pendingNmi;
1275691Sgblack@eecs.umich.edu    uint8_t nmiVector;
1285655Sgblack@eecs.umich.edu    bool pendingExtInt;
1295691Sgblack@eecs.umich.edu    uint8_t extIntVector;
1305655Sgblack@eecs.umich.edu    bool pendingInit;
1315691Sgblack@eecs.umich.edu    uint8_t initVector;
1326050Sgblack@eecs.umich.edu    bool pendingStartup;
1336050Sgblack@eecs.umich.edu    uint8_t startupVector;
1346066Sgblack@eecs.umich.edu    bool startedUp;
1355655Sgblack@eecs.umich.edu
1365655Sgblack@eecs.umich.edu    // This is a quick check whether any of the above (except ExtInt) are set.
1375655Sgblack@eecs.umich.edu    bool pendingUnmaskableInt;
1385655Sgblack@eecs.umich.edu
1395655Sgblack@eecs.umich.edu    /*
1405654Sgblack@eecs.umich.edu     * IRR and ISR maintenance.
1415654Sgblack@eecs.umich.edu     */
1425654Sgblack@eecs.umich.edu    uint8_t IRRV;
1435654Sgblack@eecs.umich.edu    uint8_t ISRV;
1445654Sgblack@eecs.umich.edu
1455654Sgblack@eecs.umich.edu    int
1465654Sgblack@eecs.umich.edu    findRegArrayMSB(ApicRegIndex base)
1475654Sgblack@eecs.umich.edu    {
1485654Sgblack@eecs.umich.edu        int offset = 7;
1495654Sgblack@eecs.umich.edu        do {
1505654Sgblack@eecs.umich.edu            if (regs[base + offset] != 0) {
1515654Sgblack@eecs.umich.edu                return offset * 32 + findMsbSet(regs[base + offset]);
1525654Sgblack@eecs.umich.edu            }
1535654Sgblack@eecs.umich.edu        } while (offset--);
1545654Sgblack@eecs.umich.edu        return 0;
1555654Sgblack@eecs.umich.edu    }
1565654Sgblack@eecs.umich.edu
1575654Sgblack@eecs.umich.edu    void
1585654Sgblack@eecs.umich.edu    updateIRRV()
1595654Sgblack@eecs.umich.edu    {
1605654Sgblack@eecs.umich.edu        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
1615654Sgblack@eecs.umich.edu    }
1625654Sgblack@eecs.umich.edu
1635654Sgblack@eecs.umich.edu    void
1645654Sgblack@eecs.umich.edu    updateISRV()
1655654Sgblack@eecs.umich.edu    {
1665654Sgblack@eecs.umich.edu        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
1675654Sgblack@eecs.umich.edu    }
1685654Sgblack@eecs.umich.edu
1695654Sgblack@eecs.umich.edu    void
1705654Sgblack@eecs.umich.edu    setRegArrayBit(ApicRegIndex base, uint8_t vector)
1715654Sgblack@eecs.umich.edu    {
1725654Sgblack@eecs.umich.edu        regs[base + (vector % 32)] |= (1 << (vector >> 5));
1735654Sgblack@eecs.umich.edu    }
1745654Sgblack@eecs.umich.edu
1755654Sgblack@eecs.umich.edu    void
1765654Sgblack@eecs.umich.edu    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
1775654Sgblack@eecs.umich.edu    {
1785654Sgblack@eecs.umich.edu        regs[base + (vector % 32)] &= ~(1 << (vector >> 5));
1795654Sgblack@eecs.umich.edu    }
1805654Sgblack@eecs.umich.edu
1815654Sgblack@eecs.umich.edu    bool
1825654Sgblack@eecs.umich.edu    getRegArrayBit(ApicRegIndex base, uint8_t vector)
1835654Sgblack@eecs.umich.edu    {
1845654Sgblack@eecs.umich.edu        return bits(regs[base + (vector % 32)], vector >> 5);
1855654Sgblack@eecs.umich.edu    }
1865654Sgblack@eecs.umich.edu
1875691Sgblack@eecs.umich.edu    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
1885691Sgblack@eecs.umich.edu
1895810Sgblack@eecs.umich.edu    BaseCPU *cpu;
1905810Sgblack@eecs.umich.edu
1915086Sgblack@eecs.umich.edu  public:
1925654Sgblack@eecs.umich.edu    /*
1935654Sgblack@eecs.umich.edu     * Params stuff.
1945654Sgblack@eecs.umich.edu     */
1955647Sgblack@eecs.umich.edu    typedef X86LocalApicParams Params;
1965647Sgblack@eecs.umich.edu
1976041Sgblack@eecs.umich.edu    void setCPU(BaseCPU * newCPU);
1985810Sgblack@eecs.umich.edu
1995810Sgblack@eecs.umich.edu    void
2005704Snate@binkert.org    setClock(Tick newClock)
2015648Sgblack@eecs.umich.edu    {
2025648Sgblack@eecs.umich.edu        clock = newClock;
2035648Sgblack@eecs.umich.edu    }
2045648Sgblack@eecs.umich.edu
2055647Sgblack@eecs.umich.edu    const Params *
2065647Sgblack@eecs.umich.edu    params() const
2075086Sgblack@eecs.umich.edu    {
2085647Sgblack@eecs.umich.edu        return dynamic_cast<const Params *>(_params);
2095647Sgblack@eecs.umich.edu    }
2105647Sgblack@eecs.umich.edu
2115654Sgblack@eecs.umich.edu    /*
2125654Sgblack@eecs.umich.edu     * Functions to interact with the interrupt port from IntDev.
2135654Sgblack@eecs.umich.edu     */
2145648Sgblack@eecs.umich.edu    Tick read(PacketPtr pkt);
2155648Sgblack@eecs.umich.edu    Tick write(PacketPtr pkt);
2165651Sgblack@eecs.umich.edu    Tick recvMessage(PacketPtr pkt);
2176064Sgblack@eecs.umich.edu    Tick recvResponse(PacketPtr pkt);
2185647Sgblack@eecs.umich.edu
2195691Sgblack@eecs.umich.edu    bool
2205691Sgblack@eecs.umich.edu    triggerTimerInterrupt()
2215691Sgblack@eecs.umich.edu    {
2225691Sgblack@eecs.umich.edu        LVTEntry entry = regs[APIC_LVT_TIMER];
2235691Sgblack@eecs.umich.edu        if (!entry.masked)
2245691Sgblack@eecs.umich.edu            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
2255691Sgblack@eecs.umich.edu        return entry.periodic;
2265691Sgblack@eecs.umich.edu    }
2275691Sgblack@eecs.umich.edu
2286041Sgblack@eecs.umich.edu    void addressRanges(AddrRangeList &range_list);
2296041Sgblack@eecs.umich.edu    void getIntAddrRange(AddrRangeList &range_list);
2305651Sgblack@eecs.umich.edu
2315654Sgblack@eecs.umich.edu    Port *getPort(const std::string &if_name, int idx = -1)
2325654Sgblack@eecs.umich.edu    {
2335654Sgblack@eecs.umich.edu        if (if_name == "int_port")
2345654Sgblack@eecs.umich.edu            return intPort;
2355654Sgblack@eecs.umich.edu        return BasicPioDevice::getPort(if_name, idx);
2365654Sgblack@eecs.umich.edu    }
2375654Sgblack@eecs.umich.edu
2385654Sgblack@eecs.umich.edu    /*
2395654Sgblack@eecs.umich.edu     * Functions to access and manipulate the APIC's registers.
2405654Sgblack@eecs.umich.edu     */
2415654Sgblack@eecs.umich.edu
2425648Sgblack@eecs.umich.edu    uint32_t readReg(ApicRegIndex miscReg);
2435648Sgblack@eecs.umich.edu    void setReg(ApicRegIndex reg, uint32_t val);
2445704Snate@binkert.org    void
2455704Snate@binkert.org    setRegNoEffect(ApicRegIndex reg, uint32_t val)
2465647Sgblack@eecs.umich.edu    {
2475648Sgblack@eecs.umich.edu        regs[reg] = val;
2485648Sgblack@eecs.umich.edu    }
2495648Sgblack@eecs.umich.edu
2505654Sgblack@eecs.umich.edu    /*
2515654Sgblack@eecs.umich.edu     * Constructor.
2525654Sgblack@eecs.umich.edu     */
2535654Sgblack@eecs.umich.edu
2546041Sgblack@eecs.umich.edu    Interrupts(Params * p);
2555086Sgblack@eecs.umich.edu
2565654Sgblack@eecs.umich.edu    /*
2575654Sgblack@eecs.umich.edu     * Functions for retrieving interrupts for the CPU to handle.
2585654Sgblack@eecs.umich.edu     */
2595651Sgblack@eecs.umich.edu
2605704Snate@binkert.org    bool checkInterrupts(ThreadContext *tc) const;
2615704Snate@binkert.org    Fault getInterrupt(ThreadContext *tc);
2625704Snate@binkert.org    void updateIntrInfo(ThreadContext *tc);
2635086Sgblack@eecs.umich.edu
2645654Sgblack@eecs.umich.edu    /*
2655654Sgblack@eecs.umich.edu     * Serialization.
2665654Sgblack@eecs.umich.edu     */
2675086Sgblack@eecs.umich.edu
2685704Snate@binkert.org    void
2695704Snate@binkert.org    serialize(std::ostream &os)
2705086Sgblack@eecs.umich.edu    {
2715133Sgblack@eecs.umich.edu        panic("Interrupts::serialize unimplemented!\n");
2725086Sgblack@eecs.umich.edu    }
2735086Sgblack@eecs.umich.edu
2745704Snate@binkert.org    void
2755704Snate@binkert.org    unserialize(Checkpoint *cp, const std::string &section)
2765086Sgblack@eecs.umich.edu    {
2775133Sgblack@eecs.umich.edu        panic("Interrupts::unserialize unimplemented!\n");
2785086Sgblack@eecs.umich.edu    }
2795654Sgblack@eecs.umich.edu
2805654Sgblack@eecs.umich.edu    /*
2815654Sgblack@eecs.umich.edu     * Old functions needed for compatability but which will be phased out
2825654Sgblack@eecs.umich.edu     * eventually.
2835654Sgblack@eecs.umich.edu     */
2845704Snate@binkert.org    void
2855704Snate@binkert.org    post(int int_num, int index)
2865654Sgblack@eecs.umich.edu    {
2875654Sgblack@eecs.umich.edu        panic("Interrupts::post unimplemented!\n");
2885654Sgblack@eecs.umich.edu    }
2895654Sgblack@eecs.umich.edu
2905704Snate@binkert.org    void
2915704Snate@binkert.org    clear(int int_num, int index)
2925654Sgblack@eecs.umich.edu    {
2935654Sgblack@eecs.umich.edu        panic("Interrupts::clear unimplemented!\n");
2945654Sgblack@eecs.umich.edu    }
2955654Sgblack@eecs.umich.edu
2965704Snate@binkert.org    void
2975704Snate@binkert.org    clearAll()
2985654Sgblack@eecs.umich.edu    {
2995704Snate@binkert.org        panic("Interrupts::clearAll unimplemented!\n");
3005654Sgblack@eecs.umich.edu    }
3015086Sgblack@eecs.umich.edu};
3025086Sgblack@eecs.umich.edu
3035704Snate@binkert.org} // namespace X86ISA
3044120Sgblack@eecs.umich.edu
3054120Sgblack@eecs.umich.edu#endif // __ARCH_X86_INTERRUPTS_HH__
306