interrupts.hh revision 6066 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
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10 * use which is NOT directed to receiving any direct monetary
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12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
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24 *     Palo Alto, California  94304
25 *
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27 * this list of conditions and the following disclaimer.  Redistributions
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34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
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39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_INTERRUPTS_HH__
59#define __ARCH_X86_INTERRUPTS_HH__
60
61#include "arch/x86/apicregs.hh"
62#include "arch/x86/faults.hh"
63#include "arch/x86/intmessage.hh"
64#include "base/bitfield.hh"
65#include "cpu/thread_context.hh"
66#include "dev/io_device.hh"
67#include "dev/x86/intdev.hh"
68#include "params/X86LocalApic.hh"
69#include "sim/eventq.hh"
70
71class ThreadContext;
72class BaseCPU;
73
74namespace X86ISA {
75
76class Interrupts : public BasicPioDevice, IntDev
77{
78  protected:
79    // Storage for the APIC registers
80    uint32_t regs[NUM_APIC_REGS];
81
82    BitUnion32(LVTEntry)
83        Bitfield<7, 0> vector;
84        Bitfield<10, 8> deliveryMode;
85        Bitfield<12> status;
86        Bitfield<13> polarity;
87        Bitfield<14> remoteIRR;
88        Bitfield<15> trigger;
89        Bitfield<16> masked;
90        Bitfield<17> periodic;
91    EndBitUnion(LVTEntry)
92
93    /*
94     * Timing related stuff.
95     */
96    Tick latency;
97    Tick clock;
98
99    class ApicTimerEvent : public Event
100    {
101      private:
102        Interrupts *localApic;
103      public:
104        ApicTimerEvent(Interrupts *_localApic) :
105            Event(), localApic(_localApic)
106        {}
107
108        void process()
109        {
110            assert(localApic);
111            if (localApic->triggerTimerInterrupt()) {
112                localApic->setReg(APIC_INITIAL_COUNT,
113                        localApic->readReg(APIC_INITIAL_COUNT));
114            }
115        }
116    };
117
118    ApicTimerEvent apicTimerEvent;
119
120    /*
121     * A set of variables to keep track of interrupts that don't go through
122     * the IRR.
123     */
124    bool pendingSmi;
125    uint8_t smiVector;
126    bool pendingNmi;
127    uint8_t nmiVector;
128    bool pendingExtInt;
129    uint8_t extIntVector;
130    bool pendingInit;
131    uint8_t initVector;
132    bool pendingStartup;
133    uint8_t startupVector;
134    bool startedUp;
135
136    // This is a quick check whether any of the above (except ExtInt) are set.
137    bool pendingUnmaskableInt;
138
139    /*
140     * IRR and ISR maintenance.
141     */
142    uint8_t IRRV;
143    uint8_t ISRV;
144
145    int
146    findRegArrayMSB(ApicRegIndex base)
147    {
148        int offset = 7;
149        do {
150            if (regs[base + offset] != 0) {
151                return offset * 32 + findMsbSet(regs[base + offset]);
152            }
153        } while (offset--);
154        return 0;
155    }
156
157    void
158    updateIRRV()
159    {
160        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
161    }
162
163    void
164    updateISRV()
165    {
166        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
167    }
168
169    void
170    setRegArrayBit(ApicRegIndex base, uint8_t vector)
171    {
172        regs[base + (vector % 32)] |= (1 << (vector >> 5));
173    }
174
175    void
176    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
177    {
178        regs[base + (vector % 32)] &= ~(1 << (vector >> 5));
179    }
180
181    bool
182    getRegArrayBit(ApicRegIndex base, uint8_t vector)
183    {
184        return bits(regs[base + (vector % 32)], vector >> 5);
185    }
186
187    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
188
189    BaseCPU *cpu;
190
191  public:
192    /*
193     * Params stuff.
194     */
195    typedef X86LocalApicParams Params;
196
197    void setCPU(BaseCPU * newCPU);
198
199    void
200    setClock(Tick newClock)
201    {
202        clock = newClock;
203    }
204
205    const Params *
206    params() const
207    {
208        return dynamic_cast<const Params *>(_params);
209    }
210
211    /*
212     * Functions to interact with the interrupt port from IntDev.
213     */
214    Tick read(PacketPtr pkt);
215    Tick write(PacketPtr pkt);
216    Tick recvMessage(PacketPtr pkt);
217    Tick recvResponse(PacketPtr pkt);
218
219    bool
220    triggerTimerInterrupt()
221    {
222        LVTEntry entry = regs[APIC_LVT_TIMER];
223        if (!entry.masked)
224            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
225        return entry.periodic;
226    }
227
228    void addressRanges(AddrRangeList &range_list);
229    void getIntAddrRange(AddrRangeList &range_list);
230
231    Port *getPort(const std::string &if_name, int idx = -1)
232    {
233        if (if_name == "int_port")
234            return intPort;
235        return BasicPioDevice::getPort(if_name, idx);
236    }
237
238    /*
239     * Functions to access and manipulate the APIC's registers.
240     */
241
242    uint32_t readReg(ApicRegIndex miscReg);
243    void setReg(ApicRegIndex reg, uint32_t val);
244    void
245    setRegNoEffect(ApicRegIndex reg, uint32_t val)
246    {
247        regs[reg] = val;
248    }
249
250    /*
251     * Constructor.
252     */
253
254    Interrupts(Params * p);
255
256    /*
257     * Functions for retrieving interrupts for the CPU to handle.
258     */
259
260    bool checkInterrupts(ThreadContext *tc) const;
261    Fault getInterrupt(ThreadContext *tc);
262    void updateIntrInfo(ThreadContext *tc);
263
264    /*
265     * Serialization.
266     */
267
268    void
269    serialize(std::ostream &os)
270    {
271        panic("Interrupts::serialize unimplemented!\n");
272    }
273
274    void
275    unserialize(Checkpoint *cp, const std::string &section)
276    {
277        panic("Interrupts::unserialize unimplemented!\n");
278    }
279
280    /*
281     * Old functions needed for compatability but which will be phased out
282     * eventually.
283     */
284    void
285    post(int int_num, int index)
286    {
287        panic("Interrupts::post unimplemented!\n");
288    }
289
290    void
291    clear(int int_num, int index)
292    {
293        panic("Interrupts::clear unimplemented!\n");
294    }
295
296    void
297    clearAll()
298    {
299        panic("Interrupts::clearAll unimplemented!\n");
300    }
301};
302
303} // namespace X86ISA
304
305#endif // __ARCH_X86_INTERRUPTS_HH__
306