faults.hh revision 5684 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
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35 * output created using the software may be prepared, but only for
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39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_FAULTS_HH__
59#define __ARCH_X86_FAULTS_HH__
60
61#include "base/misc.hh"
62#include "sim/faults.hh"
63
64namespace X86ISA
65{
66    // Base class for all x86 "faults" where faults is in the m5 sense
67    class X86FaultBase : public FaultBase
68    {
69      protected:
70        const char * faultName;
71        const char * mnem;
72        uint64_t errorCode;
73
74        X86FaultBase(const char * _faultName, const char * _mnem,
75                uint64_t _errorCode = 0) :
76            faultName(_faultName), mnem(_mnem), errorCode(_errorCode)
77        {
78        }
79
80        const char * name() const
81        {
82            return faultName;
83        }
84
85        virtual bool isBenign()
86        {
87            return true;
88        }
89
90        virtual const char * mnemonic() const
91        {
92            return mnem;
93        }
94
95        void
96        invoke(ThreadContext * tc)
97        {
98            panic("Unimplemented fault %s.\n", name());
99        }
100    };
101
102    // Base class for x86 faults which behave as if the underlying instruction
103    // didn't happen.
104    class X86Fault : public X86FaultBase
105    {
106      protected:
107        X86Fault(const char * name, const char * mnem,
108                uint64_t _errorCode = 0) :
109            X86FaultBase(name, mnem, _errorCode)
110        {}
111    };
112
113    // Base class for x86 traps which behave as if the underlying instruction
114    // completed.
115    class X86Trap : public X86FaultBase
116    {
117      protected:
118        X86Trap(const char * name, const char * mnem,
119                uint64_t _errorCode = 0) :
120            X86FaultBase(name, mnem, _errorCode)
121        {}
122
123#if FULL_SYSTEM
124        void invoke(ThreadContext * tc);
125#endif
126    };
127
128    // Base class for x86 aborts which seem to be catastrophic failures.
129    class X86Abort : public X86FaultBase
130    {
131      protected:
132        X86Abort(const char * name, const char * mnem,
133                uint64_t _errorCode = 0) :
134            X86FaultBase(name, mnem, _errorCode)
135        {}
136
137#if FULL_SYSTEM
138        void invoke(ThreadContext * tc);
139#endif
140    };
141
142    // Base class for x86 interrupts.
143    class X86Interrupt : public X86FaultBase
144    {
145      protected:
146        uint8_t vector;
147        X86Interrupt(const char * name, const char * mnem, uint8_t _vector,
148                uint64_t _errorCode = 0) :
149            X86FaultBase(name, mnem, _errorCode), vector(_vector)
150        {}
151
152#if FULL_SYSTEM
153        void invoke(ThreadContext * tc);
154#endif
155    };
156
157    class UnimpInstFault : public FaultBase
158    {
159      public:
160        const char * name() const
161        {
162            return "unimplemented_micro";
163        }
164
165        void invoke(ThreadContext * tc)
166        {
167            panic("Unimplemented instruction!");
168        }
169    };
170
171    static inline Fault genMachineCheckFault()
172    {
173        panic("Machine check fault not implemented in x86!\n");
174    }
175
176    // Below is a summary of the interrupt/exception information in the
177    // architecture manuals.
178
179    // Class  |  Type    | vector |               Cause                 | mnem
180    //------------------------------------------------------------------------
181    //Contrib   Fault     0         Divide-by-Zero-Error                  #DE
182    //Benign    Either    1         Debug                                 #DB
183    //Benign    Interrupt 2         Non-Maskable-Interrupt                #NMI
184    //Benign    Trap      3         Breakpoint                            #BP
185    //Benign    Trap      4         Overflow                              #OF
186    //Benign    Fault     5         Bound-Range                           #BR
187    //Benign    Fault     6         Invalid-Opcode                        #UD
188    //Benign    Fault     7         Device-Not-Available                  #NM
189    //Benign    Abort     8         Double-Fault                          #DF
190    //                    9         Coprocessor-Segment-Overrun
191    //Contrib   Fault     10        Invalid-TSS                           #TS
192    //Contrib   Fault     11        Segment-Not-Present                   #NP
193    //Contrib   Fault     12        Stack                                 #SS
194    //Contrib   Fault     13        General-Protection                    #GP
195    //Either    Fault     14        Page-Fault                            #PF
196    //                    15        Reserved
197    //Benign    Fault     16        x87 Floating-Point Exception Pending  #MF
198    //Benign    Fault     17        Alignment-Check                       #AC
199    //Benign    Abort     18        Machine-Check                         #MC
200    //Benign    Fault     19        SIMD Floating-Point                   #XF
201    //                    20-29     Reserved
202    //Contrib   ?         30        Security Exception                    #SX
203    //                    31        Reserved
204    //Benign    Interrupt 0-255     External Interrupts                   #INTR
205    //Benign    Interrupt 0-255     Software Interrupts                   INTn
206
207    class DivideByZero : public X86Fault
208    {
209      public:
210        DivideByZero() :
211            X86Fault("Divide-by-Zero-Error", "#DE")
212        {}
213    };
214
215    class DebugException : public X86FaultBase
216    {
217      public:
218        DebugException() :
219            X86FaultBase("Debug", "#DB")
220        {}
221    };
222
223    class NonMaskableInterrupt : public X86Interrupt
224    {
225      public:
226        NonMaskableInterrupt(uint8_t _vector) :
227            X86Interrupt("Non Maskable Interrupt", "#NMI", _vector)
228        {}
229    };
230
231    class Breakpoint : public X86Trap
232    {
233      public:
234        Breakpoint() :
235            X86Trap("Breakpoint", "#BP")
236        {}
237    };
238
239    class OverflowTrap : public X86Trap
240    {
241      public:
242        OverflowTrap() :
243            X86Trap("Overflow", "#OF")
244        {}
245    };
246
247    class BoundRange : public X86Fault
248    {
249      public:
250        BoundRange() :
251            X86Fault("Bound-Range", "#BR")
252        {}
253    };
254
255    class InvalidOpcode : public X86Fault
256    {
257      public:
258        InvalidOpcode() :
259            X86Fault("Invalid-Opcode", "#UD")
260        {}
261    };
262
263    class DeviceNotAvailable : public X86Fault
264    {
265      public:
266        DeviceNotAvailable() :
267            X86Fault("Device-Not-Available", "#NM")
268        {}
269    };
270
271    class DoubleFault : public X86Abort
272    {
273      public:
274        DoubleFault() :
275            X86Abort("Double-Fault", "#DF")
276        {}
277    };
278
279    class InvalidTSS : public X86Fault
280    {
281      public:
282        InvalidTSS() :
283            X86Fault("Invalid-TSS", "#TS")
284        {}
285    };
286
287    class SegmentNotPresent : public X86Fault
288    {
289      public:
290        SegmentNotPresent() :
291            X86Fault("Segment-Not-Present", "#NP")
292        {}
293    };
294
295    class StackFault : public X86Fault
296    {
297      public:
298        StackFault() :
299            X86Fault("Stack", "#SS")
300        {}
301    };
302
303    class GeneralProtection : public X86Fault
304    {
305      public:
306        GeneralProtection(uint64_t _errorCode) :
307            X86Fault("General-Protection", "#GP", _errorCode)
308        {}
309    };
310
311    class PageFault : public X86Fault
312    {
313      public:
314        PageFault() :
315            X86Fault("Page-Fault", "#PF")
316        {}
317    };
318
319    class X87FpExceptionPending : public X86Fault
320    {
321      public:
322        X87FpExceptionPending() :
323            X86Fault("x87 Floating-Point Exception Pending", "#MF")
324        {}
325    };
326
327    class AlignmentCheck : public X86Fault
328    {
329      public:
330        AlignmentCheck() :
331            X86Fault("Alignment-Check", "#AC")
332        {}
333    };
334
335    class MachineCheck : public X86Abort
336    {
337      public:
338        MachineCheck() :
339            X86Abort("Machine-Check", "#MC")
340        {}
341    };
342
343    class SIMDFloatingPointFault : public X86Fault
344    {
345      public:
346        SIMDFloatingPointFault() :
347            X86Fault("SIMD Floating-Point", "#XF")
348        {}
349    };
350
351    class SecurityException : public X86FaultBase
352    {
353      public:
354        SecurityException() :
355            X86FaultBase("Security Exception", "#SX")
356        {}
357    };
358
359    class ExternalInterrupt : public X86Interrupt
360    {
361      public:
362        ExternalInterrupt(uint8_t _vector) :
363            X86Interrupt("External Interrupt", "#INTR", _vector)
364        {}
365    };
366
367    class SystemManagementInterrupt : public X86Interrupt
368    {
369      public:
370        SystemManagementInterrupt() :
371            X86Interrupt("System Management Interrupt", "#SMI", 0)
372        {}
373    };
374
375    class InitInterrupt : public X86Interrupt
376    {
377        uint8_t vector;
378      public:
379        InitInterrupt(uint8_t _vector) :
380            X86Interrupt("INIT Interrupt", "#INIT", _vector)
381        {}
382    };
383
384    class SoftwareInterrupt : public X86Interrupt
385    {
386      public:
387        SoftwareInterrupt(uint8_t _vector) :
388            X86Interrupt("Software Interrupt", "INTn", _vector)
389        {}
390    };
391
392    // These faults aren't part of the ISA definition. They trigger filling
393    // the tlb on a miss and are to take the place of a hardware table walker.
394    class FakeITLBFault : public X86Fault
395    {
396      protected:
397        Addr vaddr;
398      public:
399        FakeITLBFault(Addr _vaddr) :
400            X86Fault("fake instruction tlb fault", "itlb"),
401            vaddr(_vaddr)
402        {}
403
404        void invoke(ThreadContext * tc);
405    };
406
407    class FakeDTLBFault : public X86Fault
408    {
409      protected:
410        Addr vaddr;
411      public:
412        FakeDTLBFault(Addr _vaddr) :
413            X86Fault("fake data tlb fault", "dtlb"),
414            vaddr(_vaddr)
415        {}
416
417        void invoke(ThreadContext * tc);
418    };
419};
420
421#endif // __ARCH_X86_FAULTS_HH__
422