intelmp.cc revision 5625:ea7d3676ac8d
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IN NO EVENT SHALL THE COPYRIGHT 4710449Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 4810449Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 4910449Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 5010449Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 5110449Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5210449Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 5310449Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5410449Snilay@cs.wisc.edu * 5510449Snilay@cs.wisc.edu * Authors: Gabe Black 5610449Snilay@cs.wisc.edu */ 5710449Snilay@cs.wisc.edu 5810449Snilay@cs.wisc.edu#include "arch/x86/bios/intelmp.hh" 5910449Snilay@cs.wisc.edu#include "arch/x86/isa_traits.hh" 6010449Snilay@cs.wisc.edu#include "base/misc.hh" 6110449Snilay@cs.wisc.edu#include "mem/port.hh" 6210449Snilay@cs.wisc.edu#include "sim/byteswap.hh" 6310449Snilay@cs.wisc.edu#include "sim/host.hh" 6410449Snilay@cs.wisc.edu 6510449Snilay@cs.wisc.edu// Config entry types 6610449Snilay@cs.wisc.edu#include "params/X86IntelMPBaseConfigEntry.hh" 6710449Snilay@cs.wisc.edu#include "params/X86IntelMPExtConfigEntry.hh" 6810449Snilay@cs.wisc.edu 6910449Snilay@cs.wisc.edu// General table structures 7010449Snilay@cs.wisc.edu#include "params/X86IntelMPConfigTable.hh" 7110449Snilay@cs.wisc.edu#include "params/X86IntelMPFloatingPointer.hh" 7210449Snilay@cs.wisc.edu 7310449Snilay@cs.wisc.edu// Base entry types 7410449Snilay@cs.wisc.edu#include "params/X86IntelMPBus.hh" 7510449Snilay@cs.wisc.edu#include "params/X86IntelMPIOAPIC.hh" 7610449Snilay@cs.wisc.edu#include "params/X86IntelMPIOIntAssignment.hh" 7710449Snilay@cs.wisc.edu#include "params/X86IntelMPLocalIntAssignment.hh" 7810449Snilay@cs.wisc.edu#include "params/X86IntelMPProcessor.hh" 7910449Snilay@cs.wisc.edu 8010449Snilay@cs.wisc.edu// Extended entry types 8110449Snilay@cs.wisc.edu#include "params/X86IntelMPAddrSpaceMapping.hh" 8210449Snilay@cs.wisc.edu#include "params/X86IntelMPBusHierarchy.hh" 8310449Snilay@cs.wisc.edu#include "params/X86IntelMPCompatAddrSpaceMod.hh" 8410449Snilay@cs.wisc.edu 8510449Snilay@cs.wisc.eduusing namespace std; 8610449Snilay@cs.wisc.edu 8710449Snilay@cs.wisc.educonst char X86ISA::IntelMP::FloatingPointer::signature[] = "_MP_"; 8810449Snilay@cs.wisc.edu 8910449Snilay@cs.wisc.edutemplate<class T> 9010449Snilay@cs.wisc.eduuint8_t 9110449Snilay@cs.wisc.eduwriteOutField(FunctionalPort * port, Addr addr, T val) 9210449Snilay@cs.wisc.edu{ 9310449Snilay@cs.wisc.edu T guestVal = X86ISA::htog(val); 9410449Snilay@cs.wisc.edu port->writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T)); 9510449Snilay@cs.wisc.edu 9610449Snilay@cs.wisc.edu uint8_t checkSum = 0; 9710449Snilay@cs.wisc.edu while(guestVal) { 9810449Snilay@cs.wisc.edu checkSum += guestVal; 9910449Snilay@cs.wisc.edu guestVal >>= 8; 10010449Snilay@cs.wisc.edu } 10110449Snilay@cs.wisc.edu return checkSum; 10210449Snilay@cs.wisc.edu} 10310449Snilay@cs.wisc.edu 10410449Snilay@cs.wisc.eduuint8_t 10510449Snilay@cs.wisc.eduwriteOutString(FunctionalPort * port, Addr addr, string str, int length) 10610449Snilay@cs.wisc.edu{ 10710449Snilay@cs.wisc.edu char cleanedString[length + 1]; 10810449Snilay@cs.wisc.edu cleanedString[length] = 0; 10910449Snilay@cs.wisc.edu 11010449Snilay@cs.wisc.edu if (str.length() > length) { 11110449Snilay@cs.wisc.edu memcpy(cleanedString, str.c_str(), length); 11210449Snilay@cs.wisc.edu warn("Intel MP configuration table string \"%s\" " 11310449Snilay@cs.wisc.edu "will be truncated to \"%s\".\n", str, cleanedString); 11410449Snilay@cs.wisc.edu } else { 11510449Snilay@cs.wisc.edu memcpy(cleanedString, str.c_str(), str.length()); 11610449Snilay@cs.wisc.edu memset(cleanedString + str.length(), 0, length - str.length()); 11710449Snilay@cs.wisc.edu } 11810449Snilay@cs.wisc.edu port->writeBlob(addr, (uint8_t *)(&cleanedString), length); 11910449Snilay@cs.wisc.edu 12010449Snilay@cs.wisc.edu uint8_t checkSum = 0; 12110449Snilay@cs.wisc.edu for (int i = 0; i < length; i++) 12210449Snilay@cs.wisc.edu checkSum += cleanedString[i]; 12310449Snilay@cs.wisc.edu 12410449Snilay@cs.wisc.edu return checkSum; 12510449Snilay@cs.wisc.edu} 12610449Snilay@cs.wisc.edu 12710449Snilay@cs.wisc.eduAddr 12810449Snilay@cs.wisc.eduX86ISA::IntelMP::FloatingPointer::writeOut(FunctionalPort * port, Addr addr) 12910449Snilay@cs.wisc.edu{ 13010449Snilay@cs.wisc.edu // Make sure that either a config table is present or a default 13110449Snilay@cs.wisc.edu // configuration was found but not both. 13210449Snilay@cs.wisc.edu if (!tableAddr && !defaultConfig) 13310449Snilay@cs.wisc.edu fatal("Either an MP configuration table or a default configuration " 13410449Snilay@cs.wisc.edu "must be used."); 13510449Snilay@cs.wisc.edu if (tableAddr && defaultConfig) 13610449Snilay@cs.wisc.edu fatal("Both an MP configuration table and a default configuration " 13710449Snilay@cs.wisc.edu "were set."); 13810449Snilay@cs.wisc.edu 13910449Snilay@cs.wisc.edu uint8_t checkSum = 0; 14010449Snilay@cs.wisc.edu 14110449Snilay@cs.wisc.edu port->writeBlob(addr, (uint8_t *)signature, 4); 14210449Snilay@cs.wisc.edu for (int i = 0; i < 4; i++) 14310449Snilay@cs.wisc.edu checkSum += signature[i]; 14410449Snilay@cs.wisc.edu 14510449Snilay@cs.wisc.edu checkSum += writeOutField(port, addr + 4, tableAddr); 14610449Snilay@cs.wisc.edu 14710449Snilay@cs.wisc.edu // The length of the structure in paragraphs, aka 16 byte chunks. 14810449Snilay@cs.wisc.edu uint8_t length = 1; 14910449Snilay@cs.wisc.edu port->writeBlob(addr + 8, &length, 1); 15010449Snilay@cs.wisc.edu checkSum += length; 15110449Snilay@cs.wisc.edu 15210449Snilay@cs.wisc.edu port->writeBlob(addr + 9, &specRev, 1); 15310449Snilay@cs.wisc.edu checkSum += specRev; 15410449Snilay@cs.wisc.edu 15510449Snilay@cs.wisc.edu port->writeBlob(addr + 11, &defaultConfig, 1); 15610449Snilay@cs.wisc.edu checkSum += defaultConfig; 15710449Snilay@cs.wisc.edu 15810449Snilay@cs.wisc.edu uint32_t features2_5 = imcrPresent ? (1 << 7) : 0; 15910449Snilay@cs.wisc.edu checkSum += writeOutField(port, addr + 12, features2_5); 16010449Snilay@cs.wisc.edu 16110449Snilay@cs.wisc.edu checkSum = -checkSum; 16210449Snilay@cs.wisc.edu port->writeBlob(addr + 10, &checkSum, 1); 16310449Snilay@cs.wisc.edu 16410449Snilay@cs.wisc.edu return 16; 16510449Snilay@cs.wisc.edu} 16610449Snilay@cs.wisc.edu 16710449Snilay@cs.wisc.eduX86ISA::IntelMP::FloatingPointer::FloatingPointer(Params * p) : 16810449Snilay@cs.wisc.edu SimObject(p), tableAddr(0), specRev(p->spec_rev), 16910449Snilay@cs.wisc.edu defaultConfig(p->default_config), imcrPresent(p->imcr_present) 17010449Snilay@cs.wisc.edu{} 17110449Snilay@cs.wisc.edu 17210449Snilay@cs.wisc.eduX86ISA::IntelMP::FloatingPointer * 17310449Snilay@cs.wisc.eduX86IntelMPFloatingPointerParams::create() 17410449Snilay@cs.wisc.edu{ 17510449Snilay@cs.wisc.edu return new X86ISA::IntelMP::FloatingPointer(this); 17610449Snilay@cs.wisc.edu} 17710449Snilay@cs.wisc.edu 17810449Snilay@cs.wisc.eduAddr 17910449Snilay@cs.wisc.eduX86ISA::IntelMP::BaseConfigEntry::writeOut(FunctionalPort * port, 18010449Snilay@cs.wisc.edu Addr addr, uint8_t &checkSum) 18110449Snilay@cs.wisc.edu{ 18210449Snilay@cs.wisc.edu port->writeBlob(addr, &type, 1); 18310449Snilay@cs.wisc.edu checkSum += type; 18410449Snilay@cs.wisc.edu return 1; 18510449Snilay@cs.wisc.edu} 18610449Snilay@cs.wisc.edu 18710449Snilay@cs.wisc.eduX86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(Params * p, uint8_t _type) : 18810449Snilay@cs.wisc.edu SimObject(p), type(_type) 18910449Snilay@cs.wisc.edu{} 19010449Snilay@cs.wisc.edu 19110449Snilay@cs.wisc.eduAddr 19210449Snilay@cs.wisc.eduX86ISA::IntelMP::ExtConfigEntry::writeOut(FunctionalPort * port, 19310449Snilay@cs.wisc.edu Addr addr, uint8_t &checkSum) 19410449Snilay@cs.wisc.edu{ 19510449Snilay@cs.wisc.edu port->writeBlob(addr, &type, 1); 19610449Snilay@cs.wisc.edu checkSum += type; 19710449Snilay@cs.wisc.edu port->writeBlob(addr + 1, &length, 1); 19810449Snilay@cs.wisc.edu checkSum += length; 19910449Snilay@cs.wisc.edu return 1; 20010449Snilay@cs.wisc.edu} 20110449Snilay@cs.wisc.edu 20210449Snilay@cs.wisc.eduX86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(Params * p, 20310449Snilay@cs.wisc.edu uint8_t _type, uint8_t _length) : 20410449Snilay@cs.wisc.edu SimObject(p), type(_type), length(_length) 20510449Snilay@cs.wisc.edu{} 20610449Snilay@cs.wisc.edu 20710449Snilay@cs.wisc.educonst char X86ISA::IntelMP::ConfigTable::signature[] = "PCMP"; 20810449Snilay@cs.wisc.edu 20910449Snilay@cs.wisc.eduAddr 21010449Snilay@cs.wisc.eduX86ISA::IntelMP::ConfigTable::writeOut(FunctionalPort * port, Addr addr) 21110449Snilay@cs.wisc.edu{ 21210449Snilay@cs.wisc.edu uint8_t checkSum = 0; 21310449Snilay@cs.wisc.edu 21410449Snilay@cs.wisc.edu port->writeBlob(addr, (uint8_t *)signature, 4); 21510449Snilay@cs.wisc.edu for (int i = 0; i < 4; i++) 21610449Snilay@cs.wisc.edu checkSum += signature[i]; 21710449Snilay@cs.wisc.edu 218 // Base table length goes here but will be calculated later. 219 220 port->writeBlob(addr + 6, (uint8_t *)(&specRev), 1); 221 checkSum += specRev; 222 223 // The checksum goes here but is still being calculated. 224 225 checkSum += writeOutString(port, addr + 8, oemID, 8); 226 checkSum += writeOutString(port, addr + 16, productID, 12); 227 228 checkSum += writeOutField(port, addr + 28, oemTableAddr); 229 checkSum += writeOutField(port, addr + 32, oemTableSize); 230 checkSum += writeOutField(port, addr + 34, (uint16_t)baseEntries.size()); 231 checkSum += writeOutField(port, addr + 36, localApic); 232 233 uint8_t reserved = 0; 234 port->writeBlob(addr + 43, &reserved, 1); 235 checkSum += reserved; 236 237 vector<BaseConfigEntry *>::iterator baseEnt; 238 uint16_t offset = 44; 239 for (baseEnt = baseEntries.begin(); 240 baseEnt != baseEntries.end(); baseEnt++) { 241 offset += (*baseEnt)->writeOut(port, addr + offset, checkSum); 242 } 243 244 // We've found the end of the base table this point. 245 checkSum += writeOutField(port, addr + 4, offset); 246 247 vector<ExtConfigEntry *>::iterator extEnt; 248 uint16_t extOffset = 0; 249 uint8_t extCheckSum = 0; 250 for (extEnt = extEntries.begin(); 251 extEnt != extEntries.end(); extEnt++) { 252 extOffset += (*extEnt)->writeOut(port, 253 addr + offset + extOffset, extCheckSum); 254 } 255 256 checkSum += writeOutField(port, addr + 40, extOffset); 257 extCheckSum = -extCheckSum; 258 checkSum += writeOutField(port, addr + 42, extCheckSum); 259 260 // And now, we finally have the whole check sum completed. 261 checkSum = -checkSum; 262 writeOutField(port, addr + 7, checkSum); 263 264 return offset + extOffset; 265}; 266 267X86ISA::IntelMP::ConfigTable::ConfigTable(Params * p) : SimObject(p), 268 specRev(p->spec_rev), oemID(p->oem_id), productID(p->product_id), 269 oemTableAddr(p->oem_table_addr), oemTableSize(p->oem_table_size), 270 localApic(p->local_apic), 271 baseEntries(p->base_entries), extEntries(p->ext_entries) 272{} 273 274X86ISA::IntelMP::ConfigTable * 275X86IntelMPConfigTableParams::create() 276{ 277 return new X86ISA::IntelMP::ConfigTable(this); 278} 279 280Addr 281X86ISA::IntelMP::Processor::writeOut( 282 FunctionalPort * port, Addr addr, uint8_t &checkSum) 283{ 284 BaseConfigEntry::writeOut(port, addr, checkSum); 285 checkSum += writeOutField(port, addr + 1, localApicID); 286 checkSum += writeOutField(port, addr + 2, localApicVersion); 287 checkSum += writeOutField(port, addr + 3, cpuFlags); 288 checkSum += writeOutField(port, addr + 4, cpuSignature); 289 checkSum += writeOutField(port, addr + 8, featureFlags); 290 291 uint32_t reserved = 0; 292 port->writeBlob(addr + 12, (uint8_t *)(&reserved), 4); 293 port->writeBlob(addr + 16, (uint8_t *)(&reserved), 4); 294 return 20; 295} 296 297X86ISA::IntelMP::Processor::Processor(Params * p) : BaseConfigEntry(p, 0), 298 localApicID(p->local_apic_id), localApicVersion(p->local_apic_version), 299 cpuFlags(0), cpuSignature(0), featureFlags(p->feature_flags) 300{ 301 if (p->enable) 302 cpuFlags |= (1 << 0); 303 if (p->bootstrap) 304 cpuFlags |= (1 << 1); 305 306 replaceBits(cpuSignature, 0, 3, p->stepping); 307 replaceBits(cpuSignature, 4, 7, p->model); 308 replaceBits(cpuSignature, 8, 11, p->family); 309} 310 311X86ISA::IntelMP::Processor * 312X86IntelMPProcessorParams::create() 313{ 314 return new X86ISA::IntelMP::Processor(this); 315} 316 317Addr 318X86ISA::IntelMP::Bus::writeOut( 319 FunctionalPort * port, Addr addr, uint8_t &checkSum) 320{ 321 BaseConfigEntry::writeOut(port, addr, checkSum); 322 checkSum += writeOutField(port, addr + 1, busID); 323 checkSum += writeOutString(port, addr + 2, busType, 6); 324 return 8; 325} 326 327X86ISA::IntelMP::Bus::Bus(Params * p) : BaseConfigEntry(p, 1), 328 busID(p->bus_id), busType(p->bus_type) 329{} 330 331X86ISA::IntelMP::Bus * 332X86IntelMPBusParams::create() 333{ 334 return new X86ISA::IntelMP::Bus(this); 335} 336 337Addr 338X86ISA::IntelMP::IOAPIC::writeOut( 339 FunctionalPort * port, Addr addr, uint8_t &checkSum) 340{ 341 BaseConfigEntry::writeOut(port, addr, checkSum); 342 checkSum += writeOutField(port, addr + 1, id); 343 checkSum += writeOutField(port, addr + 2, version); 344 checkSum += writeOutField(port, addr + 3, flags); 345 checkSum += writeOutField(port, addr + 4, address); 346 return 8; 347} 348 349X86ISA::IntelMP::IOAPIC::IOAPIC(Params * p) : BaseConfigEntry(p, 2), 350 id(p->id), version(p->version), flags(0), address(p->address) 351{ 352 if (p->enable) 353 flags |= 1; 354} 355 356X86ISA::IntelMP::IOAPIC * 357X86IntelMPIOAPICParams::create() 358{ 359 return new X86ISA::IntelMP::IOAPIC(this); 360} 361 362Addr 363X86ISA::IntelMP::IntAssignment::writeOut( 364 FunctionalPort * port, Addr addr, uint8_t &checkSum) 365{ 366 BaseConfigEntry::writeOut(port, addr, checkSum); 367 checkSum += writeOutField(port, addr + 1, interruptType); 368 checkSum += writeOutField(port, addr + 2, flags); 369 checkSum += writeOutField(port, addr + 4, sourceBusID); 370 checkSum += writeOutField(port, addr + 5, sourceBusIRQ); 371 checkSum += writeOutField(port, addr + 6, destApicID); 372 checkSum += writeOutField(port, addr + 7, destApicIntIn); 373 return 8; 374} 375 376X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(Params * p) : 377 IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 3, 378 p->source_bus_id, p->source_bus_irq, 379 p->dest_io_apic_id, p->dest_io_apic_intin) 380{} 381 382X86ISA::IntelMP::IOIntAssignment * 383X86IntelMPIOIntAssignmentParams::create() 384{ 385 return new X86ISA::IntelMP::IOIntAssignment(this); 386} 387 388X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(Params * p) : 389 IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 4, 390 p->source_bus_id, p->source_bus_irq, 391 p->dest_local_apic_id, p->dest_local_apic_intin) 392{} 393 394X86ISA::IntelMP::LocalIntAssignment * 395X86IntelMPLocalIntAssignmentParams::create() 396{ 397 return new X86ISA::IntelMP::LocalIntAssignment(this); 398} 399 400Addr 401X86ISA::IntelMP::AddrSpaceMapping::writeOut( 402 FunctionalPort * port, Addr addr, uint8_t &checkSum) 403{ 404 ExtConfigEntry::writeOut(port, addr, checkSum); 405 checkSum += writeOutField(port, addr + 2, busID); 406 checkSum += writeOutField(port, addr + 3, addrType); 407 checkSum += writeOutField(port, addr + 4, addr); 408 checkSum += writeOutField(port, addr + 12, addrLength); 409 return length; 410} 411 412X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(Params * p) : 413 ExtConfigEntry(p, 128, 20), 414 busID(p->bus_id), addrType(p->address_type), 415 addr(p->address), addrLength(p->length) 416{} 417 418X86ISA::IntelMP::AddrSpaceMapping * 419X86IntelMPAddrSpaceMappingParams::create() 420{ 421 return new X86ISA::IntelMP::AddrSpaceMapping(this); 422} 423 424Addr 425X86ISA::IntelMP::BusHierarchy::writeOut( 426 FunctionalPort * port, Addr addr, uint8_t &checkSum) 427{ 428 ExtConfigEntry::writeOut(port, addr, checkSum); 429 checkSum += writeOutField(port, addr + 2, busID); 430 checkSum += writeOutField(port, addr + 3, info); 431 checkSum += writeOutField(port, addr + 4, parentBus); 432 433 uint32_t reserved = 0; 434 port->writeBlob(addr + 5, (uint8_t *)(&reserved), 3); 435 436 return length; 437} 438 439X86ISA::IntelMP::BusHierarchy::BusHierarchy(Params * p) : 440 ExtConfigEntry(p, 129, 8), 441 busID(p->bus_id), info(0), parentBus(p->parent_bus) 442{ 443 if (p->subtractive_decode) 444 info |= 1; 445} 446 447X86ISA::IntelMP::BusHierarchy * 448X86IntelMPBusHierarchyParams::create() 449{ 450 return new X86ISA::IntelMP::BusHierarchy(this); 451} 452 453Addr 454X86ISA::IntelMP::CompatAddrSpaceMod::writeOut( 455 FunctionalPort * port, Addr addr, uint8_t &checkSum) 456{ 457 ExtConfigEntry::writeOut(port, addr, checkSum); 458 checkSum += writeOutField(port, addr + 2, busID); 459 checkSum += writeOutField(port, addr + 3, mod); 460 checkSum += writeOutField(port, addr + 4, rangeList); 461 return length; 462} 463 464X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(Params * p) : 465 ExtConfigEntry(p, 130, 8), 466 busID(p->bus_id), mod(0), rangeList(p->range_list) 467{ 468 if (p->add) 469 mod |= 1; 470} 471 472X86ISA::IntelMP::CompatAddrSpaceMod * 473X86IntelMPCompatAddrSpaceModParams::create() 474{ 475 return new X86ISA::IntelMP::CompatAddrSpaceMod(this); 476} 477