intelmp.cc revision 11793
15222Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35254Sksewell@umich.edu * All rights reserved. 45254Sksewell@umich.edu * 55222Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65254Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75254Sksewell@umich.edu * property including but not limited to intellectual property relating 85254Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95254Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105254Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115254Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125254Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135254Sksewell@umich.edu * 145254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 155254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 165222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 175254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 185254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 195254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 205254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 215254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 225254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 235254Sksewell@umich.edu * this software without specific prior written permission. 245254Sksewell@umich.edu * 255254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365222Sksewell@umich.edu * 375222Sksewell@umich.edu * Authors: Gabe Black 385222Sksewell@umich.edu */ 395222Sksewell@umich.edu 405222Sksewell@umich.edu#include "arch/x86/bios/intelmp.hh" 415222Sksewell@umich.edu 425222Sksewell@umich.edu#include "arch/x86/isa_traits.hh" 435222Sksewell@umich.edu#include "base/misc.hh" 445222Sksewell@umich.edu#include "base/types.hh" 455222Sksewell@umich.edu#include "mem/port_proxy.hh" 465222Sksewell@umich.edu#include "sim/byteswap.hh" 475222Sksewell@umich.edu 485222Sksewell@umich.edu// Config entry types 495222Sksewell@umich.edu#include "params/X86IntelMPBaseConfigEntry.hh" 505222Sksewell@umich.edu#include "params/X86IntelMPExtConfigEntry.hh" 515222Sksewell@umich.edu 525222Sksewell@umich.edu// General table structures 535222Sksewell@umich.edu#include "params/X86IntelMPConfigTable.hh" 545222Sksewell@umich.edu#include "params/X86IntelMPFloatingPointer.hh" 555222Sksewell@umich.edu 565222Sksewell@umich.edu// Base entry types 575222Sksewell@umich.edu#include "params/X86IntelMPBus.hh" 585222Sksewell@umich.edu#include "params/X86IntelMPIOAPIC.hh" 595222Sksewell@umich.edu#include "params/X86IntelMPIOIntAssignment.hh" 605222Sksewell@umich.edu#include "params/X86IntelMPLocalIntAssignment.hh" 615222Sksewell@umich.edu#include "params/X86IntelMPProcessor.hh" 625222Sksewell@umich.edu 635222Sksewell@umich.edu// Extended entry types 645222Sksewell@umich.edu#include "params/X86IntelMPAddrSpaceMapping.hh" 655222Sksewell@umich.edu#include "params/X86IntelMPBusHierarchy.hh" 665222Sksewell@umich.edu#include "params/X86IntelMPCompatAddrSpaceMod.hh" 675222Sksewell@umich.edu 685222Sksewell@umich.eduusing namespace std; 695222Sksewell@umich.edu 705222Sksewell@umich.educonst char X86ISA::IntelMP::FloatingPointer::signature[] = "_MP_"; 715222Sksewell@umich.edu 725222Sksewell@umich.edutemplate<class T> 735222Sksewell@umich.eduuint8_t 745222Sksewell@umich.eduwriteOutField(PortProxy& proxy, Addr addr, T val) 755222Sksewell@umich.edu{ 765222Sksewell@umich.edu uint64_t guestVal = X86ISA::htog(val); 775222Sksewell@umich.edu proxy.writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T)); 785222Sksewell@umich.edu 795222Sksewell@umich.edu uint8_t checkSum = 0; 805222Sksewell@umich.edu while (guestVal) { 815222Sksewell@umich.edu checkSum += guestVal; 825222Sksewell@umich.edu guestVal >>= 8; 835222Sksewell@umich.edu } 845222Sksewell@umich.edu return checkSum; 855222Sksewell@umich.edu} 865222Sksewell@umich.edu 875222Sksewell@umich.eduuint8_t 885222Sksewell@umich.eduwriteOutString(PortProxy& proxy, Addr addr, string str, int length) 895222Sksewell@umich.edu{ 905222Sksewell@umich.edu char cleanedString[length + 1]; 915222Sksewell@umich.edu cleanedString[length] = 0; 925222Sksewell@umich.edu 935222Sksewell@umich.edu if (str.length() > length) { 945222Sksewell@umich.edu memcpy(cleanedString, str.c_str(), length); 955222Sksewell@umich.edu warn("Intel MP configuration table string \"%s\" " 965222Sksewell@umich.edu "will be truncated to \"%s\".\n", str, (char *)&cleanedString); 975222Sksewell@umich.edu } else { 985222Sksewell@umich.edu memcpy(cleanedString, str.c_str(), str.length()); 995222Sksewell@umich.edu memset(cleanedString + str.length(), 0, length - str.length()); 1005222Sksewell@umich.edu } 1015222Sksewell@umich.edu proxy.writeBlob(addr, (uint8_t *)(&cleanedString), length); 1025222Sksewell@umich.edu 1035222Sksewell@umich.edu uint8_t checkSum = 0; 1045222Sksewell@umich.edu for (int i = 0; i < length; i++) 1055222Sksewell@umich.edu checkSum += cleanedString[i]; 1065222Sksewell@umich.edu 1075222Sksewell@umich.edu return checkSum; 1085222Sksewell@umich.edu} 1095222Sksewell@umich.edu 1105222Sksewell@umich.eduAddr 1115222Sksewell@umich.eduX86ISA::IntelMP::FloatingPointer::writeOut(PortProxy& proxy, Addr addr) 1125222Sksewell@umich.edu{ 1135222Sksewell@umich.edu // Make sure that either a config table is present or a default 1145222Sksewell@umich.edu // configuration was found but not both. 1155222Sksewell@umich.edu if (!tableAddr && !defaultConfig) 1165222Sksewell@umich.edu fatal("Either an MP configuration table or a default configuration " 1175222Sksewell@umich.edu "must be used."); 1185222Sksewell@umich.edu if (tableAddr && defaultConfig) 1195222Sksewell@umich.edu fatal("Both an MP configuration table and a default configuration " 1205222Sksewell@umich.edu "were set."); 1215222Sksewell@umich.edu 1225222Sksewell@umich.edu uint8_t checkSum = 0; 1235222Sksewell@umich.edu 1245222Sksewell@umich.edu proxy.writeBlob(addr, (uint8_t *)signature, 4); 1255222Sksewell@umich.edu for (int i = 0; i < 4; i++) 1265222Sksewell@umich.edu checkSum += signature[i]; 1275222Sksewell@umich.edu 1285222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 4, tableAddr); 1295222Sksewell@umich.edu 1305222Sksewell@umich.edu // The length of the structure in paragraphs, aka 16 byte chunks. 1315222Sksewell@umich.edu uint8_t length = 1; 1325222Sksewell@umich.edu proxy.writeBlob(addr + 8, &length, 1); 1335222Sksewell@umich.edu checkSum += length; 1345222Sksewell@umich.edu 1355222Sksewell@umich.edu proxy.writeBlob(addr + 9, &specRev, 1); 1365222Sksewell@umich.edu checkSum += specRev; 1375222Sksewell@umich.edu 1385222Sksewell@umich.edu proxy.writeBlob(addr + 11, &defaultConfig, 1); 1395222Sksewell@umich.edu checkSum += defaultConfig; 1405222Sksewell@umich.edu 1415222Sksewell@umich.edu uint32_t features2_5 = imcrPresent ? (1 << 7) : 0; 1425222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 12, features2_5); 1435222Sksewell@umich.edu 1445222Sksewell@umich.edu checkSum = -checkSum; 1455222Sksewell@umich.edu proxy.writeBlob(addr + 10, &checkSum, 1); 1465222Sksewell@umich.edu 1475222Sksewell@umich.edu return 16; 1485222Sksewell@umich.edu} 1495222Sksewell@umich.edu 1505222Sksewell@umich.eduX86ISA::IntelMP::FloatingPointer::FloatingPointer(Params * p) : 1515222Sksewell@umich.edu SimObject(p), tableAddr(0), specRev(p->spec_rev), 1525222Sksewell@umich.edu defaultConfig(p->default_config), imcrPresent(p->imcr_present) 1535222Sksewell@umich.edu{} 1545222Sksewell@umich.edu 1555222Sksewell@umich.eduX86ISA::IntelMP::FloatingPointer * 1565222Sksewell@umich.eduX86IntelMPFloatingPointerParams::create() 1575222Sksewell@umich.edu{ 1585222Sksewell@umich.edu return new X86ISA::IntelMP::FloatingPointer(this); 1595222Sksewell@umich.edu} 1605222Sksewell@umich.edu 1615222Sksewell@umich.eduAddr 1625222Sksewell@umich.eduX86ISA::IntelMP::BaseConfigEntry::writeOut(PortProxy& proxy, 1635222Sksewell@umich.edu Addr addr, uint8_t &checkSum) 1645222Sksewell@umich.edu{ 1655222Sksewell@umich.edu proxy.writeBlob(addr, &type, 1); 1665222Sksewell@umich.edu checkSum += type; 1675222Sksewell@umich.edu return 1; 1685222Sksewell@umich.edu} 1695222Sksewell@umich.edu 1705222Sksewell@umich.eduX86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(Params * p, uint8_t _type) : 1715222Sksewell@umich.edu SimObject(p), type(_type) 1725222Sksewell@umich.edu{} 1735222Sksewell@umich.edu 1745222Sksewell@umich.eduAddr 1755222Sksewell@umich.eduX86ISA::IntelMP::ExtConfigEntry::writeOut(PortProxy& proxy, 1765222Sksewell@umich.edu Addr addr, uint8_t &checkSum) 1775222Sksewell@umich.edu{ 1785222Sksewell@umich.edu proxy.writeBlob(addr, &type, 1); 1795222Sksewell@umich.edu checkSum += type; 1805222Sksewell@umich.edu proxy.writeBlob(addr + 1, &length, 1); 1815222Sksewell@umich.edu checkSum += length; 1825222Sksewell@umich.edu return 1; 1835222Sksewell@umich.edu} 1845222Sksewell@umich.edu 1855222Sksewell@umich.eduX86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(Params * p, 1865222Sksewell@umich.edu uint8_t _type, uint8_t _length) : 1875222Sksewell@umich.edu SimObject(p), type(_type), length(_length) 1885222Sksewell@umich.edu{} 1895222Sksewell@umich.edu 1905222Sksewell@umich.educonst char X86ISA::IntelMP::ConfigTable::signature[] = "PCMP"; 1915222Sksewell@umich.edu 1925222Sksewell@umich.eduAddr 1935222Sksewell@umich.eduX86ISA::IntelMP::ConfigTable::writeOut(PortProxy& proxy, Addr addr) 1945222Sksewell@umich.edu{ 1955222Sksewell@umich.edu uint8_t checkSum = 0; 1965222Sksewell@umich.edu 1975222Sksewell@umich.edu proxy.writeBlob(addr, (uint8_t *)signature, 4); 1985222Sksewell@umich.edu for (int i = 0; i < 4; i++) 1995222Sksewell@umich.edu checkSum += signature[i]; 2005222Sksewell@umich.edu 2015222Sksewell@umich.edu // Base table length goes here but will be calculated later. 2025222Sksewell@umich.edu 2035222Sksewell@umich.edu proxy.writeBlob(addr + 6, (uint8_t *)(&specRev), 1); 2045222Sksewell@umich.edu checkSum += specRev; 2055222Sksewell@umich.edu 2065222Sksewell@umich.edu // The checksum goes here but is still being calculated. 2075222Sksewell@umich.edu 2085222Sksewell@umich.edu checkSum += writeOutString(proxy, addr + 8, oemID, 8); 2095222Sksewell@umich.edu checkSum += writeOutString(proxy, addr + 16, productID, 12); 2105222Sksewell@umich.edu 2115222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 28, oemTableAddr); 2125222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 32, oemTableSize); 2135222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 34, (uint16_t)baseEntries.size()); 2145222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 36, localApic); 2155222Sksewell@umich.edu 2165222Sksewell@umich.edu uint8_t reserved = 0; 2175222Sksewell@umich.edu proxy.writeBlob(addr + 43, &reserved, 1); 2185222Sksewell@umich.edu checkSum += reserved; 2195222Sksewell@umich.edu 2205222Sksewell@umich.edu vector<BaseConfigEntry *>::iterator baseEnt; 2215222Sksewell@umich.edu uint16_t offset = 44; 2225222Sksewell@umich.edu for (baseEnt = baseEntries.begin(); 2235222Sksewell@umich.edu baseEnt != baseEntries.end(); baseEnt++) { 2245222Sksewell@umich.edu offset += (*baseEnt)->writeOut(proxy, addr + offset, checkSum); 2255222Sksewell@umich.edu } 2265222Sksewell@umich.edu 2275222Sksewell@umich.edu // We've found the end of the base table this point. 2285222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 4, offset); 2295222Sksewell@umich.edu 2305222Sksewell@umich.edu vector<ExtConfigEntry *>::iterator extEnt; 2315222Sksewell@umich.edu uint16_t extOffset = 0; 2325222Sksewell@umich.edu uint8_t extCheckSum = 0; 2335222Sksewell@umich.edu for (extEnt = extEntries.begin(); 2345222Sksewell@umich.edu extEnt != extEntries.end(); extEnt++) { 2355222Sksewell@umich.edu extOffset += (*extEnt)->writeOut(proxy, 2365222Sksewell@umich.edu addr + offset + extOffset, extCheckSum); 2375222Sksewell@umich.edu } 2385222Sksewell@umich.edu 2395222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 40, extOffset); 2405222Sksewell@umich.edu extCheckSum = -extCheckSum; 2415222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 42, extCheckSum); 2425222Sksewell@umich.edu 2435222Sksewell@umich.edu // And now, we finally have the whole check sum completed. 2445222Sksewell@umich.edu checkSum = -checkSum; 2455222Sksewell@umich.edu writeOutField(proxy, addr + 7, checkSum); 2465222Sksewell@umich.edu 2475222Sksewell@umich.edu return offset + extOffset; 2485222Sksewell@umich.edu}; 2495222Sksewell@umich.edu 2505222Sksewell@umich.eduX86ISA::IntelMP::ConfigTable::ConfigTable(Params * p) : SimObject(p), 2515222Sksewell@umich.edu specRev(p->spec_rev), oemID(p->oem_id), productID(p->product_id), 2525222Sksewell@umich.edu oemTableAddr(p->oem_table_addr), oemTableSize(p->oem_table_size), 2535222Sksewell@umich.edu localApic(p->local_apic), 2545222Sksewell@umich.edu baseEntries(p->base_entries), extEntries(p->ext_entries) 2555222Sksewell@umich.edu{} 2565222Sksewell@umich.edu 2575222Sksewell@umich.eduX86ISA::IntelMP::ConfigTable * 2585222Sksewell@umich.eduX86IntelMPConfigTableParams::create() 2595222Sksewell@umich.edu{ 2605222Sksewell@umich.edu return new X86ISA::IntelMP::ConfigTable(this); 2615222Sksewell@umich.edu} 2625222Sksewell@umich.edu 2635222Sksewell@umich.eduAddr 2645222Sksewell@umich.eduX86ISA::IntelMP::Processor::writeOut( 2655222Sksewell@umich.edu PortProxy& proxy, Addr addr, uint8_t &checkSum) 2665222Sksewell@umich.edu{ 2675222Sksewell@umich.edu BaseConfigEntry::writeOut(proxy, addr, checkSum); 2685222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 1, localApicID); 2695222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 2, localApicVersion); 2705222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 3, cpuFlags); 2715222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 4, cpuSignature); 2725222Sksewell@umich.edu checkSum += writeOutField(proxy, addr + 8, featureFlags); 2735222Sksewell@umich.edu 274 uint32_t reserved = 0; 275 proxy.writeBlob(addr + 12, (uint8_t *)(&reserved), 4); 276 proxy.writeBlob(addr + 16, (uint8_t *)(&reserved), 4); 277 return 20; 278} 279 280X86ISA::IntelMP::Processor::Processor(Params * p) : BaseConfigEntry(p, 0), 281 localApicID(p->local_apic_id), localApicVersion(p->local_apic_version), 282 cpuFlags(0), cpuSignature(0), featureFlags(p->feature_flags) 283{ 284 if (p->enable) 285 cpuFlags |= (1 << 0); 286 if (p->bootstrap) 287 cpuFlags |= (1 << 1); 288 289 replaceBits(cpuSignature, 0, 3, p->stepping); 290 replaceBits(cpuSignature, 4, 7, p->model); 291 replaceBits(cpuSignature, 8, 11, p->family); 292} 293 294X86ISA::IntelMP::Processor * 295X86IntelMPProcessorParams::create() 296{ 297 return new X86ISA::IntelMP::Processor(this); 298} 299 300Addr 301X86ISA::IntelMP::Bus::writeOut( 302 PortProxy& proxy, Addr addr, uint8_t &checkSum) 303{ 304 BaseConfigEntry::writeOut(proxy, addr, checkSum); 305 checkSum += writeOutField(proxy, addr + 1, busID); 306 checkSum += writeOutString(proxy, addr + 2, busType, 6); 307 return 8; 308} 309 310X86ISA::IntelMP::Bus::Bus(Params * p) : BaseConfigEntry(p, 1), 311 busID(p->bus_id), busType(p->bus_type) 312{} 313 314X86ISA::IntelMP::Bus * 315X86IntelMPBusParams::create() 316{ 317 return new X86ISA::IntelMP::Bus(this); 318} 319 320Addr 321X86ISA::IntelMP::IOAPIC::writeOut( 322 PortProxy& proxy, Addr addr, uint8_t &checkSum) 323{ 324 BaseConfigEntry::writeOut(proxy, addr, checkSum); 325 checkSum += writeOutField(proxy, addr + 1, id); 326 checkSum += writeOutField(proxy, addr + 2, version); 327 checkSum += writeOutField(proxy, addr + 3, flags); 328 checkSum += writeOutField(proxy, addr + 4, address); 329 return 8; 330} 331 332X86ISA::IntelMP::IOAPIC::IOAPIC(Params * p) : BaseConfigEntry(p, 2), 333 id(p->id), version(p->version), flags(0), address(p->address) 334{ 335 if (p->enable) 336 flags |= 1; 337} 338 339X86ISA::IntelMP::IOAPIC * 340X86IntelMPIOAPICParams::create() 341{ 342 return new X86ISA::IntelMP::IOAPIC(this); 343} 344 345Addr 346X86ISA::IntelMP::IntAssignment::writeOut( 347 PortProxy& proxy, Addr addr, uint8_t &checkSum) 348{ 349 BaseConfigEntry::writeOut(proxy, addr, checkSum); 350 checkSum += writeOutField(proxy, addr + 1, interruptType); 351 checkSum += writeOutField(proxy, addr + 2, flags); 352 checkSum += writeOutField(proxy, addr + 4, sourceBusID); 353 checkSum += writeOutField(proxy, addr + 5, sourceBusIRQ); 354 checkSum += writeOutField(proxy, addr + 6, destApicID); 355 checkSum += writeOutField(proxy, addr + 7, destApicIntIn); 356 return 8; 357} 358 359X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(Params * p) : 360 IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 3, 361 p->source_bus_id, p->source_bus_irq, 362 p->dest_io_apic_id, p->dest_io_apic_intin) 363{} 364 365X86ISA::IntelMP::IOIntAssignment * 366X86IntelMPIOIntAssignmentParams::create() 367{ 368 return new X86ISA::IntelMP::IOIntAssignment(this); 369} 370 371X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(Params * p) : 372 IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 4, 373 p->source_bus_id, p->source_bus_irq, 374 p->dest_local_apic_id, p->dest_local_apic_intin) 375{} 376 377X86ISA::IntelMP::LocalIntAssignment * 378X86IntelMPLocalIntAssignmentParams::create() 379{ 380 return new X86ISA::IntelMP::LocalIntAssignment(this); 381} 382 383Addr 384X86ISA::IntelMP::AddrSpaceMapping::writeOut( 385 PortProxy& proxy, Addr addr, uint8_t &checkSum) 386{ 387 ExtConfigEntry::writeOut(proxy, addr, checkSum); 388 checkSum += writeOutField(proxy, addr + 2, busID); 389 checkSum += writeOutField(proxy, addr + 3, addrType); 390 checkSum += writeOutField(proxy, addr + 4, addr); 391 checkSum += writeOutField(proxy, addr + 12, addrLength); 392 return length; 393} 394 395X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(Params * p) : 396 ExtConfigEntry(p, 128, 20), 397 busID(p->bus_id), addrType(p->address_type), 398 addr(p->address), addrLength(p->length) 399{} 400 401X86ISA::IntelMP::AddrSpaceMapping * 402X86IntelMPAddrSpaceMappingParams::create() 403{ 404 return new X86ISA::IntelMP::AddrSpaceMapping(this); 405} 406 407Addr 408X86ISA::IntelMP::BusHierarchy::writeOut( 409 PortProxy& proxy, Addr addr, uint8_t &checkSum) 410{ 411 ExtConfigEntry::writeOut(proxy, addr, checkSum); 412 checkSum += writeOutField(proxy, addr + 2, busID); 413 checkSum += writeOutField(proxy, addr + 3, info); 414 checkSum += writeOutField(proxy, addr + 4, parentBus); 415 416 uint32_t reserved = 0; 417 proxy.writeBlob(addr + 5, (uint8_t *)(&reserved), 3); 418 419 return length; 420} 421 422X86ISA::IntelMP::BusHierarchy::BusHierarchy(Params * p) : 423 ExtConfigEntry(p, 129, 8), 424 busID(p->bus_id), info(0), parentBus(p->parent_bus) 425{ 426 if (p->subtractive_decode) 427 info |= 1; 428} 429 430X86ISA::IntelMP::BusHierarchy * 431X86IntelMPBusHierarchyParams::create() 432{ 433 return new X86ISA::IntelMP::BusHierarchy(this); 434} 435 436Addr 437X86ISA::IntelMP::CompatAddrSpaceMod::writeOut( 438 PortProxy& proxy, Addr addr, uint8_t &checkSum) 439{ 440 ExtConfigEntry::writeOut(proxy, addr, checkSum); 441 checkSum += writeOutField(proxy, addr + 2, busID); 442 checkSum += writeOutField(proxy, addr + 3, mod); 443 checkSum += writeOutField(proxy, addr + 4, rangeList); 444 return length; 445} 446 447X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(Params * p) : 448 ExtConfigEntry(p, 130, 8), 449 busID(p->bus_id), mod(0), rangeList(p->range_list) 450{ 451 if (p->add) 452 mod |= 1; 453} 454 455X86ISA::IntelMP::CompatAddrSpaceMod * 456X86IntelMPCompatAddrSpaceModParams::create() 457{ 458 return new X86ISA::IntelMP::CompatAddrSpaceMod(this); 459} 460