intelmp.cc revision 6216
12SN/A/* 21762SN/A * Copyright (c) 2008 The Hewlett-Packard Development Company 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use of this software in source and binary forms, 62SN/A * with or without modification, are permitted provided that the 72SN/A * following conditions are met: 82SN/A * 92SN/A * The software must be used only for Non-Commercial Use which means any 102SN/A * use which is NOT directed to receiving any direct monetary 112SN/A * compensation for, or commercial advantage from such use. Illustrative 122SN/A * examples of non-commercial use are academic research, personal study, 132SN/A * teaching, education and corporate research & development. 142SN/A * Illustrative examples of commercial use are distributing products for 152SN/A * commercial advantage and providing services using the software for 162SN/A * commercial advantage. 172SN/A * 182SN/A * If you wish to use this software or functionality therein that may be 192SN/A * covered by patents for commercial use, please contact: 202SN/A * Director of Intellectual Property Licensing 212SN/A * Office of Strategy and Technology 222SN/A * Hewlett-Packard Company 232SN/A * 1501 Page Mill Road 242SN/A * Palo Alto, California 94304 252SN/A * 262SN/A * Redistributions of source code must retain the above copyright notice, 272665Ssaidi@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 282760Sbinkertn@umich.edu * in binary form must reproduce the above copyright notice, this list of 292760Sbinkertn@umich.edu * conditions and the following disclaimer in the documentation and/or 302665Ssaidi@eecs.umich.edu * other materials provided with the distribution. Neither the name of 312SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 322SN/A * contributors may be used to endorse or promote products derived from 332SN/A * this software without specific prior written permission. No right of 342SN/A * sublicense is granted herewith. Derivatives of the software and 352SN/A * output created using the software may be prepared, but only for 362SN/A * Non-Commercial Uses. Derivatives of the software may be shared with 372SN/A * others provided: (i) the others agree to abide by the list of 382SN/A * conditions herein which includes the Non-Commercial Use restrictions; 392SN/A * and (ii) such Derivatives of the software include the above copyright 402SN/A * notice to acknowledge the contribution from this software where 418229Snate@binkert.org * applicable, this list of conditions and the disclaimer below. 422SN/A * 438229Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 444841Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 452SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 466214Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 472SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 482738Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49395SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50237SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514000Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 522SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 539048SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 549048SAli.Saidi@ARM.com * 559056SAli.Saidi@ARM.com * Authors: Gabe Black 569048SAli.Saidi@ARM.com */ 579048SAli.Saidi@ARM.com 589056SAli.Saidi@ARM.com#include "arch/x86/bios/intelmp.hh" 599048SAli.Saidi@ARM.com#include "arch/x86/isa_traits.hh" 609431SAndreas.Sandberg@ARM.com#include "base/misc.hh" 619048SAli.Saidi@ARM.com#include "base/types.hh" 62217SN/A#include "mem/port.hh" 63502SN/A#include "sim/byteswap.hh" 64217SN/A 65217SN/A// Config entry types 66237SN/A#include "params/X86IntelMPBaseConfigEntry.hh" 67502SN/A#include "params/X86IntelMPExtConfigEntry.hh" 68217SN/A 69217SN/A// General table structures 706820SLisa.Hsu@amd.com#include "params/X86IntelMPConfigTable.hh" 716820SLisa.Hsu@amd.com#include "params/X86IntelMPFloatingPointer.hh" 726820SLisa.Hsu@amd.com 736820SLisa.Hsu@amd.com// Base entry types 74217SN/A#include "params/X86IntelMPBus.hh" 756227Snate@binkert.org#include "params/X86IntelMPIOAPIC.hh" 76217SN/A#include "params/X86IntelMPIOIntAssignment.hh" 77217SN/A#include "params/X86IntelMPLocalIntAssignment.hh" 784841Ssaidi@eecs.umich.edu#include "params/X86IntelMPProcessor.hh" 794841Ssaidi@eecs.umich.edu 804841Ssaidi@eecs.umich.edu// Extended entry types 814841Ssaidi@eecs.umich.edu#include "params/X86IntelMPAddrSpaceMapping.hh" 827948SAli.Saidi@ARM.com#include "params/X86IntelMPBusHierarchy.hh" 837948SAli.Saidi@ARM.com#include "params/X86IntelMPCompatAddrSpaceMod.hh" 847948SAli.Saidi@ARM.com 857948SAli.Saidi@ARM.comusing namespace std; 86237SN/A 876227Snate@binkert.orgconst char X86ISA::IntelMP::FloatingPointer::signature[] = "_MP_"; 88217SN/A 894841Ssaidi@eecs.umich.edutemplate<class T> 904841Ssaidi@eecs.umich.eduuint8_t 914841Ssaidi@eecs.umich.eduwriteOutField(FunctionalPort * port, Addr addr, T val) 924841Ssaidi@eecs.umich.edu{ 937948SAli.Saidi@ARM.com T guestVal = X86ISA::htog(val); 947948SAli.Saidi@ARM.com port->writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T)); 957948SAli.Saidi@ARM.com 967948SAli.Saidi@ARM.com uint8_t checkSum = 0; 97237SN/A while(guestVal) { 98237SN/A checkSum += guestVal; 994000Ssaidi@eecs.umich.edu guestVal >>= 8; 100237SN/A } 1018902Sandreas.hansson@arm.com return checkSum; 1028902Sandreas.hansson@arm.com} 1038902Sandreas.hansson@arm.com 1048902Sandreas.hansson@arm.comuint8_t 1058902Sandreas.hansson@arm.comwriteOutString(FunctionalPort * port, Addr addr, string str, int length) 1068902Sandreas.hansson@arm.com{ 1078902Sandreas.hansson@arm.com char cleanedString[length + 1]; 1088902Sandreas.hansson@arm.com cleanedString[length] = 0; 1098902Sandreas.hansson@arm.com 1108902Sandreas.hansson@arm.com if (str.length() > length) { 1118902Sandreas.hansson@arm.com memcpy(cleanedString, str.c_str(), length); 112237SN/A warn("Intel MP configuration table string \"%s\" " 113217SN/A "will be truncated to \"%s\".\n", str, cleanedString); 114217SN/A } else { 115217SN/A memcpy(cleanedString, str.c_str(), str.length()); 116237SN/A memset(cleanedString + str.length(), 0, length - str.length()); 1175543Ssaidi@eecs.umich.edu } 118217SN/A port->writeBlob(addr, (uint8_t *)(&cleanedString), length); 1195543Ssaidi@eecs.umich.edu 1206820SLisa.Hsu@amd.com uint8_t checkSum = 0; 121217SN/A for (int i = 0; i < length; i++) 122223SN/A checkSum += cleanedString[i]; 1235543Ssaidi@eecs.umich.edu 124223SN/A return checkSum; 1255543Ssaidi@eecs.umich.edu} 1265543Ssaidi@eecs.umich.edu 1275543Ssaidi@eecs.umich.eduAddr 1285543Ssaidi@eecs.umich.eduX86ISA::IntelMP::FloatingPointer::writeOut(FunctionalPort * port, Addr addr) 1298902Sandreas.hansson@arm.com{ 130223SN/A // Make sure that either a config table is present or a default 131223SN/A // configuration was found but not both. 1325543Ssaidi@eecs.umich.edu if (!tableAddr && !defaultConfig) 133217SN/A fatal("Either an MP configuration table or a default configuration " 134217SN/A "must be used."); 1355543Ssaidi@eecs.umich.edu if (tableAddr && defaultConfig) 136237SN/A fatal("Both an MP configuration table and a default configuration " 137237SN/A "were set."); 1385543Ssaidi@eecs.umich.edu 139237SN/A uint8_t checkSum = 0; 1405543Ssaidi@eecs.umich.edu 1415543Ssaidi@eecs.umich.edu port->writeBlob(addr, (uint8_t *)signature, 4); 1425543Ssaidi@eecs.umich.edu for (int i = 0; i < 4; i++) 1435543Ssaidi@eecs.umich.edu checkSum += signature[i]; 1448902Sandreas.hansson@arm.com 145237SN/A checkSum += writeOutField(port, addr + 4, tableAddr); 146217SN/A 1479342SAndreas.Sandberg@arm.com // The length of the structure in paragraphs, aka 16 byte chunks. 1482SN/A uint8_t length = 1; 1499342SAndreas.Sandberg@arm.com port->writeBlob(addr + 8, &length, 1); 1509342SAndreas.Sandberg@arm.com checkSum += length; 1519342SAndreas.Sandberg@arm.com 1529342SAndreas.Sandberg@arm.com port->writeBlob(addr + 9, &specRev, 1); 1539342SAndreas.Sandberg@arm.com checkSum += specRev; 1549342SAndreas.Sandberg@arm.com 1552SN/A port->writeBlob(addr + 11, &defaultConfig, 1); 156395SN/A checkSum += defaultConfig; 1572SN/A 1582SN/A uint32_t features2_5 = imcrPresent ? (1 << 7) : 0; 159510SN/A checkSum += writeOutField(port, addr + 12, features2_5); 160510SN/A 1612SN/A checkSum = -checkSum; 1622SN/A port->writeBlob(addr + 10, &checkSum, 1); 1635739Snate@binkert.org 1645739Snate@binkert.org return 16; 1652SN/A} 166265SN/A 167512SN/AX86ISA::IntelMP::FloatingPointer::FloatingPointer(Params * p) : 1682SN/A SimObject(p), tableAddr(0), specRev(p->spec_rev), 1695739Snate@binkert.org defaultConfig(p->default_config), imcrPresent(p->imcr_present) 1705739Snate@binkert.org{} 171237SN/A 1725739Snate@binkert.orgX86ISA::IntelMP::FloatingPointer * 1732SN/AX86IntelMPFloatingPointerParams::create() 1742287SN/A{ 1752287SN/A return new X86ISA::IntelMP::FloatingPointer(this); 1762287SN/A} 1772868Sktlim@umich.edu 178395SN/AAddr 1792SN/AX86ISA::IntelMP::BaseConfigEntry::writeOut(FunctionalPort * port, 1802SN/A Addr addr, uint8_t &checkSum) 1819554Sandreas.hansson@arm.com{ 1829554Sandreas.hansson@arm.com port->writeBlob(addr, &type, 1); 1832SN/A checkSum += type; 184395SN/A return 1; 185395SN/A} 1862SN/A 1872SN/AX86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(Params * p, uint8_t _type) : 1882SN/A SimObject(p), type(_type) 189395SN/A{} 1902SN/A 191395SN/AAddr 1922SN/AX86ISA::IntelMP::ExtConfigEntry::writeOut(FunctionalPort * port, 1932SN/A Addr addr, uint8_t &checkSum) 194395SN/A{ 1952SN/A port->writeBlob(addr, &type, 1); 196395SN/A checkSum += type; 1972SN/A port->writeBlob(addr + 1, &length, 1); 1982SN/A checkSum += length; 1992SN/A return 1; 200395SN/A} 2012SN/A 202395SN/AX86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(Params * p, 2032SN/A uint8_t _type, uint8_t _length) : 204395SN/A SimObject(p), type(_type), length(_length) 2052SN/A{} 2062SN/A 207395SN/Aconst char X86ISA::IntelMP::ConfigTable::signature[] = "PCMP"; 208395SN/A 2092SN/AAddr 2102SN/AX86ISA::IntelMP::ConfigTable::writeOut(FunctionalPort * port, Addr addr) 2112SN/A{ 212395SN/A uint8_t checkSum = 0; 213395SN/A 2142SN/A port->writeBlob(addr, (uint8_t *)signature, 4); 2152SN/A for (int i = 0; i < 4; i++) 2162SN/A checkSum += signature[i]; 2172SN/A 2182SN/A // Base table length goes here but will be calculated later. 2192SN/A 220395SN/A port->writeBlob(addr + 6, (uint8_t *)(&specRev), 1); 2212SN/A checkSum += specRev; 2222SN/A 2232SN/A // The checksum goes here but is still being calculated. 2242SN/A 2252SN/A checkSum += writeOutString(port, addr + 8, oemID, 8); 2262SN/A checkSum += writeOutString(port, addr + 16, productID, 12); 2272SN/A 2282SN/A checkSum += writeOutField(port, addr + 28, oemTableAddr); 229395SN/A checkSum += writeOutField(port, addr + 32, oemTableSize); 230395SN/A checkSum += writeOutField(port, addr + 34, (uint16_t)baseEntries.size()); 2312738Sstever@eecs.umich.edu checkSum += writeOutField(port, addr + 36, localApic); 2322SN/A 2332SN/A uint8_t reserved = 0; 2342SN/A port->writeBlob(addr + 43, &reserved, 1); 2352SN/A checkSum += reserved; 2362SN/A 237395SN/A vector<BaseConfigEntry *>::iterator baseEnt; 238395SN/A uint16_t offset = 44; 2392SN/A for (baseEnt = baseEntries.begin(); 240395SN/A baseEnt != baseEntries.end(); baseEnt++) { 2412SN/A offset += (*baseEnt)->writeOut(port, addr + offset, checkSum); 242395SN/A } 2432SN/A 244395SN/A // We've found the end of the base table this point. 2452738Sstever@eecs.umich.edu checkSum += writeOutField(port, addr + 4, offset); 2462SN/A 2472SN/A vector<ExtConfigEntry *>::iterator extEnt; 2482SN/A uint16_t extOffset = 0; 2492SN/A uint8_t extCheckSum = 0; 250395SN/A for (extEnt = extEntries.begin(); 2512SN/A extEnt != extEntries.end(); extEnt++) { 2522SN/A extOffset += (*extEnt)->writeOut(port, 2535543Ssaidi@eecs.umich.edu addr + offset + extOffset, extCheckSum); 2545543Ssaidi@eecs.umich.edu } 255237SN/A 2562SN/A checkSum += writeOutField(port, addr + 40, extOffset); 257237SN/A extCheckSum = -extCheckSum; 258237SN/A checkSum += writeOutField(port, addr + 42, extCheckSum); 259237SN/A 260237SN/A // And now, we finally have the whole check sum completed. 261237SN/A checkSum = -checkSum; 262237SN/A writeOutField(port, addr + 7, checkSum); 263237SN/A 2647491Ssteve.reinhardt@amd.com return offset + extOffset; 2659086Sandreas.hansson@arm.com}; 266237SN/A 267937SN/AX86ISA::IntelMP::ConfigTable::ConfigTable(Params * p) : SimObject(p), 268937SN/A specRev(p->spec_rev), oemID(p->oem_id), productID(p->product_id), 269237SN/A oemTableAddr(p->oem_table_addr), oemTableSize(p->oem_table_size), 270237SN/A localApic(p->local_apic), 271237SN/A baseEntries(p->base_entries), extEntries(p->ext_entries) 272237SN/A{} 2734000Ssaidi@eecs.umich.edu 274304SN/AX86ISA::IntelMP::ConfigTable * 275304SN/AX86IntelMPConfigTableParams::create() 276449SN/A{ 277449SN/A return new X86ISA::IntelMP::ConfigTable(this); 278449SN/A} 2797491Ssteve.reinhardt@amd.com 2807491Ssteve.reinhardt@amd.comAddr 2817491Ssteve.reinhardt@amd.comX86ISA::IntelMP::Processor::writeOut( 2827491Ssteve.reinhardt@amd.com FunctionalPort * port, Addr addr, uint8_t &checkSum) 2837491Ssteve.reinhardt@amd.com{ 2847491Ssteve.reinhardt@amd.com BaseConfigEntry::writeOut(port, addr, checkSum); 2857491Ssteve.reinhardt@amd.com checkSum += writeOutField(port, addr + 1, localApicID); 2867491Ssteve.reinhardt@amd.com checkSum += writeOutField(port, addr + 2, localApicVersion); 2877491Ssteve.reinhardt@amd.com checkSum += writeOutField(port, addr + 3, cpuFlags); 2887491Ssteve.reinhardt@amd.com checkSum += writeOutField(port, addr + 4, cpuSignature); 2897491Ssteve.reinhardt@amd.com checkSum += writeOutField(port, addr + 8, featureFlags); 2907823Ssteve.reinhardt@amd.com 2917491Ssteve.reinhardt@amd.com uint32_t reserved = 0; 2927491Ssteve.reinhardt@amd.com port->writeBlob(addr + 12, (uint8_t *)(&reserved), 4); 293449SN/A port->writeBlob(addr + 16, (uint8_t *)(&reserved), 4); 294449SN/A return 20; 295449SN/A} 296449SN/A 297449SN/AX86ISA::IntelMP::Processor::Processor(Params * p) : BaseConfigEntry(p, 0), 298449SN/A localApicID(p->local_apic_id), localApicVersion(p->local_apic_version), 299449SN/A cpuFlags(0), cpuSignature(0), featureFlags(p->feature_flags) 300449SN/A{ 301449SN/A if (p->enable) 302237SN/A cpuFlags |= (1 << 0); 3032SN/A if (p->bootstrap) 3042SN/A cpuFlags |= (1 << 1); 305 306 replaceBits(cpuSignature, 0, 3, p->stepping); 307 replaceBits(cpuSignature, 4, 7, p->model); 308 replaceBits(cpuSignature, 8, 11, p->family); 309} 310 311X86ISA::IntelMP::Processor * 312X86IntelMPProcessorParams::create() 313{ 314 return new X86ISA::IntelMP::Processor(this); 315} 316 317Addr 318X86ISA::IntelMP::Bus::writeOut( 319 FunctionalPort * port, Addr addr, uint8_t &checkSum) 320{ 321 BaseConfigEntry::writeOut(port, addr, checkSum); 322 checkSum += writeOutField(port, addr + 1, busID); 323 checkSum += writeOutString(port, addr + 2, busType, 6); 324 return 8; 325} 326 327X86ISA::IntelMP::Bus::Bus(Params * p) : BaseConfigEntry(p, 1), 328 busID(p->bus_id), busType(p->bus_type) 329{} 330 331X86ISA::IntelMP::Bus * 332X86IntelMPBusParams::create() 333{ 334 return new X86ISA::IntelMP::Bus(this); 335} 336 337Addr 338X86ISA::IntelMP::IOAPIC::writeOut( 339 FunctionalPort * port, Addr addr, uint8_t &checkSum) 340{ 341 BaseConfigEntry::writeOut(port, addr, checkSum); 342 checkSum += writeOutField(port, addr + 1, id); 343 checkSum += writeOutField(port, addr + 2, version); 344 checkSum += writeOutField(port, addr + 3, flags); 345 checkSum += writeOutField(port, addr + 4, address); 346 return 8; 347} 348 349X86ISA::IntelMP::IOAPIC::IOAPIC(Params * p) : BaseConfigEntry(p, 2), 350 id(p->id), version(p->version), flags(0), address(p->address) 351{ 352 if (p->enable) 353 flags |= 1; 354} 355 356X86ISA::IntelMP::IOAPIC * 357X86IntelMPIOAPICParams::create() 358{ 359 return new X86ISA::IntelMP::IOAPIC(this); 360} 361 362Addr 363X86ISA::IntelMP::IntAssignment::writeOut( 364 FunctionalPort * port, Addr addr, uint8_t &checkSum) 365{ 366 BaseConfigEntry::writeOut(port, addr, checkSum); 367 checkSum += writeOutField(port, addr + 1, interruptType); 368 checkSum += writeOutField(port, addr + 2, flags); 369 checkSum += writeOutField(port, addr + 4, sourceBusID); 370 checkSum += writeOutField(port, addr + 5, sourceBusIRQ); 371 checkSum += writeOutField(port, addr + 6, destApicID); 372 checkSum += writeOutField(port, addr + 7, destApicIntIn); 373 return 8; 374} 375 376X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(Params * p) : 377 IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 3, 378 p->source_bus_id, p->source_bus_irq, 379 p->dest_io_apic_id, p->dest_io_apic_intin) 380{} 381 382X86ISA::IntelMP::IOIntAssignment * 383X86IntelMPIOIntAssignmentParams::create() 384{ 385 return new X86ISA::IntelMP::IOIntAssignment(this); 386} 387 388X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(Params * p) : 389 IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 4, 390 p->source_bus_id, p->source_bus_irq, 391 p->dest_local_apic_id, p->dest_local_apic_intin) 392{} 393 394X86ISA::IntelMP::LocalIntAssignment * 395X86IntelMPLocalIntAssignmentParams::create() 396{ 397 return new X86ISA::IntelMP::LocalIntAssignment(this); 398} 399 400Addr 401X86ISA::IntelMP::AddrSpaceMapping::writeOut( 402 FunctionalPort * port, Addr addr, uint8_t &checkSum) 403{ 404 ExtConfigEntry::writeOut(port, addr, checkSum); 405 checkSum += writeOutField(port, addr + 2, busID); 406 checkSum += writeOutField(port, addr + 3, addrType); 407 checkSum += writeOutField(port, addr + 4, addr); 408 checkSum += writeOutField(port, addr + 12, addrLength); 409 return length; 410} 411 412X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(Params * p) : 413 ExtConfigEntry(p, 128, 20), 414 busID(p->bus_id), addrType(p->address_type), 415 addr(p->address), addrLength(p->length) 416{} 417 418X86ISA::IntelMP::AddrSpaceMapping * 419X86IntelMPAddrSpaceMappingParams::create() 420{ 421 return new X86ISA::IntelMP::AddrSpaceMapping(this); 422} 423 424Addr 425X86ISA::IntelMP::BusHierarchy::writeOut( 426 FunctionalPort * port, Addr addr, uint8_t &checkSum) 427{ 428 ExtConfigEntry::writeOut(port, addr, checkSum); 429 checkSum += writeOutField(port, addr + 2, busID); 430 checkSum += writeOutField(port, addr + 3, info); 431 checkSum += writeOutField(port, addr + 4, parentBus); 432 433 uint32_t reserved = 0; 434 port->writeBlob(addr + 5, (uint8_t *)(&reserved), 3); 435 436 return length; 437} 438 439X86ISA::IntelMP::BusHierarchy::BusHierarchy(Params * p) : 440 ExtConfigEntry(p, 129, 8), 441 busID(p->bus_id), info(0), parentBus(p->parent_bus) 442{ 443 if (p->subtractive_decode) 444 info |= 1; 445} 446 447X86ISA::IntelMP::BusHierarchy * 448X86IntelMPBusHierarchyParams::create() 449{ 450 return new X86ISA::IntelMP::BusHierarchy(this); 451} 452 453Addr 454X86ISA::IntelMP::CompatAddrSpaceMod::writeOut( 455 FunctionalPort * port, Addr addr, uint8_t &checkSum) 456{ 457 ExtConfigEntry::writeOut(port, addr, checkSum); 458 checkSum += writeOutField(port, addr + 2, busID); 459 checkSum += writeOutField(port, addr + 3, mod); 460 checkSum += writeOutField(port, addr + 4, rangeList); 461 return length; 462} 463 464X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(Params * p) : 465 ExtConfigEntry(p, 130, 8), 466 busID(p->bus_id), mod(0), rangeList(p->range_list) 467{ 468 if (p->add) 469 mod |= 1; 470} 471 472X86ISA::IntelMP::CompatAddrSpaceMod * 473X86IntelMPCompatAddrSpaceModParams::create() 474{ 475 return new X86ISA::IntelMP::CompatAddrSpaceMod(this); 476} 477