tlb.cc revision 8888
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include <cstring> 32 33#include "arch/sparc/asi.hh" 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/registers.hh" 36#include "arch/sparc/tlb.hh" 37#include "base/bitfield.hh" 38#include "base/trace.hh" 39#include "cpu/base.hh" 40#include "cpu/thread_context.hh" 41#include "debug/IPR.hh" 42#include "debug/TLB.hh" 43#include "mem/packet_access.hh" 44#include "mem/request.hh" 45#include "sim/full_system.hh" 46#include "sim/system.hh" 47 48/* @todo remove some of the magic constants. -- ali 49 * */ 50namespace SparcISA { 51 52TLB::TLB(const Params *p) 53 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 54 cacheState(0), cacheValid(false) 55{ 56 // To make this work you'll have to change the hypervisor and OS 57 if (size > 64) 58 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 59 60 tlb = new TlbEntry[size]; 61 std::memset(tlb, 0, sizeof(TlbEntry) * size); 62 63 for (int x = 0; x < size; x++) 64 freeList.push_back(&tlb[x]); 65 66 c0_tsb_ps0 = 0; 67 c0_tsb_ps1 = 0; 68 c0_config = 0; 69 cx_tsb_ps0 = 0; 70 cx_tsb_ps1 = 0; 71 cx_config = 0; 72 sfsr = 0; 73 tag_access = 0; 74 sfar = 0; 75 cacheEntry[0] = NULL; 76 cacheEntry[1] = NULL; 77} 78 79void 80TLB::clearUsedBits() 81{ 82 MapIter i; 83 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 84 TlbEntry *t = i->second; 85 if (!t->pte.locked()) { 86 t->used = false; 87 usedEntries--; 88 } 89 } 90} 91 92 93void 94TLB::insert(Addr va, int partition_id, int context_id, bool real, 95 const PageTableEntry& PTE, int entry) 96{ 97 MapIter i; 98 TlbEntry *new_entry = NULL; 99// TlbRange tr; 100 int x; 101 102 cacheValid = false; 103 va &= ~(PTE.size()-1); 104 /* tr.va = va; 105 tr.size = PTE.size() - 1; 106 tr.contextId = context_id; 107 tr.partitionId = partition_id; 108 tr.real = real; 109*/ 110 111 DPRINTF(TLB, 112 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 113 va, PTE.paddr(), partition_id, context_id, (int)real, entry); 114 115 // Demap any entry that conflicts 116 for (x = 0; x < size; x++) { 117 if (tlb[x].range.real == real && 118 tlb[x].range.partitionId == partition_id && 119 tlb[x].range.va < va + PTE.size() - 1 && 120 tlb[x].range.va + tlb[x].range.size >= va && 121 (real || tlb[x].range.contextId == context_id )) 122 { 123 if (tlb[x].valid) { 124 freeList.push_front(&tlb[x]); 125 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 126 127 tlb[x].valid = false; 128 if (tlb[x].used) { 129 tlb[x].used = false; 130 usedEntries--; 131 } 132 lookupTable.erase(tlb[x].range); 133 } 134 } 135 } 136 137 if (entry != -1) { 138 assert(entry < size && entry >= 0); 139 new_entry = &tlb[entry]; 140 } else { 141 if (!freeList.empty()) { 142 new_entry = freeList.front(); 143 } else { 144 x = lastReplaced; 145 do { 146 ++x; 147 if (x == size) 148 x = 0; 149 if (x == lastReplaced) 150 goto insertAllLocked; 151 } while (tlb[x].pte.locked()); 152 lastReplaced = x; 153 new_entry = &tlb[x]; 154 } 155 } 156 157insertAllLocked: 158 // Update the last ently if their all locked 159 if (!new_entry) { 160 new_entry = &tlb[size-1]; 161 } 162 163 freeList.remove(new_entry); 164 if (new_entry->valid && new_entry->used) 165 usedEntries--; 166 if (new_entry->valid) 167 lookupTable.erase(new_entry->range); 168 169 170 assert(PTE.valid()); 171 new_entry->range.va = va; 172 new_entry->range.size = PTE.size() - 1; 173 new_entry->range.partitionId = partition_id; 174 new_entry->range.contextId = context_id; 175 new_entry->range.real = real; 176 new_entry->pte = PTE; 177 new_entry->used = true;; 178 new_entry->valid = true; 179 usedEntries++; 180 181 i = lookupTable.insert(new_entry->range, new_entry); 182 assert(i != lookupTable.end()); 183 184 // If all entries have their used bit set, clear it on them all, 185 // but the one we just inserted 186 if (usedEntries == size) { 187 clearUsedBits(); 188 new_entry->used = true; 189 usedEntries++; 190 } 191} 192 193 194TlbEntry* 195TLB::lookup(Addr va, int partition_id, bool real, int context_id, 196 bool update_used) 197{ 198 MapIter i; 199 TlbRange tr; 200 TlbEntry *t; 201 202 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 203 va, partition_id, context_id, real); 204 // Assemble full address structure 205 tr.va = va; 206 tr.size = 1; 207 tr.contextId = context_id; 208 tr.partitionId = partition_id; 209 tr.real = real; 210 211 // Try to find the entry 212 i = lookupTable.find(tr); 213 if (i == lookupTable.end()) { 214 DPRINTF(TLB, "TLB: No valid entry found\n"); 215 return NULL; 216 } 217 218 // Mark the entries used bit and clear other used bits in needed 219 t = i->second; 220 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 221 t->pte.size()); 222 223 // Update the used bits only if this is a real access (not a fake 224 // one from virttophys() 225 if (!t->used && update_used) { 226 t->used = true; 227 usedEntries++; 228 if (usedEntries == size) { 229 clearUsedBits(); 230 t->used = true; 231 usedEntries++; 232 } 233 } 234 235 return t; 236} 237 238void 239TLB::dumpAll() 240{ 241 MapIter i; 242 for (int x = 0; x < size; x++) { 243 if (tlb[x].valid) { 244 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 245 x, tlb[x].range.partitionId, tlb[x].range.contextId, 246 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 247 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 248 } 249 } 250} 251 252void 253TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 254{ 255 TlbRange tr; 256 MapIter i; 257 258 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 259 va, partition_id, context_id, real); 260 261 cacheValid = false; 262 263 // Assemble full address structure 264 tr.va = va; 265 tr.size = 1; 266 tr.contextId = context_id; 267 tr.partitionId = partition_id; 268 tr.real = real; 269 270 // Demap any entry that conflicts 271 i = lookupTable.find(tr); 272 if (i != lookupTable.end()) { 273 DPRINTF(IPR, "TLB: Demapped page\n"); 274 i->second->valid = false; 275 if (i->second->used) { 276 i->second->used = false; 277 usedEntries--; 278 } 279 freeList.push_front(i->second); 280 lookupTable.erase(i); 281 } 282} 283 284void 285TLB::demapContext(int partition_id, int context_id) 286{ 287 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 288 partition_id, context_id); 289 cacheValid = false; 290 for (int x = 0; x < size; x++) { 291 if (tlb[x].range.contextId == context_id && 292 tlb[x].range.partitionId == partition_id) { 293 if (tlb[x].valid == true) { 294 freeList.push_front(&tlb[x]); 295 } 296 tlb[x].valid = false; 297 if (tlb[x].used) { 298 tlb[x].used = false; 299 usedEntries--; 300 } 301 lookupTable.erase(tlb[x].range); 302 } 303 } 304} 305 306void 307TLB::demapAll(int partition_id) 308{ 309 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 310 cacheValid = false; 311 for (int x = 0; x < size; x++) { 312 if (tlb[x].valid && !tlb[x].pte.locked() && 313 tlb[x].range.partitionId == partition_id) { 314 freeList.push_front(&tlb[x]); 315 tlb[x].valid = false; 316 if (tlb[x].used) { 317 tlb[x].used = false; 318 usedEntries--; 319 } 320 lookupTable.erase(tlb[x].range); 321 } 322 } 323} 324 325void 326TLB::invalidateAll() 327{ 328 cacheValid = false; 329 lookupTable.clear(); 330 331 for (int x = 0; x < size; x++) { 332 if (tlb[x].valid == true) 333 freeList.push_back(&tlb[x]); 334 tlb[x].valid = false; 335 tlb[x].used = false; 336 } 337 usedEntries = 0; 338} 339 340uint64_t 341TLB::TteRead(int entry) 342{ 343 if (entry >= size) 344 panic("entry: %d\n", entry); 345 346 assert(entry < size); 347 if (tlb[entry].valid) 348 return tlb[entry].pte(); 349 else 350 return (uint64_t)-1ll; 351} 352 353uint64_t 354TLB::TagRead(int entry) 355{ 356 assert(entry < size); 357 uint64_t tag; 358 if (!tlb[entry].valid) 359 return (uint64_t)-1ll; 360 361 tag = tlb[entry].range.contextId; 362 tag |= tlb[entry].range.va; 363 tag |= (uint64_t)tlb[entry].range.partitionId << 61; 364 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 365 tag |= (uint64_t)~tlb[entry].pte._size() << 56; 366 return tag; 367} 368 369bool 370TLB::validVirtualAddress(Addr va, bool am) 371{ 372 if (am) 373 return true; 374 if (va >= StartVAddrHole && va <= EndVAddrHole) 375 return false; 376 return true; 377} 378 379void 380TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 381{ 382 if (sfsr & 0x1) 383 sfsr = 0x3; 384 else 385 sfsr = 1; 386 387 if (write) 388 sfsr |= 1 << 2; 389 sfsr |= ct << 4; 390 if (se) 391 sfsr |= 1 << 6; 392 sfsr |= ft << 7; 393 sfsr |= asi << 16; 394} 395 396void 397TLB::writeTagAccess(Addr va, int context) 398{ 399 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 400 va, context, mbits(va, 63,13) | mbits(context,12,0)); 401 402 tag_access = mbits(va, 63,13) | mbits(context,12,0); 403} 404 405void 406TLB::writeSfsr(Addr a, bool write, ContextType ct, 407 bool se, FaultTypes ft, int asi) 408{ 409 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 410 a, (int)write, ct, ft, asi); 411 TLB::writeSfsr(write, ct, se, ft, asi); 412 sfar = a; 413} 414 415Fault 416TLB::translateInst(RequestPtr req, ThreadContext *tc) 417{ 418 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 419 420 Addr vaddr = req->getVaddr(); 421 TlbEntry *e; 422 423 assert(req->getAsi() == ASI_IMPLICIT); 424 425 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 426 vaddr, req->getSize()); 427 428 // Be fast if we can! 429 if (cacheValid && cacheState == tlbdata) { 430 if (cacheEntry[0]) { 431 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 432 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 433 req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 434 return NoFault; 435 } 436 } else { 437 req->setPaddr(vaddr & PAddrImplMask); 438 return NoFault; 439 } 440 } 441 442 bool hpriv = bits(tlbdata,0,0); 443 bool red = bits(tlbdata,1,1); 444 bool priv = bits(tlbdata,2,2); 445 bool addr_mask = bits(tlbdata,3,3); 446 bool lsu_im = bits(tlbdata,4,4); 447 448 int part_id = bits(tlbdata,15,8); 449 int tl = bits(tlbdata,18,16); 450 int pri_context = bits(tlbdata,47,32); 451 int context; 452 ContextType ct; 453 int asi; 454 bool real = false; 455 456 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 457 priv, hpriv, red, lsu_im, part_id); 458 459 if (tl > 0) { 460 asi = ASI_N; 461 ct = Nucleus; 462 context = 0; 463 } else { 464 asi = ASI_P; 465 ct = Primary; 466 context = pri_context; 467 } 468 469 if ( hpriv || red ) { 470 cacheValid = true; 471 cacheState = tlbdata; 472 cacheEntry[0] = NULL; 473 req->setPaddr(vaddr & PAddrImplMask); 474 return NoFault; 475 } 476 477 // If the access is unaligned trap 478 if (vaddr & 0x3) { 479 writeSfsr(false, ct, false, OtherFault, asi); 480 return new MemAddressNotAligned; 481 } 482 483 if (addr_mask) 484 vaddr = vaddr & VAddrAMask; 485 486 if (!validVirtualAddress(vaddr, addr_mask)) { 487 writeSfsr(false, ct, false, VaOutOfRange, asi); 488 return new InstructionAccessException; 489 } 490 491 if (!lsu_im) { 492 e = lookup(vaddr, part_id, true); 493 real = true; 494 context = 0; 495 } else { 496 e = lookup(vaddr, part_id, false, context); 497 } 498 499 if (e == NULL || !e->valid) { 500 writeTagAccess(vaddr, context); 501 if (real) { 502 return new InstructionRealTranslationMiss; 503 } else { 504 if (FullSystem) 505 return new FastInstructionAccessMMUMiss; 506 else 507 return new FastInstructionAccessMMUMiss(req->getVaddr()); 508 } 509 } 510 511 // were not priviledged accesing priv page 512 if (!priv && e->pte.priv()) { 513 writeTagAccess(vaddr, context); 514 writeSfsr(false, ct, false, PrivViolation, asi); 515 return new InstructionAccessException; 516 } 517 518 // cache translation date for next translation 519 cacheValid = true; 520 cacheState = tlbdata; 521 cacheEntry[0] = e; 522 523 req->setPaddr(e->pte.translate(vaddr)); 524 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 525 return NoFault; 526} 527 528Fault 529TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 530{ 531 /* 532 * @todo this could really use some profiling and fixing to make 533 * it faster! 534 */ 535 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 536 Addr vaddr = req->getVaddr(); 537 Addr size = req->getSize(); 538 ASI asi; 539 asi = (ASI)req->getAsi(); 540 bool implicit = false; 541 bool hpriv = bits(tlbdata,0,0); 542 bool unaligned = vaddr & (size - 1); 543 544 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 545 vaddr, size, asi); 546 547 if (lookupTable.size() != 64 - freeList.size()) 548 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 549 freeList.size()); 550 if (asi == ASI_IMPLICIT) 551 implicit = true; 552 553 // Only use the fast path here if there doesn't need to be an unaligned 554 // trap later 555 if (!unaligned) { 556 if (hpriv && implicit) { 557 req->setPaddr(vaddr & PAddrImplMask); 558 return NoFault; 559 } 560 561 // Be fast if we can! 562 if (cacheValid && cacheState == tlbdata) { 563 564 565 566 if (cacheEntry[0]) { 567 TlbEntry *ce = cacheEntry[0]; 568 Addr ce_va = ce->range.va; 569 if (cacheAsi[0] == asi && 570 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 571 (!write || ce->pte.writable())) { 572 req->setPaddr(ce->pte.translate(vaddr)); 573 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 574 req->setFlags(Request::UNCACHEABLE); 575 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 576 return NoFault; 577 } // if matched 578 } // if cache entry valid 579 if (cacheEntry[1]) { 580 TlbEntry *ce = cacheEntry[1]; 581 Addr ce_va = ce->range.va; 582 if (cacheAsi[1] == asi && 583 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 584 (!write || ce->pte.writable())) { 585 req->setPaddr(ce->pte.translate(vaddr)); 586 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 587 req->setFlags(Request::UNCACHEABLE); 588 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 589 return NoFault; 590 } // if matched 591 } // if cache entry valid 592 } 593 } 594 595 bool red = bits(tlbdata,1,1); 596 bool priv = bits(tlbdata,2,2); 597 bool addr_mask = bits(tlbdata,3,3); 598 bool lsu_dm = bits(tlbdata,5,5); 599 600 int part_id = bits(tlbdata,15,8); 601 int tl = bits(tlbdata,18,16); 602 int pri_context = bits(tlbdata,47,32); 603 int sec_context = bits(tlbdata,63,48); 604 605 bool real = false; 606 ContextType ct = Primary; 607 int context = 0; 608 609 TlbEntry *e; 610 611 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 612 priv, hpriv, red, lsu_dm, part_id); 613 614 if (implicit) { 615 if (tl > 0) { 616 asi = ASI_N; 617 ct = Nucleus; 618 context = 0; 619 } else { 620 asi = ASI_P; 621 ct = Primary; 622 context = pri_context; 623 } 624 } else { 625 // We need to check for priv level/asi priv 626 if (!priv && !hpriv && !asiIsUnPriv(asi)) { 627 // It appears that context should be Nucleus in these cases? 628 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 629 return new PrivilegedAction; 630 } 631 632 if (!hpriv && asiIsHPriv(asi)) { 633 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 634 return new DataAccessException; 635 } 636 637 if (asiIsPrimary(asi)) { 638 context = pri_context; 639 ct = Primary; 640 } else if (asiIsSecondary(asi)) { 641 context = sec_context; 642 ct = Secondary; 643 } else if (asiIsNucleus(asi)) { 644 ct = Nucleus; 645 context = 0; 646 } else { // ???? 647 ct = Primary; 648 context = pri_context; 649 } 650 } 651 652 if (!implicit && asi != ASI_P && asi != ASI_S) { 653 if (asiIsLittle(asi)) 654 panic("Little Endian ASIs not supported\n"); 655 656 //XXX It's unclear from looking at the documentation how a no fault 657 // load differs from a regular one, other than what happens concerning 658 // nfo and e bits in the TTE 659// if (asiIsNoFault(asi)) 660// panic("No Fault ASIs not supported\n"); 661 662 if (asiIsPartialStore(asi)) 663 panic("Partial Store ASIs not supported\n"); 664 665 if (asiIsCmt(asi)) 666 panic("Cmt ASI registers not implmented\n"); 667 668 if (asiIsInterrupt(asi)) 669 goto handleIntRegAccess; 670 if (asiIsMmu(asi)) 671 goto handleMmuRegAccess; 672 if (asiIsScratchPad(asi)) 673 goto handleScratchRegAccess; 674 if (asiIsQueue(asi)) 675 goto handleQueueRegAccess; 676 if (asiIsSparcError(asi)) 677 goto handleSparcErrorRegAccess; 678 679 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 680 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 681 panic("Accessing ASI %#X. Should we?\n", asi); 682 } 683 684 // If the asi is unaligned trap 685 if (unaligned) { 686 writeSfsr(vaddr, false, ct, false, OtherFault, asi); 687 return new MemAddressNotAligned; 688 } 689 690 if (addr_mask) 691 vaddr = vaddr & VAddrAMask; 692 693 if (!validVirtualAddress(vaddr, addr_mask)) { 694 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 695 return new DataAccessException; 696 } 697 698 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 699 real = true; 700 context = 0; 701 } 702 703 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 704 req->setPaddr(vaddr & PAddrImplMask); 705 return NoFault; 706 } 707 708 e = lookup(vaddr, part_id, real, context); 709 710 if (e == NULL || !e->valid) { 711 writeTagAccess(vaddr, context); 712 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 713 if (real) { 714 return new DataRealTranslationMiss; 715 } else { 716 if (FullSystem) 717 return new FastDataAccessMMUMiss; 718 else 719 return new FastDataAccessMMUMiss(req->getVaddr()); 720 } 721 722 } 723 724 if (!priv && e->pte.priv()) { 725 writeTagAccess(vaddr, context); 726 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 727 return new DataAccessException; 728 } 729 730 if (write && !e->pte.writable()) { 731 writeTagAccess(vaddr, context); 732 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 733 return new FastDataAccessProtection; 734 } 735 736 if (e->pte.nofault() && !asiIsNoFault(asi)) { 737 writeTagAccess(vaddr, context); 738 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 739 return new DataAccessException; 740 } 741 742 if (e->pte.sideffect() && asiIsNoFault(asi)) { 743 writeTagAccess(vaddr, context); 744 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 745 return new DataAccessException; 746 } 747 748 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 749 req->setFlags(Request::UNCACHEABLE); 750 751 // cache translation date for next translation 752 cacheState = tlbdata; 753 if (!cacheValid) { 754 cacheEntry[1] = NULL; 755 cacheEntry[0] = NULL; 756 } 757 758 if (cacheEntry[0] != e && cacheEntry[1] != e) { 759 cacheEntry[1] = cacheEntry[0]; 760 cacheEntry[0] = e; 761 cacheAsi[1] = cacheAsi[0]; 762 cacheAsi[0] = asi; 763 if (implicit) 764 cacheAsi[0] = (ASI)0; 765 } 766 cacheValid = true; 767 req->setPaddr(e->pte.translate(vaddr)); 768 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 769 return NoFault; 770 771 /** Normal flow ends here. */ 772handleIntRegAccess: 773 if (!hpriv) { 774 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 775 if (priv) 776 return new DataAccessException; 777 else 778 return new PrivilegedAction; 779 } 780 781 if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 782 (asi == ASI_SWVR_UDB_INTR_R && write)) { 783 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 784 return new DataAccessException; 785 } 786 787 goto regAccessOk; 788 789 790handleScratchRegAccess: 791 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 792 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 793 return new DataAccessException; 794 } 795 goto regAccessOk; 796 797handleQueueRegAccess: 798 if (!priv && !hpriv) { 799 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 800 return new PrivilegedAction; 801 } 802 if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 803 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 804 return new DataAccessException; 805 } 806 goto regAccessOk; 807 808handleSparcErrorRegAccess: 809 if (!hpriv) { 810 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 811 if (priv) 812 return new DataAccessException; 813 else 814 return new PrivilegedAction; 815 } 816 goto regAccessOk; 817 818 819regAccessOk: 820handleMmuRegAccess: 821 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 822 req->setFlags(Request::MMAPPED_IPR); 823 req->setPaddr(req->getVaddr()); 824 return NoFault; 825}; 826 827Fault 828TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 829{ 830 if (mode == Execute) 831 return translateInst(req, tc); 832 else 833 return translateData(req, tc, mode == Write); 834} 835 836void 837TLB::translateTiming(RequestPtr req, ThreadContext *tc, 838 Translation *translation, Mode mode) 839{ 840 assert(translation); 841 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 842} 843 844Fault 845TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 846{ 847 panic("Not implemented\n"); 848 return NoFault; 849} 850 851Tick 852TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 853{ 854 Addr va = pkt->getAddr(); 855 ASI asi = (ASI)pkt->req->getAsi(); 856 uint64_t temp; 857 858 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 859 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 860 861 TLB *itb = tc->getITBPtr(); 862 863 switch (asi) { 864 case ASI_LSU_CONTROL_REG: 865 assert(va == 0); 866 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 867 break; 868 case ASI_MMU: 869 switch (va) { 870 case 0x8: 871 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 872 break; 873 case 0x10: 874 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 875 break; 876 default: 877 goto doMmuReadError; 878 } 879 break; 880 case ASI_QUEUE: 881 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 882 (va >> 4) - 0x3c)); 883 break; 884 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 885 assert(va == 0); 886 pkt->set(c0_tsb_ps0); 887 break; 888 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 889 assert(va == 0); 890 pkt->set(c0_tsb_ps1); 891 break; 892 case ASI_DMMU_CTXT_ZERO_CONFIG: 893 assert(va == 0); 894 pkt->set(c0_config); 895 break; 896 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 897 assert(va == 0); 898 pkt->set(itb->c0_tsb_ps0); 899 break; 900 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 901 assert(va == 0); 902 pkt->set(itb->c0_tsb_ps1); 903 break; 904 case ASI_IMMU_CTXT_ZERO_CONFIG: 905 assert(va == 0); 906 pkt->set(itb->c0_config); 907 break; 908 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 909 assert(va == 0); 910 pkt->set(cx_tsb_ps0); 911 break; 912 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 913 assert(va == 0); 914 pkt->set(cx_tsb_ps1); 915 break; 916 case ASI_DMMU_CTXT_NONZERO_CONFIG: 917 assert(va == 0); 918 pkt->set(cx_config); 919 break; 920 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 921 assert(va == 0); 922 pkt->set(itb->cx_tsb_ps0); 923 break; 924 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 925 assert(va == 0); 926 pkt->set(itb->cx_tsb_ps1); 927 break; 928 case ASI_IMMU_CTXT_NONZERO_CONFIG: 929 assert(va == 0); 930 pkt->set(itb->cx_config); 931 break; 932 case ASI_SPARC_ERROR_STATUS_REG: 933 pkt->set((uint64_t)0); 934 break; 935 case ASI_HYP_SCRATCHPAD: 936 case ASI_SCRATCHPAD: 937 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 938 break; 939 case ASI_IMMU: 940 switch (va) { 941 case 0x0: 942 temp = itb->tag_access; 943 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 944 break; 945 case 0x18: 946 pkt->set(itb->sfsr); 947 break; 948 case 0x30: 949 pkt->set(itb->tag_access); 950 break; 951 default: 952 goto doMmuReadError; 953 } 954 break; 955 case ASI_DMMU: 956 switch (va) { 957 case 0x0: 958 temp = tag_access; 959 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 960 break; 961 case 0x18: 962 pkt->set(sfsr); 963 break; 964 case 0x20: 965 pkt->set(sfar); 966 break; 967 case 0x30: 968 pkt->set(tag_access); 969 break; 970 case 0x80: 971 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 972 break; 973 default: 974 goto doMmuReadError; 975 } 976 break; 977 case ASI_DMMU_TSB_PS0_PTR_REG: 978 pkt->set(MakeTsbPtr(Ps0, 979 tag_access, 980 c0_tsb_ps0, 981 c0_config, 982 cx_tsb_ps0, 983 cx_config)); 984 break; 985 case ASI_DMMU_TSB_PS1_PTR_REG: 986 pkt->set(MakeTsbPtr(Ps1, 987 tag_access, 988 c0_tsb_ps1, 989 c0_config, 990 cx_tsb_ps1, 991 cx_config)); 992 break; 993 case ASI_IMMU_TSB_PS0_PTR_REG: 994 pkt->set(MakeTsbPtr(Ps0, 995 itb->tag_access, 996 itb->c0_tsb_ps0, 997 itb->c0_config, 998 itb->cx_tsb_ps0, 999 itb->cx_config)); 1000 break; 1001 case ASI_IMMU_TSB_PS1_PTR_REG: 1002 pkt->set(MakeTsbPtr(Ps1, 1003 itb->tag_access, 1004 itb->c0_tsb_ps1, 1005 itb->c0_config, 1006 itb->cx_tsb_ps1, 1007 itb->cx_config)); 1008 break; 1009 case ASI_SWVR_INTR_RECEIVE: 1010 { 1011 SparcISA::Interrupts * interrupts = 1012 dynamic_cast<SparcISA::Interrupts *>( 1013 tc->getCpuPtr()->getInterruptController()); 1014 pkt->set(interrupts->get_vec(IT_INT_VEC)); 1015 } 1016 break; 1017 case ASI_SWVR_UDB_INTR_R: 1018 { 1019 SparcISA::Interrupts * interrupts = 1020 dynamic_cast<SparcISA::Interrupts *>( 1021 tc->getCpuPtr()->getInterruptController()); 1022 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 1023 tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); 1024 pkt->set(temp); 1025 } 1026 break; 1027 default: 1028doMmuReadError: 1029 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 1030 (uint32_t)asi, va); 1031 } 1032 pkt->makeAtomicResponse(); 1033 return tc->getCpuPtr()->ticks(1); 1034} 1035 1036Tick 1037TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1038{ 1039 uint64_t data = pkt->get<uint64_t>(); 1040 Addr va = pkt->getAddr(); 1041 ASI asi = (ASI)pkt->req->getAsi(); 1042 1043 Addr ta_insert; 1044 Addr va_insert; 1045 Addr ct_insert; 1046 int part_insert; 1047 int entry_insert = -1; 1048 bool real_insert; 1049 bool ignore; 1050 int part_id; 1051 int ctx_id; 1052 PageTableEntry pte; 1053 1054 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1055 (uint32_t)asi, va, data); 1056 1057 TLB *itb = tc->getITBPtr(); 1058 1059 switch (asi) { 1060 case ASI_LSU_CONTROL_REG: 1061 assert(va == 0); 1062 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 1063 break; 1064 case ASI_MMU: 1065 switch (va) { 1066 case 0x8: 1067 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 1068 break; 1069 case 0x10: 1070 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 1071 break; 1072 default: 1073 goto doMmuWriteError; 1074 } 1075 break; 1076 case ASI_QUEUE: 1077 assert(mbits(data,13,6) == data); 1078 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 1079 (va >> 4) - 0x3c, data); 1080 break; 1081 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1082 assert(va == 0); 1083 c0_tsb_ps0 = data; 1084 break; 1085 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1086 assert(va == 0); 1087 c0_tsb_ps1 = data; 1088 break; 1089 case ASI_DMMU_CTXT_ZERO_CONFIG: 1090 assert(va == 0); 1091 c0_config = data; 1092 break; 1093 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1094 assert(va == 0); 1095 itb->c0_tsb_ps0 = data; 1096 break; 1097 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1098 assert(va == 0); 1099 itb->c0_tsb_ps1 = data; 1100 break; 1101 case ASI_IMMU_CTXT_ZERO_CONFIG: 1102 assert(va == 0); 1103 itb->c0_config = data; 1104 break; 1105 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1106 assert(va == 0); 1107 cx_tsb_ps0 = data; 1108 break; 1109 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1110 assert(va == 0); 1111 cx_tsb_ps1 = data; 1112 break; 1113 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1114 assert(va == 0); 1115 cx_config = data; 1116 break; 1117 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1118 assert(va == 0); 1119 itb->cx_tsb_ps0 = data; 1120 break; 1121 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1122 assert(va == 0); 1123 itb->cx_tsb_ps1 = data; 1124 break; 1125 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1126 assert(va == 0); 1127 itb->cx_config = data; 1128 break; 1129 case ASI_SPARC_ERROR_EN_REG: 1130 case ASI_SPARC_ERROR_STATUS_REG: 1131 inform("Ignoring write to SPARC ERROR regsiter\n"); 1132 break; 1133 case ASI_HYP_SCRATCHPAD: 1134 case ASI_SCRATCHPAD: 1135 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1136 break; 1137 case ASI_IMMU: 1138 switch (va) { 1139 case 0x18: 1140 itb->sfsr = data; 1141 break; 1142 case 0x30: 1143 sext<59>(bits(data, 59,0)); 1144 itb->tag_access = data; 1145 break; 1146 default: 1147 goto doMmuWriteError; 1148 } 1149 break; 1150 case ASI_ITLB_DATA_ACCESS_REG: 1151 entry_insert = bits(va, 8,3); 1152 case ASI_ITLB_DATA_IN_REG: 1153 assert(entry_insert != -1 || mbits(va,10,9) == va); 1154 ta_insert = itb->tag_access; 1155 va_insert = mbits(ta_insert, 63,13); 1156 ct_insert = mbits(ta_insert, 12,0); 1157 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1158 real_insert = bits(va, 9,9); 1159 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1160 PageTableEntry::sun4u); 1161 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1162 pte, entry_insert); 1163 break; 1164 case ASI_DTLB_DATA_ACCESS_REG: 1165 entry_insert = bits(va, 8,3); 1166 case ASI_DTLB_DATA_IN_REG: 1167 assert(entry_insert != -1 || mbits(va,10,9) == va); 1168 ta_insert = tag_access; 1169 va_insert = mbits(ta_insert, 63,13); 1170 ct_insert = mbits(ta_insert, 12,0); 1171 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1172 real_insert = bits(va, 9,9); 1173 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1174 PageTableEntry::sun4u); 1175 insert(va_insert, part_insert, ct_insert, real_insert, pte, 1176 entry_insert); 1177 break; 1178 case ASI_IMMU_DEMAP: 1179 ignore = false; 1180 ctx_id = -1; 1181 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1182 switch (bits(va,5,4)) { 1183 case 0: 1184 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1185 break; 1186 case 1: 1187 ignore = true; 1188 break; 1189 case 3: 1190 ctx_id = 0; 1191 break; 1192 default: 1193 ignore = true; 1194 } 1195 1196 switch (bits(va,7,6)) { 1197 case 0: // demap page 1198 if (!ignore) 1199 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1200 bits(va,9,9), ctx_id); 1201 break; 1202 case 1: // demap context 1203 if (!ignore) 1204 tc->getITBPtr()->demapContext(part_id, ctx_id); 1205 break; 1206 case 2: 1207 tc->getITBPtr()->demapAll(part_id); 1208 break; 1209 default: 1210 panic("Invalid type for IMMU demap\n"); 1211 } 1212 break; 1213 case ASI_DMMU: 1214 switch (va) { 1215 case 0x18: 1216 sfsr = data; 1217 break; 1218 case 0x30: 1219 sext<59>(bits(data, 59,0)); 1220 tag_access = data; 1221 break; 1222 case 0x80: 1223 tc->setMiscReg(MISCREG_MMU_PART_ID, data); 1224 break; 1225 default: 1226 goto doMmuWriteError; 1227 } 1228 break; 1229 case ASI_DMMU_DEMAP: 1230 ignore = false; 1231 ctx_id = -1; 1232 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1233 switch (bits(va,5,4)) { 1234 case 0: 1235 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1236 break; 1237 case 1: 1238 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 1239 break; 1240 case 3: 1241 ctx_id = 0; 1242 break; 1243 default: 1244 ignore = true; 1245 } 1246 1247 switch (bits(va,7,6)) { 1248 case 0: // demap page 1249 if (!ignore) 1250 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1251 break; 1252 case 1: // demap context 1253 if (!ignore) 1254 demapContext(part_id, ctx_id); 1255 break; 1256 case 2: 1257 demapAll(part_id); 1258 break; 1259 default: 1260 panic("Invalid type for IMMU demap\n"); 1261 } 1262 break; 1263 case ASI_SWVR_INTR_RECEIVE: 1264 { 1265 int msb; 1266 // clear all the interrupts that aren't set in the write 1267 SparcISA::Interrupts * interrupts = 1268 dynamic_cast<SparcISA::Interrupts *>( 1269 tc->getCpuPtr()->getInterruptController()); 1270 while (interrupts->get_vec(IT_INT_VEC) & data) { 1271 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 1272 tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); 1273 } 1274 } 1275 break; 1276 case ASI_SWVR_UDB_INTR_W: 1277 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 1278 postInterrupt(bits(data, 5, 0), 0); 1279 break; 1280 default: 1281doMmuWriteError: 1282 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 1283 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 1284 } 1285 pkt->makeAtomicResponse(); 1286 return tc->getCpuPtr()->ticks(1); 1287} 1288 1289void 1290TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1291{ 1292 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 1293 TLB * itb = tc->getITBPtr(); 1294 ptrs[0] = MakeTsbPtr(Ps0, tag_access, 1295 c0_tsb_ps0, 1296 c0_config, 1297 cx_tsb_ps0, 1298 cx_config); 1299 ptrs[1] = MakeTsbPtr(Ps1, tag_access, 1300 c0_tsb_ps1, 1301 c0_config, 1302 cx_tsb_ps1, 1303 cx_config); 1304 ptrs[2] = MakeTsbPtr(Ps0, tag_access, 1305 itb->c0_tsb_ps0, 1306 itb->c0_config, 1307 itb->cx_tsb_ps0, 1308 itb->cx_config); 1309 ptrs[3] = MakeTsbPtr(Ps1, tag_access, 1310 itb->c0_tsb_ps1, 1311 itb->c0_config, 1312 itb->cx_tsb_ps1, 1313 itb->cx_config); 1314} 1315 1316uint64_t 1317TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1318 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 1319{ 1320 uint64_t tsb; 1321 uint64_t config; 1322 1323 if (bits(tag_access, 12,0) == 0) { 1324 tsb = c0_tsb; 1325 config = c0_config; 1326 } else { 1327 tsb = cX_tsb; 1328 config = cX_config; 1329 } 1330 1331 uint64_t ptr = mbits(tsb,63,13); 1332 bool split = bits(tsb,12,12); 1333 int tsb_size = bits(tsb,3,0); 1334 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 1335 1336 if (ps == Ps1 && split) 1337 ptr |= ULL(1) << (13 + tsb_size); 1338 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 1339 1340 return ptr; 1341} 1342 1343void 1344TLB::serialize(std::ostream &os) 1345{ 1346 SERIALIZE_SCALAR(size); 1347 SERIALIZE_SCALAR(usedEntries); 1348 SERIALIZE_SCALAR(lastReplaced); 1349 1350 // convert the pointer based free list into an index based one 1351 int *free_list = (int*)malloc(sizeof(int) * size); 1352 int cntr = 0; 1353 std::list<TlbEntry*>::iterator i; 1354 i = freeList.begin(); 1355 while (i != freeList.end()) { 1356 free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 1357 i++; 1358 } 1359 SERIALIZE_SCALAR(cntr); 1360 SERIALIZE_ARRAY(free_list, cntr); 1361 1362 SERIALIZE_SCALAR(c0_tsb_ps0); 1363 SERIALIZE_SCALAR(c0_tsb_ps1); 1364 SERIALIZE_SCALAR(c0_config); 1365 SERIALIZE_SCALAR(cx_tsb_ps0); 1366 SERIALIZE_SCALAR(cx_tsb_ps1); 1367 SERIALIZE_SCALAR(cx_config); 1368 SERIALIZE_SCALAR(sfsr); 1369 SERIALIZE_SCALAR(tag_access); 1370 1371 for (int x = 0; x < size; x++) { 1372 nameOut(os, csprintf("%s.PTE%d", name(), x)); 1373 tlb[x].serialize(os); 1374 } 1375 SERIALIZE_SCALAR(sfar); 1376} 1377 1378void 1379TLB::unserialize(Checkpoint *cp, const std::string §ion) 1380{ 1381 int oldSize; 1382 1383 paramIn(cp, section, "size", oldSize); 1384 if (oldSize != size) 1385 panic("Don't support unserializing different sized TLBs\n"); 1386 UNSERIALIZE_SCALAR(usedEntries); 1387 UNSERIALIZE_SCALAR(lastReplaced); 1388 1389 int cntr; 1390 UNSERIALIZE_SCALAR(cntr); 1391 1392 int *free_list = (int*)malloc(sizeof(int) * cntr); 1393 freeList.clear(); 1394 UNSERIALIZE_ARRAY(free_list, cntr); 1395 for (int x = 0; x < cntr; x++) 1396 freeList.push_back(&tlb[free_list[x]]); 1397 1398 UNSERIALIZE_SCALAR(c0_tsb_ps0); 1399 UNSERIALIZE_SCALAR(c0_tsb_ps1); 1400 UNSERIALIZE_SCALAR(c0_config); 1401 UNSERIALIZE_SCALAR(cx_tsb_ps0); 1402 UNSERIALIZE_SCALAR(cx_tsb_ps1); 1403 UNSERIALIZE_SCALAR(cx_config); 1404 UNSERIALIZE_SCALAR(sfsr); 1405 UNSERIALIZE_SCALAR(tag_access); 1406 1407 lookupTable.clear(); 1408 for (int x = 0; x < size; x++) { 1409 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1410 if (tlb[x].valid) 1411 lookupTable.insert(tlb[x].range, &tlb[x]); 1412 1413 } 1414 UNSERIALIZE_SCALAR(sfar); 1415} 1416 1417} // namespace SparcISA 1418 1419SparcISA::TLB * 1420SparcTLBParams::create() 1421{ 1422 return new SparcISA::TLB(this); 1423} 1424