tlb.cc revision 4090
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include <cstring> 32 33#include "arch/sparc/asi.hh" 34#include "arch/sparc/miscregfile.hh" 35#include "arch/sparc/tlb.hh" 36#include "base/bitfield.hh" 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39#include "cpu/base.hh" 40#include "mem/packet_access.hh" 41#include "mem/request.hh" 42#include "sim/builder.hh" 43 44/* @todo remove some of the magic constants. -- ali 45 * */ 46namespace SparcISA 47{ 48 49TLB::TLB(const std::string &name, int s) 50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 51 cacheValid(false) 52{ 53 // To make this work you'll have to change the hypervisor and OS 54 if (size > 64) 55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 56 57 tlb = new TlbEntry[size]; 58 std::memset(tlb, 0, sizeof(TlbEntry) * size); 59 60 for (int x = 0; x < size; x++) 61 freeList.push_back(&tlb[x]); 62} 63 64void 65TLB::clearUsedBits() 66{ 67 MapIter i; 68 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 69 TlbEntry *t = i->second; 70 if (!t->pte.locked()) { 71 t->used = false; 72 usedEntries--; 73 } 74 } 75} 76 77 78void 79TLB::insert(Addr va, int partition_id, int context_id, bool real, 80 const PageTableEntry& PTE, int entry) 81{ 82 83 84 MapIter i; 85 TlbEntry *new_entry = NULL; 86// TlbRange tr; 87 int x; 88 89 cacheValid = false; 90 va &= ~(PTE.size()-1); 91 /* tr.va = va; 92 tr.size = PTE.size() - 1; 93 tr.contextId = context_id; 94 tr.partitionId = partition_id; 95 tr.real = real; 96*/ 97 98 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 99 va, PTE.paddr(), partition_id, context_id, (int)real, entry); 100 101 // Demap any entry that conflicts 102 for (x = 0; x < size; x++) { 103 if (tlb[x].range.real == real && 104 tlb[x].range.partitionId == partition_id && 105 tlb[x].range.va < va + PTE.size() - 1 && 106 tlb[x].range.va + tlb[x].range.size >= va && 107 (real || tlb[x].range.contextId == context_id )) 108 { 109 if (tlb[x].valid) { 110 freeList.push_front(&tlb[x]); 111 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 112 113 tlb[x].valid = false; 114 if (tlb[x].used) { 115 tlb[x].used = false; 116 usedEntries--; 117 } 118 lookupTable.erase(tlb[x].range); 119 } 120 } 121 } 122 123 124/* 125 i = lookupTable.find(tr); 126 if (i != lookupTable.end()) { 127 i->second->valid = false; 128 if (i->second->used) { 129 i->second->used = false; 130 usedEntries--; 131 } 132 freeList.push_front(i->second); 133 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 134 i->second); 135 lookupTable.erase(i); 136 } 137*/ 138 139 if (entry != -1) { 140 assert(entry < size && entry >= 0); 141 new_entry = &tlb[entry]; 142 } else { 143 if (!freeList.empty()) { 144 new_entry = freeList.front(); 145 } else { 146 x = lastReplaced; 147 do { 148 ++x; 149 if (x == size) 150 x = 0; 151 if (x == lastReplaced) 152 goto insertAllLocked; 153 } while (tlb[x].pte.locked()); 154 lastReplaced = x; 155 new_entry = &tlb[x]; 156 } 157 /* 158 for (x = 0; x < size; x++) { 159 if (!tlb[x].valid || !tlb[x].used) { 160 new_entry = &tlb[x]; 161 break; 162 } 163 }*/ 164 } 165 166insertAllLocked: 167 // Update the last ently if their all locked 168 if (!new_entry) { 169 new_entry = &tlb[size-1]; 170 } 171 172 freeList.remove(new_entry); 173 if (new_entry->valid && new_entry->used) 174 usedEntries--; 175 if (new_entry->valid) 176 lookupTable.erase(new_entry->range); 177 178 179 assert(PTE.valid()); 180 new_entry->range.va = va; 181 new_entry->range.size = PTE.size() - 1; 182 new_entry->range.partitionId = partition_id; 183 new_entry->range.contextId = context_id; 184 new_entry->range.real = real; 185 new_entry->pte = PTE; 186 new_entry->used = true;; 187 new_entry->valid = true; 188 usedEntries++; 189 190 191 192 i = lookupTable.insert(new_entry->range, new_entry); 193 assert(i != lookupTable.end()); 194 195 // If all entries have there used bit set, clear it on them all, but the 196 // one we just inserted 197 if (usedEntries == size) { 198 clearUsedBits(); 199 new_entry->used = true; 200 usedEntries++; 201 } 202 203} 204 205 206TlbEntry* 207TLB::lookup(Addr va, int partition_id, bool real, int context_id, bool 208 update_used) 209{ 210 MapIter i; 211 TlbRange tr; 212 TlbEntry *t; 213 214 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 215 va, partition_id, context_id, real); 216 // Assemble full address structure 217 tr.va = va; 218 tr.size = MachineBytes; 219 tr.contextId = context_id; 220 tr.partitionId = partition_id; 221 tr.real = real; 222 223 // Try to find the entry 224 i = lookupTable.find(tr); 225 if (i == lookupTable.end()) { 226 DPRINTF(TLB, "TLB: No valid entry found\n"); 227 return NULL; 228 } 229 230 // Mark the entries used bit and clear other used bits in needed 231 t = i->second; 232 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 233 t->pte.size()); 234 235 // Update the used bits only if this is a real access (not a fake one from 236 // virttophys() 237 if (!t->used && update_used) { 238 t->used = true; 239 usedEntries++; 240 if (usedEntries == size) { 241 clearUsedBits(); 242 t->used = true; 243 usedEntries++; 244 } 245 } 246 247 return t; 248} 249 250void 251TLB::dumpAll() 252{ 253 MapIter i; 254 for (int x = 0; x < size; x++) { 255 if (tlb[x].valid) { 256 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 257 x, tlb[x].range.partitionId, tlb[x].range.contextId, 258 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 259 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 260 } 261 } 262} 263 264void 265TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 266{ 267 TlbRange tr; 268 MapIter i; 269 270 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 271 va, partition_id, context_id, real); 272 273 cacheValid = false; 274 275 // Assemble full address structure 276 tr.va = va; 277 tr.size = MachineBytes; 278 tr.contextId = context_id; 279 tr.partitionId = partition_id; 280 tr.real = real; 281 282 // Demap any entry that conflicts 283 i = lookupTable.find(tr); 284 if (i != lookupTable.end()) { 285 DPRINTF(IPR, "TLB: Demapped page\n"); 286 i->second->valid = false; 287 if (i->second->used) { 288 i->second->used = false; 289 usedEntries--; 290 } 291 freeList.push_front(i->second); 292 lookupTable.erase(i); 293 } 294} 295 296void 297TLB::demapContext(int partition_id, int context_id) 298{ 299 int x; 300 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 301 partition_id, context_id); 302 cacheValid = false; 303 for (x = 0; x < size; x++) { 304 if (tlb[x].range.contextId == context_id && 305 tlb[x].range.partitionId == partition_id) { 306 if (tlb[x].valid == true) { 307 freeList.push_front(&tlb[x]); 308 } 309 tlb[x].valid = false; 310 if (tlb[x].used) { 311 tlb[x].used = false; 312 usedEntries--; 313 } 314 lookupTable.erase(tlb[x].range); 315 } 316 } 317} 318 319void 320TLB::demapAll(int partition_id) 321{ 322 int x; 323 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 324 cacheValid = false; 325 for (x = 0; x < size; x++) { 326 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 327 if (tlb[x].valid == true){ 328 freeList.push_front(&tlb[x]); 329 } 330 tlb[x].valid = false; 331 if (tlb[x].used) { 332 tlb[x].used = false; 333 usedEntries--; 334 } 335 lookupTable.erase(tlb[x].range); 336 } 337 } 338} 339 340void 341TLB::invalidateAll() 342{ 343 int x; 344 cacheValid = false; 345 346 freeList.clear(); 347 lookupTable.clear(); 348 for (x = 0; x < size; x++) { 349 if (tlb[x].valid == true) 350 freeList.push_back(&tlb[x]); 351 tlb[x].valid = false; 352 tlb[x].used = false; 353 } 354 usedEntries = 0; 355} 356 357uint64_t 358TLB::TteRead(int entry) { 359 if (entry >= size) 360 panic("entry: %d\n", entry); 361 362 assert(entry < size); 363 if (tlb[entry].valid) 364 return tlb[entry].pte(); 365 else 366 return (uint64_t)-1ll; 367} 368 369uint64_t 370TLB::TagRead(int entry) { 371 assert(entry < size); 372 uint64_t tag; 373 if (!tlb[entry].valid) 374 return (uint64_t)-1ll; 375 376 tag = tlb[entry].range.contextId; 377 tag |= tlb[entry].range.va; 378 tag |= (uint64_t)tlb[entry].range.partitionId << 61; 379 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 380 tag |= (uint64_t)~tlb[entry].pte._size() << 56; 381 return tag; 382} 383 384bool 385TLB::validVirtualAddress(Addr va, bool am) 386{ 387 if (am) 388 return true; 389 if (va >= StartVAddrHole && va <= EndVAddrHole) 390 return false; 391 return true; 392} 393 394void 395TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 396 bool se, FaultTypes ft, int asi) 397{ 398 uint64_t sfsr; 399 sfsr = tc->readMiscReg(reg); 400 401 if (sfsr & 0x1) 402 sfsr = 0x3; 403 else 404 sfsr = 1; 405 406 if (write) 407 sfsr |= 1 << 2; 408 sfsr |= ct << 4; 409 if (se) 410 sfsr |= 1 << 6; 411 sfsr |= ft << 7; 412 sfsr |= asi << 16; 413 tc->setMiscRegWithEffect(reg, sfsr); 414} 415 416void 417TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 418{ 419 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 420 va, context, mbits(va, 63,13) | mbits(context,12,0)); 421 422 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 423} 424 425void 426ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 427 bool se, FaultTypes ft, int asi) 428{ 429 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 430 (int)write, ct, ft, asi); 431 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 432} 433 434void 435ITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 436{ 437 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 438} 439 440void 441DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 442 bool se, FaultTypes ft, int asi) 443{ 444 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 445 a, (int)write, ct, ft, asi); 446 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 447 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 448} 449 450void 451DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 452{ 453 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 454} 455 456 457 458Fault 459ITB::translate(RequestPtr &req, ThreadContext *tc) 460{ 461 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 462 463 Addr vaddr = req->getVaddr(); 464 TlbEntry *e; 465 466 assert(req->getAsi() == ASI_IMPLICIT); 467 468 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 469 vaddr, req->getSize()); 470 471 // Be fast if we can! 472 if (cacheValid && cacheState == tlbdata) { 473 if (cacheEntry) { 474 if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 475 cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 476 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 477 vaddr & cacheEntry->pte.size()-1 ); 478 return NoFault; 479 } 480 } else { 481 req->setPaddr(vaddr & PAddrImplMask); 482 return NoFault; 483 } 484 } 485 486 bool hpriv = bits(tlbdata,0,0); 487 bool red = bits(tlbdata,1,1); 488 bool priv = bits(tlbdata,2,2); 489 bool addr_mask = bits(tlbdata,3,3); 490 bool lsu_im = bits(tlbdata,4,4); 491 492 int part_id = bits(tlbdata,15,8); 493 int tl = bits(tlbdata,18,16); 494 int pri_context = bits(tlbdata,47,32); 495 int context; 496 ContextType ct; 497 int asi; 498 bool real = false; 499 500 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 501 priv, hpriv, red, lsu_im, part_id); 502 503 if (tl > 0) { 504 asi = ASI_N; 505 ct = Nucleus; 506 context = 0; 507 } else { 508 asi = ASI_P; 509 ct = Primary; 510 context = pri_context; 511 } 512 513 if ( hpriv || red ) { 514 cacheValid = true; 515 cacheState = tlbdata; 516 cacheEntry = NULL; 517 req->setPaddr(vaddr & PAddrImplMask); 518 return NoFault; 519 } 520 521 // If the access is unaligned trap 522 if (vaddr & 0x3) { 523 writeSfsr(tc, false, ct, false, OtherFault, asi); 524 return new MemAddressNotAligned; 525 } 526 527 if (addr_mask) 528 vaddr = vaddr & VAddrAMask; 529 530 if (!validVirtualAddress(vaddr, addr_mask)) { 531 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 532 return new InstructionAccessException; 533 } 534 535 if (!lsu_im) { 536 e = lookup(vaddr, part_id, true); 537 real = true; 538 context = 0; 539 } else { 540 e = lookup(vaddr, part_id, false, context); 541 } 542 543 if (e == NULL || !e->valid) { 544 writeTagAccess(tc, vaddr, context); 545 if (real) 546 return new InstructionRealTranslationMiss; 547 else 548 return new FastInstructionAccessMMUMiss; 549 } 550 551 // were not priviledged accesing priv page 552 if (!priv && e->pte.priv()) { 553 writeTagAccess(tc, vaddr, context); 554 writeSfsr(tc, false, ct, false, PrivViolation, asi); 555 return new InstructionAccessException; 556 } 557 558 // cache translation date for next translation 559 cacheValid = true; 560 cacheState = tlbdata; 561 cacheEntry = e; 562 563 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 564 vaddr & e->pte.size()-1 ); 565 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 566 return NoFault; 567} 568 569 570 571Fault 572DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 573{ 574 /* @todo this could really use some profiling and fixing to make it faster! */ 575 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 576 Addr vaddr = req->getVaddr(); 577 Addr size = req->getSize(); 578 ASI asi; 579 asi = (ASI)req->getAsi(); 580 bool implicit = false; 581 bool hpriv = bits(tlbdata,0,0); 582 583 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 584 vaddr, size, asi); 585 586 if (lookupTable.size() != 64 - freeList.size()) 587 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 588 freeList.size()); 589 if (asi == ASI_IMPLICIT) 590 implicit = true; 591 592 if (hpriv && implicit) { 593 req->setPaddr(vaddr & PAddrImplMask); 594 return NoFault; 595 } 596 597 // Be fast if we can! 598 if (cacheValid && cacheState == tlbdata) { 599 600 601 602 if (cacheEntry[0]) { 603 TlbEntry *ce = cacheEntry[0]; 604 Addr ce_va = ce->range.va; 605 if (cacheAsi[0] == asi && 606 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 607 (!write || ce->pte.writable())) { 608 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 609 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 610 req->setFlags(req->getFlags() | UNCACHEABLE); 611 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 612 return NoFault; 613 } // if matched 614 } // if cache entry valid 615 if (cacheEntry[1]) { 616 TlbEntry *ce = cacheEntry[1]; 617 Addr ce_va = ce->range.va; 618 if (cacheAsi[1] == asi && 619 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 620 (!write || ce->pte.writable())) { 621 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 622 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 623 req->setFlags(req->getFlags() | UNCACHEABLE); 624 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 625 return NoFault; 626 } // if matched 627 } // if cache entry valid 628 } 629 630 bool red = bits(tlbdata,1,1); 631 bool priv = bits(tlbdata,2,2); 632 bool addr_mask = bits(tlbdata,3,3); 633 bool lsu_dm = bits(tlbdata,5,5); 634 635 int part_id = bits(tlbdata,15,8); 636 int tl = bits(tlbdata,18,16); 637 int pri_context = bits(tlbdata,47,32); 638 int sec_context = bits(tlbdata,63,48); 639 640 bool real = false; 641 ContextType ct = Primary; 642 int context = 0; 643 644 TlbEntry *e; 645 646 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 647 priv, hpriv, red, lsu_dm, part_id); 648 649 if (implicit) { 650 if (tl > 0) { 651 asi = ASI_N; 652 ct = Nucleus; 653 context = 0; 654 } else { 655 asi = ASI_P; 656 ct = Primary; 657 context = pri_context; 658 } 659 } else { 660 // We need to check for priv level/asi priv 661 if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 662 // It appears that context should be Nucleus in these cases? 663 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 664 return new PrivilegedAction; 665 } 666 667 if (!hpriv && AsiIsHPriv(asi)) { 668 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 669 return new DataAccessException; 670 } 671 672 if (AsiIsPrimary(asi)) { 673 context = pri_context; 674 ct = Primary; 675 } else if (AsiIsSecondary(asi)) { 676 context = sec_context; 677 ct = Secondary; 678 } else if (AsiIsNucleus(asi)) { 679 ct = Nucleus; 680 context = 0; 681 } else { // ???? 682 ct = Primary; 683 context = pri_context; 684 } 685 } 686 687 if (!implicit && asi != ASI_P && asi != ASI_S) { 688 if (AsiIsLittle(asi)) 689 panic("Little Endian ASIs not supported\n"); 690 if (AsiIsNoFault(asi)) 691 panic("No Fault ASIs not supported\n"); 692 693 if (AsiIsPartialStore(asi)) 694 panic("Partial Store ASIs not supported\n"); 695 if (AsiIsInterrupt(asi)) 696 panic("Interrupt ASIs not supported\n"); 697 698 if (AsiIsMmu(asi)) 699 goto handleMmuRegAccess; 700 if (AsiIsScratchPad(asi)) 701 goto handleScratchRegAccess; 702 if (AsiIsQueue(asi)) 703 goto handleQueueRegAccess; 704 if (AsiIsSparcError(asi)) 705 goto handleSparcErrorRegAccess; 706 707 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 708 !AsiIsTwin(asi) && !AsiIsBlock(asi)) 709 panic("Accessing ASI %#X. Should we?\n", asi); 710 } 711 712 // If the asi is unaligned trap 713 if (vaddr & size-1) { 714 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 715 return new MemAddressNotAligned; 716 } 717 718 if (addr_mask) 719 vaddr = vaddr & VAddrAMask; 720 721 if (!validVirtualAddress(vaddr, addr_mask)) { 722 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 723 return new DataAccessException; 724 } 725 726 727 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 728 real = true; 729 context = 0; 730 }; 731 732 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 733 req->setPaddr(vaddr & PAddrImplMask); 734 return NoFault; 735 } 736 737 e = lookup(vaddr, part_id, real, context); 738 739 if (e == NULL || !e->valid) { 740 writeTagAccess(tc, vaddr, context); 741 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 742 if (real) 743 return new DataRealTranslationMiss; 744 else 745 return new FastDataAccessMMUMiss; 746 747 } 748 749 if (!priv && e->pte.priv()) { 750 writeTagAccess(tc, vaddr, context); 751 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 752 return new DataAccessException; 753 } 754 755 if (write && !e->pte.writable()) { 756 writeTagAccess(tc, vaddr, context); 757 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 758 return new FastDataAccessProtection; 759 } 760 761 if (e->pte.nofault() && !AsiIsNoFault(asi)) { 762 writeTagAccess(tc, vaddr, context); 763 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 764 return new DataAccessException; 765 } 766 767 if (e->pte.sideffect() && AsiIsNoFault(asi)) { 768 writeTagAccess(tc, vaddr, context); 769 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 770 return new DataAccessException; 771 } 772 773 774 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 775 req->setFlags(req->getFlags() | UNCACHEABLE); 776 777 // cache translation date for next translation 778 cacheState = tlbdata; 779 if (!cacheValid) { 780 cacheEntry[1] = NULL; 781 cacheEntry[0] = NULL; 782 } 783 784 if (cacheEntry[0] != e && cacheEntry[1] != e) { 785 cacheEntry[1] = cacheEntry[0]; 786 cacheEntry[0] = e; 787 cacheAsi[1] = cacheAsi[0]; 788 cacheAsi[0] = asi; 789 if (implicit) 790 cacheAsi[0] = (ASI)0; 791 } 792 cacheValid = true; 793 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 794 vaddr & e->pte.size()-1); 795 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 796 return NoFault; 797 /** Normal flow ends here. */ 798 799handleScratchRegAccess: 800 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 801 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 802 return new DataAccessException; 803 } 804 goto regAccessOk; 805 806handleQueueRegAccess: 807 if (!priv && !hpriv) { 808 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 809 return new PrivilegedAction; 810 } 811 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 812 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 813 return new DataAccessException; 814 } 815 goto regAccessOk; 816 817handleSparcErrorRegAccess: 818 if (!hpriv) { 819 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 820 if (priv) 821 return new DataAccessException; 822 else 823 return new PrivilegedAction; 824 } 825 goto regAccessOk; 826 827 828regAccessOk: 829handleMmuRegAccess: 830 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 831 req->setMmapedIpr(true); 832 req->setPaddr(req->getVaddr()); 833 return NoFault; 834}; 835 836Tick 837DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 838{ 839 Addr va = pkt->getAddr(); 840 ASI asi = (ASI)pkt->req->getAsi(); 841 uint64_t temp; 842 843 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 844 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 845 846 switch (asi) { 847 case ASI_LSU_CONTROL_REG: 848 assert(va == 0); 849 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 850 break; 851 case ASI_MMU: 852 switch (va) { 853 case 0x8: 854 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 855 break; 856 case 0x10: 857 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 858 break; 859 default: 860 goto doMmuReadError; 861 } 862 break; 863 case ASI_QUEUE: 864 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 865 (va >> 4) - 0x3c)); 866 break; 867 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 868 assert(va == 0); 869 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 870 break; 871 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 872 assert(va == 0); 873 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 874 break; 875 case ASI_DMMU_CTXT_ZERO_CONFIG: 876 assert(va == 0); 877 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 878 break; 879 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 880 assert(va == 0); 881 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 882 break; 883 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 884 assert(va == 0); 885 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 886 break; 887 case ASI_IMMU_CTXT_ZERO_CONFIG: 888 assert(va == 0); 889 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 890 break; 891 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 892 assert(va == 0); 893 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 894 break; 895 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 896 assert(va == 0); 897 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 898 break; 899 case ASI_DMMU_CTXT_NONZERO_CONFIG: 900 assert(va == 0); 901 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 902 break; 903 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 904 assert(va == 0); 905 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 906 break; 907 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 908 assert(va == 0); 909 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 910 break; 911 case ASI_IMMU_CTXT_NONZERO_CONFIG: 912 assert(va == 0); 913 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 914 break; 915 case ASI_SPARC_ERROR_STATUS_REG: 916 pkt->set((uint64_t)0); 917 break; 918 case ASI_HYP_SCRATCHPAD: 919 case ASI_SCRATCHPAD: 920 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 921 break; 922 case ASI_IMMU: 923 switch (va) { 924 case 0x0: 925 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 926 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 927 break; 928 case 0x18: 929 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 930 break; 931 case 0x30: 932 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 933 break; 934 default: 935 goto doMmuReadError; 936 } 937 break; 938 case ASI_DMMU: 939 switch (va) { 940 case 0x0: 941 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 942 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 943 break; 944 case 0x18: 945 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 946 break; 947 case 0x20: 948 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 949 break; 950 case 0x30: 951 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 952 break; 953 case 0x80: 954 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 955 break; 956 default: 957 goto doMmuReadError; 958 } 959 break; 960 case ASI_DMMU_TSB_PS0_PTR_REG: 961 pkt->set(MakeTsbPtr(Ps0, 962 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), 963 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), 964 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 965 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), 966 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); 967 break; 968 case ASI_DMMU_TSB_PS1_PTR_REG: 969 pkt->set(MakeTsbPtr(Ps1, 970 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), 971 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), 972 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 973 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), 974 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); 975 break; 976 case ASI_IMMU_TSB_PS0_PTR_REG: 977 pkt->set(MakeTsbPtr(Ps0, 978 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), 979 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), 980 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 981 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), 982 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); 983 break; 984 case ASI_IMMU_TSB_PS1_PTR_REG: 985 pkt->set(MakeTsbPtr(Ps1, 986 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), 987 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), 988 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 989 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), 990 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); 991 break; 992 993 default: 994doMmuReadError: 995 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 996 (uint32_t)asi, va); 997 } 998 pkt->result = Packet::Success; 999 return tc->getCpuPtr()->cycles(1); 1000} 1001 1002Tick 1003DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1004{ 1005 uint64_t data = gtoh(pkt->get<uint64_t>()); 1006 Addr va = pkt->getAddr(); 1007 ASI asi = (ASI)pkt->req->getAsi(); 1008 1009 Addr ta_insert; 1010 Addr va_insert; 1011 Addr ct_insert; 1012 int part_insert; 1013 int entry_insert = -1; 1014 bool real_insert; 1015 bool ignore; 1016 int part_id; 1017 int ctx_id; 1018 PageTableEntry pte; 1019 1020 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1021 (uint32_t)asi, va, data); 1022 1023 switch (asi) { 1024 case ASI_LSU_CONTROL_REG: 1025 assert(va == 0); 1026 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 1027 break; 1028 case ASI_MMU: 1029 switch (va) { 1030 case 0x8: 1031 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 1032 break; 1033 case 0x10: 1034 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 1035 break; 1036 default: 1037 goto doMmuWriteError; 1038 } 1039 break; 1040 case ASI_QUEUE: 1041 assert(mbits(data,13,6) == data); 1042 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 1043 (va >> 4) - 0x3c, data); 1044 break; 1045 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1046 assert(va == 0); 1047 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 1048 break; 1049 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1050 assert(va == 0); 1051 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 1052 break; 1053 case ASI_DMMU_CTXT_ZERO_CONFIG: 1054 assert(va == 0); 1055 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 1056 break; 1057 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1058 assert(va == 0); 1059 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 1060 break; 1061 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1062 assert(va == 0); 1063 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 1064 break; 1065 case ASI_IMMU_CTXT_ZERO_CONFIG: 1066 assert(va == 0); 1067 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 1068 break; 1069 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1070 assert(va == 0); 1071 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 1072 break; 1073 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1074 assert(va == 0); 1075 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 1076 break; 1077 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1078 assert(va == 0); 1079 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 1080 break; 1081 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1082 assert(va == 0); 1083 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 1084 break; 1085 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1086 assert(va == 0); 1087 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 1088 break; 1089 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1090 assert(va == 0); 1091 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 1092 break; 1093 case ASI_SPARC_ERROR_EN_REG: 1094 case ASI_SPARC_ERROR_STATUS_REG: 1095 warn("Ignoring write to SPARC ERROR regsiter\n"); 1096 break; 1097 case ASI_HYP_SCRATCHPAD: 1098 case ASI_SCRATCHPAD: 1099 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1100 break; 1101 case ASI_IMMU: 1102 switch (va) { 1103 case 0x18: 1104 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 1105 break; 1106 case 0x30: 1107 sext<59>(bits(data, 59,0)); 1108 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 1109 break; 1110 default: 1111 goto doMmuWriteError; 1112 } 1113 break; 1114 case ASI_ITLB_DATA_ACCESS_REG: 1115 entry_insert = bits(va, 8,3); 1116 case ASI_ITLB_DATA_IN_REG: 1117 assert(entry_insert != -1 || mbits(va,10,9) == va); 1118 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 1119 va_insert = mbits(ta_insert, 63,13); 1120 ct_insert = mbits(ta_insert, 12,0); 1121 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1122 real_insert = bits(va, 9,9); 1123 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1124 PageTableEntry::sun4u); 1125 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1126 pte, entry_insert); 1127 break; 1128 case ASI_DTLB_DATA_ACCESS_REG: 1129 entry_insert = bits(va, 8,3); 1130 case ASI_DTLB_DATA_IN_REG: 1131 assert(entry_insert != -1 || mbits(va,10,9) == va); 1132 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 1133 va_insert = mbits(ta_insert, 63,13); 1134 ct_insert = mbits(ta_insert, 12,0); 1135 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1136 real_insert = bits(va, 9,9); 1137 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1138 PageTableEntry::sun4u); 1139 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 1140 break; 1141 case ASI_IMMU_DEMAP: 1142 ignore = false; 1143 ctx_id = -1; 1144 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1145 switch (bits(va,5,4)) { 1146 case 0: 1147 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 1148 break; 1149 case 1: 1150 ignore = true; 1151 break; 1152 case 3: 1153 ctx_id = 0; 1154 break; 1155 default: 1156 ignore = true; 1157 } 1158 1159 switch(bits(va,7,6)) { 1160 case 0: // demap page 1161 if (!ignore) 1162 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1163 bits(va,9,9), ctx_id); 1164 break; 1165 case 1: //demap context 1166 if (!ignore) 1167 tc->getITBPtr()->demapContext(part_id, ctx_id); 1168 break; 1169 case 2: 1170 tc->getITBPtr()->demapAll(part_id); 1171 break; 1172 default: 1173 panic("Invalid type for IMMU demap\n"); 1174 } 1175 break; 1176 case ASI_DMMU: 1177 switch (va) { 1178 case 0x18: 1179 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 1180 break; 1181 case 0x30: 1182 sext<59>(bits(data, 59,0)); 1183 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 1184 break; 1185 case 0x80: 1186 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 1187 break; 1188 default: 1189 goto doMmuWriteError; 1190 } 1191 break; 1192 case ASI_DMMU_DEMAP: 1193 ignore = false; 1194 ctx_id = -1; 1195 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1196 switch (bits(va,5,4)) { 1197 case 0: 1198 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 1199 break; 1200 case 1: 1201 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 1202 break; 1203 case 3: 1204 ctx_id = 0; 1205 break; 1206 default: 1207 ignore = true; 1208 } 1209 1210 switch(bits(va,7,6)) { 1211 case 0: // demap page 1212 if (!ignore) 1213 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1214 break; 1215 case 1: //demap context 1216 if (!ignore) 1217 demapContext(part_id, ctx_id); 1218 break; 1219 case 2: 1220 demapAll(part_id); 1221 break; 1222 default: 1223 panic("Invalid type for IMMU demap\n"); 1224 } 1225 break; 1226 default: 1227doMmuWriteError: 1228 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 1229 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 1230 } 1231 pkt->result = Packet::Success; 1232 return tc->getCpuPtr()->cycles(1); 1233} 1234 1235void 1236DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1237{ 1238 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 1239 ptrs[0] = MakeTsbPtr(Ps0, tag_access, 1240 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), 1241 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 1242 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), 1243 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 1244 ptrs[1] = MakeTsbPtr(Ps1, tag_access, 1245 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), 1246 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 1247 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), 1248 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 1249 ptrs[2] = MakeTsbPtr(Ps0, tag_access, 1250 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), 1251 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 1252 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), 1253 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 1254 ptrs[3] = MakeTsbPtr(Ps1, tag_access, 1255 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), 1256 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 1257 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), 1258 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 1259} 1260 1261 1262 1263 1264 1265uint64_t 1266DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1267 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 1268{ 1269 uint64_t tsb; 1270 uint64_t config; 1271 1272 if (bits(tag_access, 12,0) == 0) { 1273 tsb = c0_tsb; 1274 config = c0_config; 1275 } else { 1276 tsb = cX_tsb; 1277 config = cX_config; 1278 } 1279 1280 uint64_t ptr = mbits(tsb,63,13); 1281 bool split = bits(tsb,12,12); 1282 int tsb_size = bits(tsb,3,0); 1283 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 1284 1285 if (ps == Ps1 && split) 1286 ptr |= ULL(1) << (13 + tsb_size); 1287 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 1288 1289 return ptr; 1290} 1291 1292 1293void 1294TLB::serialize(std::ostream &os) 1295{ 1296 SERIALIZE_SCALAR(size); 1297 SERIALIZE_SCALAR(usedEntries); 1298 SERIALIZE_SCALAR(lastReplaced); 1299 1300 // convert the pointer based free list into an index based one 1301 int *free_list = (int*)malloc(sizeof(int) * size); 1302 int cntr = 0; 1303 std::list<TlbEntry*>::iterator i; 1304 i = freeList.begin(); 1305 while (i != freeList.end()) { 1306 free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 1307 i++; 1308 } 1309 SERIALIZE_SCALAR(cntr); 1310 SERIALIZE_ARRAY(free_list, cntr); 1311 1312 for (int x = 0; x < size; x++) { 1313 nameOut(os, csprintf("%s.PTE%d", name(), x)); 1314 tlb[x].serialize(os); 1315 } 1316} 1317 1318void 1319TLB::unserialize(Checkpoint *cp, const std::string §ion) 1320{ 1321 int oldSize; 1322 1323 paramIn(cp, section, "size", oldSize); 1324 if (oldSize != size) 1325 panic("Don't support unserializing different sized TLBs\n"); 1326 UNSERIALIZE_SCALAR(usedEntries); 1327 UNSERIALIZE_SCALAR(lastReplaced); 1328 1329 int cntr; 1330 UNSERIALIZE_SCALAR(cntr); 1331 1332 int *free_list = (int*)malloc(sizeof(int) * cntr); 1333 freeList.clear(); 1334 UNSERIALIZE_ARRAY(free_list, cntr); 1335 for (int x = 0; x < cntr; x++) 1336 freeList.push_back(&tlb[free_list[x]]); 1337 1338 lookupTable.clear(); 1339 for (int x = 0; x < size; x++) { 1340 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1341 if (tlb[x].valid) 1342 lookupTable.insert(tlb[x].range, &tlb[x]); 1343 1344 } 1345} 1346 1347 1348DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 1349 1350BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 1351 1352 Param<int> size; 1353 1354END_DECLARE_SIM_OBJECT_PARAMS(ITB) 1355 1356BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 1357 1358 INIT_PARAM_DFLT(size, "TLB size", 48) 1359 1360END_INIT_SIM_OBJECT_PARAMS(ITB) 1361 1362 1363CREATE_SIM_OBJECT(ITB) 1364{ 1365 return new ITB(getInstanceName(), size); 1366} 1367 1368REGISTER_SIM_OBJECT("SparcITB", ITB) 1369 1370BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 1371 1372 Param<int> size; 1373 1374END_DECLARE_SIM_OBJECT_PARAMS(DTB) 1375 1376BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 1377 1378 INIT_PARAM_DFLT(size, "TLB size", 64) 1379 1380END_INIT_SIM_OBJECT_PARAMS(DTB) 1381 1382 1383CREATE_SIM_OBJECT(DTB) 1384{ 1385 return new DTB(getInstanceName(), size); 1386} 1387 1388REGISTER_SIM_OBJECT("SparcDTB", DTB) 1389} 1390