tlb.cc revision 3928 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40#include "sim/builder.hh"
41
42/* @todo remove some of the magic constants.  -- ali
43 * */
44namespace SparcISA
45{
46
47TLB::TLB(const std::string &name, int s)
48    : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
49      cacheValid(false)
50{
51    // To make this work you'll have to change the hypervisor and OS
52    if (size > 64)
53        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
54
55    tlb = new TlbEntry[size];
56    memset(tlb, 0, sizeof(TlbEntry) * size);
57
58    for (int x = 0; x < size; x++)
59        freeList.push_back(&tlb[x]);
60}
61
62void
63TLB::clearUsedBits()
64{
65    MapIter i;
66    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
67        TlbEntry *t = i->second;
68        if (!t->pte.locked()) {
69            t->used = false;
70            usedEntries--;
71        }
72    }
73}
74
75
76void
77TLB::insert(Addr va, int partition_id, int context_id, bool real,
78        const PageTableEntry& PTE, int entry)
79{
80
81
82    MapIter i;
83    TlbEntry *new_entry = NULL;
84//    TlbRange tr;
85    int x;
86
87    cacheValid = false;
88    va &= ~(PTE.size()-1);
89 /*   tr.va = va;
90    tr.size = PTE.size() - 1;
91    tr.contextId = context_id;
92    tr.partitionId = partition_id;
93    tr.real = real;
94*/
95
96    DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
97            va, PTE.paddr(), partition_id, context_id, (int)real, entry);
98
99    // Demap any entry that conflicts
100    for (x = 0; x < size; x++) {
101        if (tlb[x].range.real == real &&
102            tlb[x].range.partitionId == partition_id &&
103            tlb[x].range.va < va + PTE.size() - 1 &&
104            tlb[x].range.va + tlb[x].range.size >= va &&
105            (real || tlb[x].range.contextId == context_id ))
106        {
107            if (tlb[x].valid) {
108                freeList.push_front(&tlb[x]);
109                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
110
111                tlb[x].valid = false;
112                if (tlb[x].used) {
113                    tlb[x].used = false;
114                    usedEntries--;
115                }
116                lookupTable.erase(tlb[x].range);
117            }
118        }
119    }
120
121
122/*
123    i = lookupTable.find(tr);
124    if (i != lookupTable.end()) {
125        i->second->valid = false;
126        if (i->second->used) {
127            i->second->used = false;
128            usedEntries--;
129        }
130        freeList.push_front(i->second);
131        DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
132                i->second);
133        lookupTable.erase(i);
134    }
135*/
136
137    if (entry != -1) {
138        assert(entry < size && entry >= 0);
139        new_entry = &tlb[entry];
140    } else {
141        if (!freeList.empty()) {
142            new_entry = freeList.front();
143        } else {
144            x = lastReplaced;
145            do {
146                ++x;
147                if (x == size)
148                    x = 0;
149                if (x == lastReplaced)
150                    goto insertAllLocked;
151            } while (tlb[x].pte.locked());
152            lastReplaced = x;
153            new_entry = &tlb[x];
154        }
155        /*
156        for (x = 0; x < size; x++) {
157            if (!tlb[x].valid || !tlb[x].used)  {
158                new_entry = &tlb[x];
159                break;
160            }
161        }*/
162    }
163
164insertAllLocked:
165    // Update the last ently if their all locked
166    if (!new_entry) {
167        new_entry = &tlb[size-1];
168    }
169
170    freeList.remove(new_entry);
171    if (new_entry->valid && new_entry->used)
172        usedEntries--;
173
174    lookupTable.erase(new_entry->range);
175
176
177    DPRINTF(TLB, "Using entry: %#X\n", new_entry);
178
179    assert(PTE.valid());
180    new_entry->range.va = va;
181    new_entry->range.size = PTE.size() - 1;
182    new_entry->range.partitionId = partition_id;
183    new_entry->range.contextId = context_id;
184    new_entry->range.real = real;
185    new_entry->pte = PTE;
186    new_entry->used = true;;
187    new_entry->valid = true;
188    usedEntries++;
189
190
191
192    i = lookupTable.insert(new_entry->range, new_entry);
193    assert(i != lookupTable.end());
194
195    // If all entries have there used bit set, clear it on them all, but the
196    // one we just inserted
197    if (usedEntries == size) {
198        clearUsedBits();
199        new_entry->used = true;
200        usedEntries++;
201    }
202
203}
204
205
206TlbEntry*
207TLB::lookup(Addr va, int partition_id, bool real, int context_id)
208{
209    MapIter i;
210    TlbRange tr;
211    TlbEntry *t;
212
213    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
214            va, partition_id, context_id, real);
215    // Assemble full address structure
216    tr.va = va;
217    tr.size = MachineBytes;
218    tr.contextId = context_id;
219    tr.partitionId = partition_id;
220    tr.real = real;
221
222    // Try to find the entry
223    i = lookupTable.find(tr);
224    if (i == lookupTable.end()) {
225        DPRINTF(TLB, "TLB: No valid entry found\n");
226        return NULL;
227    }
228
229    // Mark the entries used bit and clear other used bits in needed
230    t = i->second;
231    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
232            t->pte.size());
233    if (!t->used) {
234        t->used = true;
235        usedEntries++;
236        if (usedEntries == size) {
237            clearUsedBits();
238            t->used = true;
239            usedEntries++;
240        }
241    }
242
243    return t;
244}
245
246void
247TLB::dumpAll()
248{
249    MapIter i;
250    for (int x = 0; x < size; x++) {
251        if (tlb[x].valid) {
252           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
253                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
254                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
255                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
256        }
257    }
258}
259
260void
261TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
262{
263    TlbRange tr;
264    MapIter i;
265
266    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
267            va, partition_id, context_id, real);
268
269    cacheValid = false;
270
271    // Assemble full address structure
272    tr.va = va;
273    tr.size = MachineBytes;
274    tr.contextId = context_id;
275    tr.partitionId = partition_id;
276    tr.real = real;
277
278    // Demap any entry that conflicts
279    i = lookupTable.find(tr);
280    if (i != lookupTable.end()) {
281        DPRINTF(IPR, "TLB: Demapped page\n");
282        i->second->valid = false;
283        if (i->second->used) {
284            i->second->used = false;
285            usedEntries--;
286        }
287        freeList.push_front(i->second);
288        DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second);
289        lookupTable.erase(i);
290    }
291}
292
293void
294TLB::demapContext(int partition_id, int context_id)
295{
296    int x;
297    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
298            partition_id, context_id);
299    cacheValid = false;
300    for (x = 0; x < size; x++) {
301        if (tlb[x].range.contextId == context_id &&
302            tlb[x].range.partitionId == partition_id) {
303            if (tlb[x].valid == true) {
304                freeList.push_front(&tlb[x]);
305                DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
306            }
307            tlb[x].valid = false;
308            if (tlb[x].used) {
309                tlb[x].used = false;
310                usedEntries--;
311            }
312            lookupTable.erase(tlb[x].range);
313        }
314    }
315}
316
317void
318TLB::demapAll(int partition_id)
319{
320    int x;
321    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
322    cacheValid = false;
323    for (x = 0; x < size; x++) {
324        if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
325            if (tlb[x].valid == true){
326                freeList.push_front(&tlb[x]);
327                DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
328            }
329            tlb[x].valid = false;
330            if (tlb[x].used) {
331                tlb[x].used = false;
332                usedEntries--;
333            }
334            lookupTable.erase(tlb[x].range);
335        }
336    }
337}
338
339void
340TLB::invalidateAll()
341{
342    int x;
343    cacheValid = false;
344
345    freeList.clear();
346    lookupTable.clear();
347    for (x = 0; x < size; x++) {
348        if (tlb[x].valid == true)
349            freeList.push_back(&tlb[x]);
350        tlb[x].valid = false;
351        tlb[x].used = false;
352    }
353    usedEntries = 0;
354}
355
356uint64_t
357TLB::TteRead(int entry) {
358    if (entry >= size)
359        panic("entry: %d\n", entry);
360
361    assert(entry < size);
362    if (tlb[entry].valid)
363        return tlb[entry].pte();
364    else
365        return (uint64_t)-1ll;
366}
367
368uint64_t
369TLB::TagRead(int entry) {
370    assert(entry < size);
371    uint64_t tag;
372    if (!tlb[entry].valid)
373        return (uint64_t)-1ll;
374
375    tag = tlb[entry].range.contextId;
376    tag |= tlb[entry].range.va;
377    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
378    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
379    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
380    return tag;
381}
382
383bool
384TLB::validVirtualAddress(Addr va, bool am)
385{
386    if (am)
387        return true;
388    if (va >= StartVAddrHole && va <= EndVAddrHole)
389        return false;
390    return true;
391}
392
393void
394TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
395        bool se, FaultTypes ft, int asi)
396{
397    uint64_t sfsr;
398    sfsr = tc->readMiscReg(reg);
399
400    if (sfsr & 0x1)
401        sfsr = 0x3;
402    else
403        sfsr = 1;
404
405    if (write)
406        sfsr |= 1 << 2;
407    sfsr |= ct << 4;
408    if (se)
409        sfsr |= 1 << 6;
410    sfsr |= ft << 7;
411    sfsr |= asi << 16;
412    tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
418    DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
419            va, context, mbits(va, 63,13) | mbits(context,12,0));
420
421    tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
422}
423
424void
425ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
426        bool se, FaultTypes ft, int asi)
427{
428    DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
429             (int)write, ct, ft, asi);
430    TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
431}
432
433void
434ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
435{
436    TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
437}
438
439void
440DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
441        bool se, FaultTypes ft, int asi)
442{
443    DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
444            a, (int)write, ct, ft, asi);
445    TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
446    tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
447}
448
449void
450DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
451{
452    TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
453}
454
455
456
457Fault
458ITB::translate(RequestPtr &req, ThreadContext *tc)
459{
460    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
461
462    Addr vaddr = req->getVaddr();
463    TlbEntry *e;
464
465    assert(req->getAsi() == ASI_IMPLICIT);
466
467    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
468            vaddr, req->getSize());
469
470    // Be fast if we can!
471    if (cacheValid && cacheState == tlbdata) {
472        if (cacheEntry) {
473            if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
474                cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
475                    req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
476                                  vaddr & cacheEntry->pte.size()-1 );
477                    return NoFault;
478            }
479        } else {
480            req->setPaddr(vaddr & PAddrImplMask);
481            return NoFault;
482        }
483    }
484
485    bool hpriv = bits(tlbdata,0,0);
486    bool red = bits(tlbdata,1,1);
487    bool priv = bits(tlbdata,2,2);
488    bool addr_mask = bits(tlbdata,3,3);
489    bool lsu_im = bits(tlbdata,4,4);
490
491    int part_id = bits(tlbdata,15,8);
492    int tl = bits(tlbdata,18,16);
493    int pri_context = bits(tlbdata,47,32);
494    int context;
495    ContextType ct;
496    int asi;
497    bool real = false;
498
499    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
500           priv, hpriv, red, lsu_im, part_id);
501
502    if (tl > 0) {
503        asi = ASI_N;
504        ct = Nucleus;
505        context = 0;
506    } else {
507        asi = ASI_P;
508        ct = Primary;
509        context = pri_context;
510    }
511
512    if ( hpriv || red ) {
513        cacheValid = true;
514        cacheState = tlbdata;
515        cacheEntry = NULL;
516        req->setPaddr(vaddr & PAddrImplMask);
517        return NoFault;
518    }
519
520    // If the access is unaligned trap
521    if (vaddr & 0x3) {
522        writeSfsr(tc, false, ct, false, OtherFault, asi);
523        return new MemAddressNotAligned;
524    }
525
526    if (addr_mask)
527        vaddr = vaddr & VAddrAMask;
528
529    if (!validVirtualAddress(vaddr, addr_mask)) {
530        writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
531        return new InstructionAccessException;
532    }
533
534    if (!lsu_im) {
535        e = lookup(vaddr, part_id, true);
536        real = true;
537        context = 0;
538    } else {
539        e = lookup(vaddr, part_id, false, context);
540    }
541
542    if (e == NULL || !e->valid) {
543        writeTagAccess(tc, vaddr, context);
544        if (real)
545            return new InstructionRealTranslationMiss;
546        else
547            return new FastInstructionAccessMMUMiss;
548    }
549
550    // were not priviledged accesing priv page
551    if (!priv && e->pte.priv()) {
552        writeTagAccess(tc, vaddr, context);
553        writeSfsr(tc, false, ct, false, PrivViolation, asi);
554        return new InstructionAccessException;
555    }
556
557    // cache translation date for next translation
558    cacheValid = true;
559    cacheState = tlbdata;
560    cacheEntry = e;
561
562    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
563                  vaddr & e->pte.size()-1 );
564    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
565    return NoFault;
566}
567
568
569
570Fault
571DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
572{
573    /* @todo this could really use some profiling and fixing to make it faster! */
574    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
575    Addr vaddr = req->getVaddr();
576    Addr size = req->getSize();
577    ASI asi;
578    asi = (ASI)req->getAsi();
579    bool implicit = false;
580    bool hpriv = bits(tlbdata,0,0);
581
582    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
583            vaddr, size, asi);
584
585    if (asi == ASI_IMPLICIT)
586        implicit = true;
587
588    if (hpriv && implicit) {
589        req->setPaddr(vaddr & PAddrImplMask);
590        return NoFault;
591    }
592
593    // Be fast if we can!
594    if (cacheValid &&  cacheState == tlbdata) {
595        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
596            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
597            (!write || cacheEntry[0]->pte.writable())) {
598                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
599                              vaddr & cacheEntry[0]->pte.size()-1 );
600                return NoFault;
601        }
602        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
603            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
604            (!write || cacheEntry[1]->pte.writable())) {
605                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
606                              vaddr & cacheEntry[1]->pte.size()-1 );
607                return NoFault;
608        }
609    }
610
611    bool red = bits(tlbdata,1,1);
612    bool priv = bits(tlbdata,2,2);
613    bool addr_mask = bits(tlbdata,3,3);
614    bool lsu_dm = bits(tlbdata,5,5);
615
616    int part_id = bits(tlbdata,15,8);
617    int tl = bits(tlbdata,18,16);
618    int pri_context = bits(tlbdata,47,32);
619    int sec_context = bits(tlbdata,63,48);
620
621    bool real = false;
622    ContextType ct = Primary;
623    int context = 0;
624
625    TlbEntry *e;
626
627    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
628           priv, hpriv, red, lsu_dm, part_id);
629
630    if (implicit) {
631        if (tl > 0) {
632            asi = ASI_N;
633            ct = Nucleus;
634            context = 0;
635        } else {
636            asi = ASI_P;
637            ct = Primary;
638            context = pri_context;
639        }
640    } else {
641        // We need to check for priv level/asi priv
642        if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
643            // It appears that context should be Nucleus in these cases?
644            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
645            return new PrivilegedAction;
646        }
647
648        if (!hpriv && AsiIsHPriv(asi)) {
649            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
650            return new DataAccessException;
651        }
652
653        if (AsiIsPrimary(asi)) {
654            context = pri_context;
655            ct = Primary;
656        } else if (AsiIsSecondary(asi)) {
657            context = sec_context;
658            ct = Secondary;
659        } else if (AsiIsNucleus(asi)) {
660            ct = Nucleus;
661            context = 0;
662        } else {  // ????
663            ct = Primary;
664            context = pri_context;
665        }
666    }
667
668    if (!implicit && asi != ASI_P && asi != ASI_S) {
669        if (AsiIsLittle(asi))
670            panic("Little Endian ASIs not supported\n");
671        if (AsiIsBlock(asi))
672            panic("Block ASIs not supported\n");
673        if (AsiIsNoFault(asi))
674            panic("No Fault ASIs not supported\n");
675
676        if (AsiIsPartialStore(asi))
677            panic("Partial Store ASIs not supported\n");
678        if (AsiIsInterrupt(asi))
679            panic("Interrupt ASIs not supported\n");
680
681        if (AsiIsMmu(asi))
682            goto handleMmuRegAccess;
683        if (AsiIsScratchPad(asi))
684            goto handleScratchRegAccess;
685        if (AsiIsQueue(asi))
686            goto handleQueueRegAccess;
687        if (AsiIsSparcError(asi))
688            goto handleSparcErrorRegAccess;
689
690        if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
691                !AsiIsTwin(asi))
692            panic("Accessing ASI %#X. Should we?\n", asi);
693    }
694
695    // If the asi is unaligned trap
696    if (vaddr & size-1) {
697        writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
698        return new MemAddressNotAligned;
699    }
700
701    if (addr_mask)
702        vaddr = vaddr & VAddrAMask;
703
704    if (!validVirtualAddress(vaddr, addr_mask)) {
705        writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
706        return new DataAccessException;
707    }
708
709
710    if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
711        real = true;
712        context = 0;
713    };
714
715    if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
716        req->setPaddr(vaddr & PAddrImplMask);
717        return NoFault;
718    }
719
720    e = lookup(vaddr, part_id, real, context);
721
722    if (e == NULL || !e->valid) {
723        writeTagAccess(tc, vaddr, context);
724        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
725        if (real)
726            return new DataRealTranslationMiss;
727        else
728            return new FastDataAccessMMUMiss;
729
730    }
731
732    if (!priv && e->pte.priv()) {
733        writeTagAccess(tc, vaddr, context);
734        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
735        return new DataAccessException;
736    }
737
738    if (write && !e->pte.writable()) {
739        writeTagAccess(tc, vaddr, context);
740        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
741        return new FastDataAccessProtection;
742    }
743
744    if (e->pte.nofault() && !AsiIsNoFault(asi)) {
745        writeTagAccess(tc, vaddr, context);
746        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
747        return new DataAccessException;
748    }
749
750    if (e->pte.sideffect() && AsiIsNoFault(asi)) {
751        writeTagAccess(tc, vaddr, context);
752        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
753        return new DataAccessException;
754    }
755
756
757    if (e->pte.sideffect())
758        req->setFlags(req->getFlags() | UNCACHEABLE);
759
760    // cache translation date for next translation
761    cacheState = tlbdata;
762    if (!cacheValid) {
763        cacheEntry[1] = NULL;
764        cacheEntry[0] = NULL;
765    }
766
767    if (cacheEntry[0] != e && cacheEntry[1] != e) {
768        cacheEntry[1] = cacheEntry[0];
769        cacheEntry[0] = e;
770        cacheAsi[1] = cacheAsi[0];
771        cacheAsi[0] = asi;
772        if (implicit)
773            cacheAsi[0] = (ASI)0;
774    }
775    cacheValid = true;
776    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
777                  vaddr & e->pte.size()-1);
778    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
779    return NoFault;
780    /** Normal flow ends here. */
781
782handleScratchRegAccess:
783    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
784        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
785        return new DataAccessException;
786    }
787    goto regAccessOk;
788
789handleQueueRegAccess:
790    if (!priv  && !hpriv) {
791        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
792        return new PrivilegedAction;
793    }
794    if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
795        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
796        return new DataAccessException;
797    }
798    goto regAccessOk;
799
800handleSparcErrorRegAccess:
801    if (!hpriv) {
802        if (priv) {
803            writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
804            return new DataAccessException;
805        } else {
806            writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
807            return new PrivilegedAction;
808        }
809    }
810    goto regAccessOk;
811
812
813regAccessOk:
814handleMmuRegAccess:
815    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
816    req->setMmapedIpr(true);
817    req->setPaddr(req->getVaddr());
818    return NoFault;
819};
820
821Tick
822DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
823{
824    Addr va = pkt->getAddr();
825    ASI asi = (ASI)pkt->req->getAsi();
826    uint64_t temp, data;
827    uint64_t tsbtemp, cnftemp;
828
829    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
830         (uint32_t)pkt->req->getAsi(), pkt->getAddr());
831
832    switch (asi) {
833      case ASI_LSU_CONTROL_REG:
834        assert(va == 0);
835        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
836        break;
837      case ASI_MMU:
838        switch (va) {
839          case 0x8:
840            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
841            break;
842          case 0x10:
843            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
844            break;
845          default:
846            goto doMmuReadError;
847        }
848        break;
849      case ASI_QUEUE:
850        pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
851                    (va >> 4) - 0x3c));
852        break;
853      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
854        assert(va == 0);
855        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
856        break;
857      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
858        assert(va == 0);
859        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
860        break;
861      case ASI_DMMU_CTXT_ZERO_CONFIG:
862        assert(va == 0);
863        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
864        break;
865      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
866        assert(va == 0);
867        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
868        break;
869      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
870        assert(va == 0);
871        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
872        break;
873      case ASI_IMMU_CTXT_ZERO_CONFIG:
874        assert(va == 0);
875        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
876        break;
877      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
878        assert(va == 0);
879        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
880        break;
881      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
882        assert(va == 0);
883        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
884        break;
885      case ASI_DMMU_CTXT_NONZERO_CONFIG:
886        assert(va == 0);
887        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
888        break;
889      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
890        assert(va == 0);
891        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
892        break;
893      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
894        assert(va == 0);
895        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
896        break;
897      case ASI_IMMU_CTXT_NONZERO_CONFIG:
898        assert(va == 0);
899        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
900        break;
901      case ASI_SPARC_ERROR_STATUS_REG:
902        warn("returning 0 for  SPARC ERROR regsiter read\n");
903        pkt->set((uint64_t)0);
904        break;
905      case ASI_HYP_SCRATCHPAD:
906      case ASI_SCRATCHPAD:
907        pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
908        break;
909      case ASI_IMMU:
910        switch (va) {
911          case 0x0:
912            temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
913            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
914            break;
915          case 0x18:
916            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
917            break;
918          case 0x30:
919            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
920            break;
921          default:
922            goto doMmuReadError;
923        }
924        break;
925      case ASI_DMMU:
926        switch (va) {
927          case 0x0:
928            temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
929            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
930            break;
931          case 0x18:
932            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
933            break;
934          case 0x20:
935            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
936            break;
937          case 0x30:
938            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
939            break;
940          case 0x80:
941            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
942            break;
943          default:
944                goto doMmuReadError;
945        }
946        break;
947      case ASI_DMMU_TSB_PS0_PTR_REG:
948        temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
949        if (bits(temp,12,0) == 0) {
950            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
951            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
952        } else {
953            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
954            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
955        }
956        data = mbits(tsbtemp,63,13);
957        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
958            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
959        pkt->set(data);
960        break;
961      case ASI_DMMU_TSB_PS1_PTR_REG:
962        temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
963        if (bits(temp,12,0) == 0) {
964            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
965            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
966        } else {
967            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
968            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
969        }
970        data = mbits(tsbtemp,63,13);
971        if (bits(tsbtemp,12,12))
972            data |= ULL(1) << (13+bits(tsbtemp,3,0));
973        data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
974            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
975        pkt->set(data);
976        break;
977      case ASI_IMMU_TSB_PS0_PTR_REG:
978        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
979        if (bits(temp,12,0) == 0) {
980            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
981            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
982        } else {
983            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
984            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
985        }
986        data = mbits(tsbtemp,63,13);
987        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
988            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
989        pkt->set(data);
990        break;
991      case ASI_IMMU_TSB_PS1_PTR_REG:
992        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
993        if (bits(temp,12,0) == 0) {
994            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
995            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
996        } else {
997            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
998            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
999        }
1000        data = mbits(tsbtemp,63,13);
1001        if (bits(tsbtemp,12,12))
1002            data |= ULL(1) << (13+bits(tsbtemp,3,0));
1003        data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
1004            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1005        pkt->set(data);
1006        break;
1007
1008      default:
1009doMmuReadError:
1010        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1011            (uint32_t)asi, va);
1012    }
1013    pkt->result = Packet::Success;
1014    return tc->getCpuPtr()->cycles(1);
1015}
1016
1017Tick
1018DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1019{
1020    uint64_t data = gtoh(pkt->get<uint64_t>());
1021    Addr va = pkt->getAddr();
1022    ASI asi = (ASI)pkt->req->getAsi();
1023
1024    Addr ta_insert;
1025    Addr va_insert;
1026    Addr ct_insert;
1027    int part_insert;
1028    int entry_insert = -1;
1029    bool real_insert;
1030    bool ignore;
1031    int part_id;
1032    int ctx_id;
1033    PageTableEntry pte;
1034
1035    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1036         (uint32_t)asi, va, data);
1037
1038    switch (asi) {
1039      case ASI_LSU_CONTROL_REG:
1040        assert(va == 0);
1041        tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1042        break;
1043      case ASI_MMU:
1044        switch (va) {
1045          case 0x8:
1046            tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1047            break;
1048          case 0x10:
1049            tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1050            break;
1051          default:
1052            goto doMmuWriteError;
1053        }
1054        break;
1055      case ASI_QUEUE:
1056        assert(mbits(data,13,6) == data);
1057        tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1058                    (va >> 4) - 0x3c, data);
1059        break;
1060      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1061        assert(va == 0);
1062        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1063        break;
1064      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1065        assert(va == 0);
1066        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1067        break;
1068      case ASI_DMMU_CTXT_ZERO_CONFIG:
1069        assert(va == 0);
1070        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1071        break;
1072      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1073        assert(va == 0);
1074        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1075        break;
1076      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1077        assert(va == 0);
1078        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1079        break;
1080      case ASI_IMMU_CTXT_ZERO_CONFIG:
1081        assert(va == 0);
1082        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1083        break;
1084      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1085        assert(va == 0);
1086        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1087        break;
1088      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1089        assert(va == 0);
1090        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1091        break;
1092      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1093        assert(va == 0);
1094        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1095        break;
1096      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1097        assert(va == 0);
1098        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1099        break;
1100      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1101        assert(va == 0);
1102        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1103        break;
1104      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1105        assert(va == 0);
1106        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1107        break;
1108      case ASI_SPARC_ERROR_EN_REG:
1109      case ASI_SPARC_ERROR_STATUS_REG:
1110        warn("Ignoring write to SPARC ERROR regsiter\n");
1111        break;
1112      case ASI_HYP_SCRATCHPAD:
1113      case ASI_SCRATCHPAD:
1114        tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1115        break;
1116      case ASI_IMMU:
1117        switch (va) {
1118          case 0x18:
1119            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1120            break;
1121          case 0x30:
1122            sext<59>(bits(data, 59,0));
1123            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1124            break;
1125          default:
1126            goto doMmuWriteError;
1127        }
1128        break;
1129      case ASI_ITLB_DATA_ACCESS_REG:
1130        entry_insert = bits(va, 8,3);
1131      case ASI_ITLB_DATA_IN_REG:
1132        assert(entry_insert != -1 || mbits(va,10,9) == va);
1133        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1134        va_insert = mbits(ta_insert, 63,13);
1135        ct_insert = mbits(ta_insert, 12,0);
1136        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1137        real_insert = bits(va, 9,9);
1138        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1139                PageTableEntry::sun4u);
1140        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1141                pte, entry_insert);
1142        break;
1143      case ASI_DTLB_DATA_ACCESS_REG:
1144        entry_insert = bits(va, 8,3);
1145      case ASI_DTLB_DATA_IN_REG:
1146        assert(entry_insert != -1 || mbits(va,10,9) == va);
1147        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1148        va_insert = mbits(ta_insert, 63,13);
1149        ct_insert = mbits(ta_insert, 12,0);
1150        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1151        real_insert = bits(va, 9,9);
1152        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1153                PageTableEntry::sun4u);
1154        insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1155        break;
1156      case ASI_IMMU_DEMAP:
1157        ignore = false;
1158        ctx_id = -1;
1159        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1160        switch (bits(va,5,4)) {
1161          case 0:
1162            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1163            break;
1164          case 1:
1165            ignore = true;
1166            break;
1167          case 3:
1168            ctx_id = 0;
1169            break;
1170          default:
1171            ignore = true;
1172        }
1173
1174        switch(bits(va,7,6)) {
1175          case 0: // demap page
1176            if (!ignore)
1177                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1178                        bits(va,9,9), ctx_id);
1179            break;
1180          case 1: //demap context
1181            if (!ignore)
1182                tc->getITBPtr()->demapContext(part_id, ctx_id);
1183            break;
1184          case 2:
1185            tc->getITBPtr()->demapAll(part_id);
1186            break;
1187          default:
1188            panic("Invalid type for IMMU demap\n");
1189        }
1190        break;
1191      case ASI_DMMU:
1192        switch (va) {
1193          case 0x18:
1194            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1195            break;
1196          case 0x30:
1197            sext<59>(bits(data, 59,0));
1198            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1199            break;
1200          case 0x80:
1201            tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1202            break;
1203          default:
1204            goto doMmuWriteError;
1205        }
1206        break;
1207      case ASI_DMMU_DEMAP:
1208        ignore = false;
1209        ctx_id = -1;
1210        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1211        switch (bits(va,5,4)) {
1212          case 0:
1213            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1214            break;
1215          case 1:
1216            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1217            break;
1218          case 3:
1219            ctx_id = 0;
1220            break;
1221          default:
1222            ignore = true;
1223        }
1224
1225        switch(bits(va,7,6)) {
1226          case 0: // demap page
1227            if (!ignore)
1228                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1229            break;
1230          case 1: //demap context
1231            if (!ignore)
1232                demapContext(part_id, ctx_id);
1233            break;
1234          case 2:
1235            demapAll(part_id);
1236            break;
1237          default:
1238            panic("Invalid type for IMMU demap\n");
1239        }
1240        break;
1241      default:
1242doMmuWriteError:
1243        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1244            (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1245    }
1246    pkt->result = Packet::Success;
1247    return tc->getCpuPtr()->cycles(1);
1248}
1249
1250void
1251TLB::serialize(std::ostream &os)
1252{
1253    panic("Need to implement serialize tlb for SPARC\n");
1254}
1255
1256void
1257TLB::unserialize(Checkpoint *cp, const std::string &section)
1258{
1259    panic("Need to implement unserialize tlb for SPARC\n");
1260}
1261
1262
1263DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1264
1265BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1266
1267    Param<int> size;
1268
1269END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1270
1271BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1272
1273    INIT_PARAM_DFLT(size, "TLB size", 48)
1274
1275END_INIT_SIM_OBJECT_PARAMS(ITB)
1276
1277
1278CREATE_SIM_OBJECT(ITB)
1279{
1280    return new ITB(getInstanceName(), size);
1281}
1282
1283REGISTER_SIM_OBJECT("SparcITB", ITB)
1284
1285BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1286
1287    Param<int> size;
1288
1289END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1290
1291BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1292
1293    INIT_PARAM_DFLT(size, "TLB size", 64)
1294
1295END_INIT_SIM_OBJECT_PARAMS(DTB)
1296
1297
1298CREATE_SIM_OBJECT(DTB)
1299{
1300    return new DTB(getInstanceName(), size);
1301}
1302
1303REGISTER_SIM_OBJECT("SparcDTB", DTB)
1304}
1305