tlb.cc revision 3918 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"
41#include "mem/request.hh"
42#include "sim/builder.hh"
43
44/* @todo remove some of the magic constants.  -- ali
45 * */
46namespace SparcISA
47{
48
49TLB::TLB(const std::string &name, int s)
50    : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
51      cacheValid(false)
52{
53    // To make this work you'll have to change the hypervisor and OS
54    if (size > 64)
55        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
56
57    tlb = new TlbEntry[size];
58    std::memset(tlb, 0, sizeof(TlbEntry) * size);
59
60    for (int x = 0; x < size; x++)
61        freeList.push_back(&tlb[x]);
62}
63
64void
65TLB::clearUsedBits()
66{
67    MapIter i;
68    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
69        TlbEntry *t = i->second;
70        if (!t->pte.locked()) {
71            t->used = false;
72            usedEntries--;
73        }
74    }
75}
76
77
78void
79TLB::insert(Addr va, int partition_id, int context_id, bool real,
80        const PageTableEntry& PTE, int entry)
81{
82
83
84    MapIter i;
85    TlbEntry *new_entry = NULL;
86//    TlbRange tr;
87    int x;
88
89    cacheValid = false;
90 /*   tr.va = va;
91    tr.size = PTE.size() - 1;
92    tr.contextId = context_id;
93    tr.partitionId = partition_id;
94    tr.real = real;
95*/
96
97    DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
98            va, PTE.paddr(), partition_id, context_id, (int)real, entry);
99
100    // Demap any entry that conflicts
101    for (x = 0; x < size; x++) {
102        if (tlb[x].range.real == real &&
103            tlb[x].range.partitionId == partition_id &&
104            tlb[x].range.va < va + PTE.size() - 1 &&
105            tlb[x].range.va + tlb[x].range.size >= va &&
106            (real || tlb[x].range.contextId == context_id ))
107        {
108            if (tlb[x].valid) {
109                freeList.push_front(&tlb[x]);
110                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
111
112                tlb[x].valid = false;
113                if (tlb[x].used) {
114                    tlb[x].used = false;
115                    usedEntries--;
116                }
117                lookupTable.erase(tlb[x].range);
118            }
119        }
120    }
121
122
123/*
124    i = lookupTable.find(tr);
125    if (i != lookupTable.end()) {
126        i->second->valid = false;
127        if (i->second->used) {
128            i->second->used = false;
129            usedEntries--;
130        }
131        freeList.push_front(i->second);
132        DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
133                i->second);
134        lookupTable.erase(i);
135    }
136*/
137
138    if (entry != -1) {
139        assert(entry < size && entry >= 0);
140        new_entry = &tlb[entry];
141    } else {
142        if (!freeList.empty()) {
143            new_entry = freeList.front();
144        } else {
145            x = lastReplaced;
146            do {
147                ++x;
148                if (x == size)
149                    x = 0;
150                if (x == lastReplaced)
151                    goto insertAllLocked;
152            } while (tlb[x].pte.locked());
153            lastReplaced = x;
154            new_entry = &tlb[x];
155        }
156        /*
157        for (x = 0; x < size; x++) {
158            if (!tlb[x].valid || !tlb[x].used)  {
159                new_entry = &tlb[x];
160                break;
161            }
162        }*/
163    }
164
165insertAllLocked:
166    // Update the last ently if their all locked
167    if (!new_entry) {
168        new_entry = &tlb[size-1];
169    }
170
171    freeList.remove(new_entry);
172    if (new_entry->valid && new_entry->used)
173        usedEntries--;
174
175    lookupTable.erase(new_entry->range);
176
177
178    DPRINTF(TLB, "Using entry: %#X\n", new_entry);
179
180    assert(PTE.valid());
181    new_entry->range.va = va;
182    new_entry->range.size = PTE.size() - 1;
183    new_entry->range.partitionId = partition_id;
184    new_entry->range.contextId = context_id;
185    new_entry->range.real = real;
186    new_entry->pte = PTE;
187    new_entry->used = true;;
188    new_entry->valid = true;
189    usedEntries++;
190
191
192
193    i = lookupTable.insert(new_entry->range, new_entry);
194    assert(i != lookupTable.end());
195
196    // If all entries have there used bit set, clear it on them all, but the
197    // one we just inserted
198    if (usedEntries == size) {
199        clearUsedBits();
200        new_entry->used = true;
201        usedEntries++;
202    }
203
204}
205
206
207TlbEntry*
208TLB::lookup(Addr va, int partition_id, bool real, int context_id)
209{
210    MapIter i;
211    TlbRange tr;
212    TlbEntry *t;
213
214    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
215            va, partition_id, context_id, real);
216    // Assemble full address structure
217    tr.va = va;
218    tr.size = MachineBytes;
219    tr.contextId = context_id;
220    tr.partitionId = partition_id;
221    tr.real = real;
222
223    // Try to find the entry
224    i = lookupTable.find(tr);
225    if (i == lookupTable.end()) {
226        DPRINTF(TLB, "TLB: No valid entry found\n");
227        return NULL;
228    }
229
230    // Mark the entries used bit and clear other used bits in needed
231    t = i->second;
232    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
233            t->pte.size());
234    if (!t->used) {
235        t->used = true;
236        usedEntries++;
237        if (usedEntries == size) {
238            clearUsedBits();
239            t->used = true;
240            usedEntries++;
241        }
242    }
243
244    return t;
245}
246
247void
248TLB::dumpAll()
249{
250    MapIter i;
251    for (int x = 0; x < size; x++) {
252        if (tlb[x].valid) {
253           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
254                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
255                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
256                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
257        }
258    }
259}
260
261void
262TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
263{
264    TlbRange tr;
265    MapIter i;
266
267    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
268            va, partition_id, context_id, real);
269
270    cacheValid = false;
271
272    // Assemble full address structure
273    tr.va = va;
274    tr.size = MachineBytes;
275    tr.contextId = context_id;
276    tr.partitionId = partition_id;
277    tr.real = real;
278
279    // Demap any entry that conflicts
280    i = lookupTable.find(tr);
281    if (i != lookupTable.end()) {
282        DPRINTF(IPR, "TLB: Demapped page\n");
283        i->second->valid = false;
284        if (i->second->used) {
285            i->second->used = false;
286            usedEntries--;
287        }
288        freeList.push_front(i->second);
289        DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second);
290        lookupTable.erase(i);
291    }
292}
293
294void
295TLB::demapContext(int partition_id, int context_id)
296{
297    int x;
298    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
299            partition_id, context_id);
300    cacheValid = false;
301    for (x = 0; x < size; x++) {
302        if (tlb[x].range.contextId == context_id &&
303            tlb[x].range.partitionId == partition_id) {
304            if (tlb[x].valid == true) {
305                freeList.push_front(&tlb[x]);
306                DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
307            }
308            tlb[x].valid = false;
309            if (tlb[x].used) {
310                tlb[x].used = false;
311                usedEntries--;
312            }
313            lookupTable.erase(tlb[x].range);
314        }
315    }
316}
317
318void
319TLB::demapAll(int partition_id)
320{
321    int x;
322    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
323    cacheValid = false;
324    for (x = 0; x < size; x++) {
325        if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
326            if (tlb[x].valid == true){
327                freeList.push_front(&tlb[x]);
328                DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
329            }
330            tlb[x].valid = false;
331            if (tlb[x].used) {
332                tlb[x].used = false;
333                usedEntries--;
334            }
335            lookupTable.erase(tlb[x].range);
336        }
337    }
338}
339
340void
341TLB::invalidateAll()
342{
343    int x;
344    cacheValid = false;
345
346    freeList.clear();
347    lookupTable.clear();
348    for (x = 0; x < size; x++) {
349        if (tlb[x].valid == true)
350            freeList.push_back(&tlb[x]);
351        tlb[x].valid = false;
352        tlb[x].used = false;
353    }
354    usedEntries = 0;
355}
356
357uint64_t
358TLB::TteRead(int entry) {
359    if (entry >= size)
360        panic("entry: %d\n", entry);
361
362    assert(entry < size);
363    if (tlb[entry].valid)
364        return tlb[entry].pte();
365    else
366        return (uint64_t)-1ll;
367}
368
369uint64_t
370TLB::TagRead(int entry) {
371    assert(entry < size);
372    uint64_t tag;
373    if (!tlb[entry].valid)
374        return (uint64_t)-1ll;
375
376    tag = tlb[entry].range.contextId;
377    tag |= tlb[entry].range.va;
378    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
379    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
380    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
381    return tag;
382}
383
384bool
385TLB::validVirtualAddress(Addr va, bool am)
386{
387    if (am)
388        return true;
389    if (va >= StartVAddrHole && va <= EndVAddrHole)
390        return false;
391    return true;
392}
393
394void
395TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
396        bool se, FaultTypes ft, int asi)
397{
398    uint64_t sfsr;
399    sfsr = tc->readMiscReg(reg);
400
401    if (sfsr & 0x1)
402        sfsr = 0x3;
403    else
404        sfsr = 1;
405
406    if (write)
407        sfsr |= 1 << 2;
408    sfsr |= ct << 4;
409    if (se)
410        sfsr |= 1 << 6;
411    sfsr |= ft << 7;
412    sfsr |= asi << 16;
413    tc->setMiscRegWithEffect(reg, sfsr);
414}
415
416void
417TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
418{
419    tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
420}
421
422void
423ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
424        bool se, FaultTypes ft, int asi)
425{
426    DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
427             (int)write, ct, ft, asi);
428    TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
429}
430
431void
432ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
433{
434    TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
435}
436
437void
438DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
439        bool se, FaultTypes ft, int asi)
440{
441    DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
442            a, (int)write, ct, ft, asi);
443    TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
444    tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
445}
446
447void
448DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
449{
450    TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
451}
452
453
454
455Fault
456ITB::translate(RequestPtr &req, ThreadContext *tc)
457{
458    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
459
460    Addr vaddr = req->getVaddr();
461    TlbEntry *e;
462
463    assert(req->getAsi() == ASI_IMPLICIT);
464
465    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
466            vaddr, req->getSize());
467
468    // Be fast if we can!
469    if (cacheValid && cacheState == tlbdata) {
470        if (cacheEntry) {
471            if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
472                cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
473                    req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
474                                  vaddr & cacheEntry->pte.size()-1 );
475                    return NoFault;
476            }
477        } else {
478            req->setPaddr(vaddr & PAddrImplMask);
479            return NoFault;
480        }
481    }
482
483    bool hpriv = bits(tlbdata,0,0);
484    bool red = bits(tlbdata,1,1);
485    bool priv = bits(tlbdata,2,2);
486    bool addr_mask = bits(tlbdata,3,3);
487    bool lsu_im = bits(tlbdata,4,4);
488
489    int part_id = bits(tlbdata,15,8);
490    int tl = bits(tlbdata,18,16);
491    int pri_context = bits(tlbdata,47,32);
492    int context;
493    ContextType ct;
494    int asi;
495    bool real = false;
496
497    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
498           priv, hpriv, red, lsu_im, part_id);
499
500    if (tl > 0) {
501        asi = ASI_N;
502        ct = Nucleus;
503        context = 0;
504    } else {
505        asi = ASI_P;
506        ct = Primary;
507        context = pri_context;
508    }
509
510    if ( hpriv || red ) {
511        cacheValid = true;
512        cacheState = tlbdata;
513        cacheEntry = NULL;
514        req->setPaddr(vaddr & PAddrImplMask);
515        return NoFault;
516    }
517
518    // If the access is unaligned trap
519    if (vaddr & 0x3) {
520        writeSfsr(tc, false, ct, false, OtherFault, asi);
521        return new MemAddressNotAligned;
522    }
523
524    if (addr_mask)
525        vaddr = vaddr & VAddrAMask;
526
527    if (!validVirtualAddress(vaddr, addr_mask)) {
528        writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
529        return new InstructionAccessException;
530    }
531
532    if (!lsu_im) {
533        e = lookup(vaddr, part_id, true);
534        real = true;
535        context = 0;
536    } else {
537        e = lookup(vaddr, part_id, false, context);
538    }
539
540    if (e == NULL || !e->valid) {
541        tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
542                vaddr & ~BytesInPageMask | context);
543        if (real)
544            return new InstructionRealTranslationMiss;
545        else
546            return new FastInstructionAccessMMUMiss;
547    }
548
549    // were not priviledged accesing priv page
550    if (!priv && e->pte.priv()) {
551        writeSfsr(tc, false, ct, false, PrivViolation, asi);
552        return new InstructionAccessException;
553    }
554
555    // cache translation date for next translation
556    cacheValid = true;
557    cacheState = tlbdata;
558    cacheEntry = e;
559
560    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
561                  vaddr & e->pte.size()-1 );
562    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
563    return NoFault;
564}
565
566
567
568Fault
569DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
570{
571    /* @todo this could really use some profiling and fixing to make it faster! */
572    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
573    Addr vaddr = req->getVaddr();
574    Addr size = req->getSize();
575    ASI asi;
576    asi = (ASI)req->getAsi();
577    bool implicit = false;
578    bool hpriv = bits(tlbdata,0,0);
579
580    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
581            vaddr, size, asi);
582
583    if (asi == ASI_IMPLICIT)
584        implicit = true;
585
586    if (hpriv && implicit) {
587        req->setPaddr(vaddr & PAddrImplMask);
588        return NoFault;
589    }
590
591    // Be fast if we can!
592    if (cacheValid &&  cacheState == tlbdata) {
593        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
594            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) {
595                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
596                              vaddr & cacheEntry[0]->pte.size()-1 );
597                return NoFault;
598        }
599        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
600            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) {
601                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
602                              vaddr & cacheEntry[1]->pte.size()-1 );
603                return NoFault;
604        }
605    }
606
607    bool red = bits(tlbdata,1,1);
608    bool priv = bits(tlbdata,2,2);
609    bool addr_mask = bits(tlbdata,3,3);
610    bool lsu_dm = bits(tlbdata,5,5);
611
612    int part_id = bits(tlbdata,15,8);
613    int tl = bits(tlbdata,18,16);
614    int pri_context = bits(tlbdata,47,32);
615    int sec_context = bits(tlbdata,47,32);
616
617    bool real = false;
618    ContextType ct = Primary;
619    int context = 0;
620
621    TlbEntry *e;
622
623    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
624           priv, hpriv, red, lsu_dm, part_id);
625
626    if (implicit) {
627        if (tl > 0) {
628            asi = ASI_N;
629            ct = Nucleus;
630            context = 0;
631        } else {
632            asi = ASI_P;
633            ct = Primary;
634            context = pri_context;
635        }
636    } else if (!hpriv && !red) {
637        if (tl > 0 || AsiIsNucleus(asi)) {
638            ct = Nucleus;
639            context = 0;
640        } else if (AsiIsSecondary(asi)) {
641            ct = Secondary;
642            context = sec_context;
643        } else {
644            context = pri_context;
645            ct = Primary; //???
646        }
647
648        // We need to check for priv level/asi priv
649        if (!priv && !AsiIsUnPriv(asi)) {
650            // It appears that context should be Nucleus in these cases?
651            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
652            return new PrivilegedAction;
653        }
654        if (priv && AsiIsHPriv(asi)) {
655            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
656            return new DataAccessException;
657        }
658
659    }
660    if (asi == ASI_P || asi == ASI_LDTX_P) {
661        ct = Primary;
662        context = pri_context;
663        goto continueDtbFlow;
664    }
665
666    if (!implicit) {
667        if (AsiIsLittle(asi))
668            panic("Little Endian ASIs not supported\n");
669        if (AsiIsBlock(asi))
670            panic("Block ASIs not supported\n");
671        if (AsiIsNoFault(asi))
672            panic("No Fault ASIs not supported\n");
673        if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL))
674            goto continueDtbFlow;
675
676        if (AsiIsTwin(asi))
677            panic("Twin ASIs not supported\n");
678        if (AsiIsPartialStore(asi))
679            panic("Partial Store ASIs not supported\n");
680        if (AsiIsInterrupt(asi))
681            panic("Interrupt ASIs not supported\n");
682
683        if (AsiIsMmu(asi))
684            goto handleMmuRegAccess;
685        if (AsiIsScratchPad(asi))
686            goto handleScratchRegAccess;
687        if (AsiIsQueue(asi))
688            goto handleQueueRegAccess;
689        if (AsiIsSparcError(asi))
690            goto handleSparcErrorRegAccess;
691
692        if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
693            panic("Accessing ASI %#X. Should we?\n", asi);
694    }
695
696continueDtbFlow:
697    // If the asi is unaligned trap
698    if (vaddr & size-1) {
699        writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
700        return new MemAddressNotAligned;
701    }
702
703    if (addr_mask)
704        vaddr = vaddr & VAddrAMask;
705
706    if (!validVirtualAddress(vaddr, addr_mask)) {
707        writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
708        return new DataAccessException;
709    }
710
711
712    if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) {
713        real = true;
714        context = 0;
715    };
716
717    if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
718        req->setPaddr(vaddr & PAddrImplMask);
719        return NoFault;
720    }
721
722    e = lookup(vaddr, part_id, real, context);
723
724    if (e == NULL || !e->valid) {
725        tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
726                vaddr & ~BytesInPageMask | context);
727        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
728        if (real)
729            return new DataRealTranslationMiss;
730        else
731            return new FastDataAccessMMUMiss;
732
733    }
734
735
736    if (write && !e->pte.writable()) {
737        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
738        return new FastDataAccessProtection;
739    }
740
741    if (e->pte.nofault() && !AsiIsNoFault(asi)) {
742        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
743        return new DataAccessException;
744    }
745
746    if (e->pte.sideffect())
747        req->setFlags(req->getFlags() | UNCACHEABLE);
748
749
750    if (!priv && e->pte.priv()) {
751        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
752        return new DataAccessException;
753    }
754
755    // cache translation date for next translation
756    cacheState = tlbdata;
757    if (!cacheValid) {
758        cacheEntry[1] = NULL;
759        cacheEntry[0] = NULL;
760    }
761
762    if (cacheEntry[0] != e && cacheEntry[1] != e) {
763        cacheEntry[1] = cacheEntry[0];
764        cacheEntry[0] = e;
765        cacheAsi[1] = cacheAsi[0];
766        cacheAsi[0] = asi;
767        if (implicit)
768            cacheAsi[0] = (ASI)0;
769    }
770    cacheValid = true;
771    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
772                  vaddr & e->pte.size()-1);
773    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
774    return NoFault;
775    /** Normal flow ends here. */
776
777handleScratchRegAccess:
778    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
779        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
780        return new DataAccessException;
781    }
782    goto regAccessOk;
783
784handleQueueRegAccess:
785    if (!priv  && !hpriv) {
786        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
787        return new PrivilegedAction;
788    }
789    if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
790        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
791        return new DataAccessException;
792    }
793    goto regAccessOk;
794
795handleSparcErrorRegAccess:
796    if (!hpriv) {
797        if (priv) {
798            writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
799            return new DataAccessException;
800        } else {
801            writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
802            return new PrivilegedAction;
803        }
804    }
805    goto regAccessOk;
806
807
808regAccessOk:
809handleMmuRegAccess:
810    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
811    req->setMmapedIpr(true);
812    req->setPaddr(req->getVaddr());
813    return NoFault;
814};
815
816Tick
817DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
818{
819    Addr va = pkt->getAddr();
820    ASI asi = (ASI)pkt->req->getAsi();
821    uint64_t temp, data;
822    uint64_t tsbtemp, cnftemp;
823
824    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
825         (uint32_t)pkt->req->getAsi(), pkt->getAddr());
826
827    switch (asi) {
828      case ASI_LSU_CONTROL_REG:
829        assert(va == 0);
830        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
831        break;
832      case ASI_MMU:
833        switch (va) {
834          case 0x8:
835            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
836            break;
837          case 0x10:
838            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
839            break;
840          default:
841            goto doMmuReadError;
842        }
843        break;
844      case ASI_QUEUE:
845        pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
846                    (va >> 4) - 0x3c));
847        break;
848      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
849        assert(va == 0);
850        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
851        break;
852      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
853        assert(va == 0);
854        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
855        break;
856      case ASI_DMMU_CTXT_ZERO_CONFIG:
857        assert(va == 0);
858        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
859        break;
860      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
861        assert(va == 0);
862        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
863        break;
864      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
865        assert(va == 0);
866        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
867        break;
868      case ASI_IMMU_CTXT_ZERO_CONFIG:
869        assert(va == 0);
870        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
871        break;
872      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
873        assert(va == 0);
874        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
875        break;
876      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
877        assert(va == 0);
878        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
879        break;
880      case ASI_DMMU_CTXT_NONZERO_CONFIG:
881        assert(va == 0);
882        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
883        break;
884      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
885        assert(va == 0);
886        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
887        break;
888      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
889        assert(va == 0);
890        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
891        break;
892      case ASI_IMMU_CTXT_NONZERO_CONFIG:
893        assert(va == 0);
894        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
895        break;
896      case ASI_SPARC_ERROR_STATUS_REG:
897        warn("returning 0 for  SPARC ERROR regsiter read\n");
898        pkt->set(0);
899        break;
900      case ASI_HYP_SCRATCHPAD:
901      case ASI_SCRATCHPAD:
902        pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
903        break;
904      case ASI_IMMU:
905        switch (va) {
906          case 0x0:
907            temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
908            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
909            break;
910          case 0x18:
911            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
912            break;
913          case 0x30:
914            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
915            break;
916          default:
917            goto doMmuReadError;
918        }
919        break;
920      case ASI_DMMU:
921        switch (va) {
922          case 0x0:
923            temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
924            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
925            break;
926          case 0x18:
927            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
928            break;
929          case 0x20:
930            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
931            break;
932          case 0x30:
933            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
934            break;
935          case 0x80:
936            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
937            break;
938          default:
939                goto doMmuReadError;
940        }
941        break;
942      case ASI_DMMU_TSB_PS0_PTR_REG:
943        temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
944        if (bits(temp,12,0) == 0) {
945            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
946            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
947        } else {
948            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
949            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
950        }
951        data = mbits(tsbtemp,63,13);
952        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
953            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
954        pkt->set(data);
955        break;
956      case ASI_DMMU_TSB_PS1_PTR_REG:
957        temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
958        if (bits(temp,12,0) == 0) {
959            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
960            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
961        } else {
962            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
963            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
964        }
965        data = mbits(tsbtemp,63,13);
966        if (bits(tsbtemp,12,12))
967            data |= ULL(1) << (13+bits(tsbtemp,3,0));
968        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
969            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
970        pkt->set(data);
971        break;
972      case ASI_IMMU_TSB_PS0_PTR_REG:
973        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
974        if (bits(temp,12,0) == 0) {
975            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
976            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
977        } else {
978            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
979            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
980        }
981        data = mbits(tsbtemp,63,13);
982        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
983            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
984        pkt->set(data);
985        break;
986      case ASI_IMMU_TSB_PS1_PTR_REG:
987        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
988        if (bits(temp,12,0) == 0) {
989            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
990            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
991        } else {
992            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
993            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
994        }
995        data = mbits(tsbtemp,63,13);
996        if (bits(tsbtemp,12,12))
997            data |= ULL(1) << (13+bits(tsbtemp,3,0));
998        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
999            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1000        pkt->set(data);
1001        break;
1002
1003      default:
1004doMmuReadError:
1005        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1006            (uint32_t)asi, va);
1007    }
1008    pkt->result = Packet::Success;
1009    return tc->getCpuPtr()->cycles(1);
1010}
1011
1012Tick
1013DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1014{
1015    uint64_t data = gtoh(pkt->get<uint64_t>());
1016    Addr va = pkt->getAddr();
1017    ASI asi = (ASI)pkt->req->getAsi();
1018
1019    Addr ta_insert;
1020    Addr va_insert;
1021    Addr ct_insert;
1022    int part_insert;
1023    int entry_insert = -1;
1024    bool real_insert;
1025    bool ignore;
1026    int part_id;
1027    int ctx_id;
1028    PageTableEntry pte;
1029
1030    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1031         (uint32_t)asi, va, data);
1032
1033    switch (asi) {
1034      case ASI_LSU_CONTROL_REG:
1035        assert(va == 0);
1036        tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1037        break;
1038      case ASI_MMU:
1039        switch (va) {
1040          case 0x8:
1041            tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1042            break;
1043          case 0x10:
1044            tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1045            break;
1046          default:
1047            goto doMmuWriteError;
1048        }
1049        break;
1050      case ASI_QUEUE:
1051        assert(mbits(data,13,6) == data);
1052        tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1053                    (va >> 4) - 0x3c, data);
1054        break;
1055      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1056        assert(va == 0);
1057        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1058        break;
1059      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1060        assert(va == 0);
1061        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1062        break;
1063      case ASI_DMMU_CTXT_ZERO_CONFIG:
1064        assert(va == 0);
1065        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1066        break;
1067      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1068        assert(va == 0);
1069        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1070        break;
1071      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1072        assert(va == 0);
1073        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1074        break;
1075      case ASI_IMMU_CTXT_ZERO_CONFIG:
1076        assert(va == 0);
1077        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1078        break;
1079      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1080        assert(va == 0);
1081        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1082        break;
1083      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1084        assert(va == 0);
1085        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1086        break;
1087      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1088        assert(va == 0);
1089        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1090        break;
1091      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1092        assert(va == 0);
1093        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1094        break;
1095      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1096        assert(va == 0);
1097        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1098        break;
1099      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1100        assert(va == 0);
1101        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1102        break;
1103      case ASI_SPARC_ERROR_EN_REG:
1104      case ASI_SPARC_ERROR_STATUS_REG:
1105        warn("Ignoring write to SPARC ERROR regsiter\n");
1106        break;
1107      case ASI_HYP_SCRATCHPAD:
1108      case ASI_SCRATCHPAD:
1109        tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1110        break;
1111      case ASI_IMMU:
1112        switch (va) {
1113          case 0x18:
1114            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1115            break;
1116          case 0x30:
1117            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1118            break;
1119          default:
1120            goto doMmuWriteError;
1121        }
1122        break;
1123      case ASI_ITLB_DATA_ACCESS_REG:
1124        entry_insert = bits(va, 8,3);
1125      case ASI_ITLB_DATA_IN_REG:
1126        assert(entry_insert != -1 || mbits(va,10,9) == va);
1127        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1128        va_insert = mbits(ta_insert, 63,13);
1129        ct_insert = mbits(ta_insert, 12,0);
1130        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1131        real_insert = bits(va, 9,9);
1132        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1133                PageTableEntry::sun4u);
1134        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1135                pte, entry_insert);
1136        break;
1137      case ASI_DTLB_DATA_ACCESS_REG:
1138        entry_insert = bits(va, 8,3);
1139      case ASI_DTLB_DATA_IN_REG:
1140        assert(entry_insert != -1 || mbits(va,10,9) == va);
1141        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1142        va_insert = mbits(ta_insert, 63,13);
1143        ct_insert = mbits(ta_insert, 12,0);
1144        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1145        real_insert = bits(va, 9,9);
1146        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1147                PageTableEntry::sun4u);
1148        insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1149        break;
1150      case ASI_IMMU_DEMAP:
1151        ignore = false;
1152        ctx_id = -1;
1153        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1154        switch (bits(va,5,4)) {
1155          case 0:
1156            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1157            break;
1158          case 1:
1159            ignore = true;
1160            break;
1161          case 3:
1162            ctx_id = 0;
1163            break;
1164          default:
1165            ignore = true;
1166        }
1167
1168        switch(bits(va,7,6)) {
1169          case 0: // demap page
1170            if (!ignore)
1171                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1172                        bits(va,9,9), ctx_id);
1173            break;
1174          case 1: //demap context
1175            if (!ignore)
1176                tc->getITBPtr()->demapContext(part_id, ctx_id);
1177            break;
1178          case 2:
1179            tc->getITBPtr()->demapAll(part_id);
1180            break;
1181          default:
1182            panic("Invalid type for IMMU demap\n");
1183        }
1184        break;
1185      case ASI_DMMU:
1186        switch (va) {
1187          case 0x18:
1188            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1189            break;
1190          case 0x30:
1191            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1192            break;
1193          case 0x80:
1194            tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1195            break;
1196          default:
1197            goto doMmuWriteError;
1198        }
1199        break;
1200      case ASI_DMMU_DEMAP:
1201        ignore = false;
1202        ctx_id = -1;
1203        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1204        switch (bits(va,5,4)) {
1205          case 0:
1206            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1207            break;
1208          case 1:
1209            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1210            break;
1211          case 3:
1212            ctx_id = 0;
1213            break;
1214          default:
1215            ignore = true;
1216        }
1217
1218        switch(bits(va,7,6)) {
1219          case 0: // demap page
1220            if (!ignore)
1221                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1222            break;
1223          case 1: //demap context
1224            if (!ignore)
1225                demapContext(part_id, ctx_id);
1226            break;
1227          case 2:
1228            demapAll(part_id);
1229            break;
1230          default:
1231            panic("Invalid type for IMMU demap\n");
1232        }
1233        break;
1234      default:
1235doMmuWriteError:
1236        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1237            (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1238    }
1239    pkt->result = Packet::Success;
1240    return tc->getCpuPtr()->cycles(1);
1241}
1242
1243void
1244TLB::serialize(std::ostream &os)
1245{
1246    panic("Need to implement serialize tlb for SPARC\n");
1247}
1248
1249void
1250TLB::unserialize(Checkpoint *cp, const std::string &section)
1251{
1252    panic("Need to implement unserialize tlb for SPARC\n");
1253}
1254
1255
1256DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1257
1258BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1259
1260    Param<int> size;
1261
1262END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1263
1264BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1265
1266    INIT_PARAM_DFLT(size, "TLB size", 48)
1267
1268END_INIT_SIM_OBJECT_PARAMS(ITB)
1269
1270
1271CREATE_SIM_OBJECT(ITB)
1272{
1273    return new ITB(getInstanceName(), size);
1274}
1275
1276REGISTER_SIM_OBJECT("SparcITB", ITB)
1277
1278BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1279
1280    Param<int> size;
1281
1282END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1283
1284BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1285
1286    INIT_PARAM_DFLT(size, "TLB size", 64)
1287
1288END_INIT_SIM_OBJECT_PARAMS(DTB)
1289
1290
1291CREATE_SIM_OBJECT(DTB)
1292{
1293    return new DTB(getInstanceName(), size);
1294}
1295
1296REGISTER_SIM_OBJECT("SparcDTB", DTB)
1297}
1298