tlb.cc revision 11150
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include <cstring> 32 33#include "arch/sparc/asi.hh" 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/registers.hh" 36#include "arch/sparc/tlb.hh" 37#include "base/bitfield.hh" 38#include "base/trace.hh" 39#include "cpu/base.hh" 40#include "cpu/thread_context.hh" 41#include "debug/IPR.hh" 42#include "debug/TLB.hh" 43#include "mem/packet_access.hh" 44#include "mem/request.hh" 45#include "sim/full_system.hh" 46#include "sim/system.hh" 47 48/* @todo remove some of the magic constants. -- ali 49 * */ 50namespace SparcISA { 51 52TLB::TLB(const Params *p) 53 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 54 cacheState(0), cacheValid(false) 55{ 56 // To make this work you'll have to change the hypervisor and OS 57 if (size > 64) 58 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 59 60 tlb = new TlbEntry[size]; 61 std::memset(tlb, 0, sizeof(TlbEntry) * size); 62 63 for (int x = 0; x < size; x++) 64 freeList.push_back(&tlb[x]); 65 66 c0_tsb_ps0 = 0; 67 c0_tsb_ps1 = 0; 68 c0_config = 0; 69 cx_tsb_ps0 = 0; 70 cx_tsb_ps1 = 0; 71 cx_config = 0; 72 sfsr = 0; 73 tag_access = 0; 74 sfar = 0; 75 cacheEntry[0] = NULL; 76 cacheEntry[1] = NULL; 77} 78 79void 80TLB::clearUsedBits() 81{ 82 MapIter i; 83 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 84 TlbEntry *t = i->second; 85 if (!t->pte.locked()) { 86 t->used = false; 87 usedEntries--; 88 } 89 } 90} 91 92 93void 94TLB::insert(Addr va, int partition_id, int context_id, bool real, 95 const PageTableEntry& PTE, int entry) 96{ 97 MapIter i; 98 TlbEntry *new_entry = NULL; 99// TlbRange tr; 100 int x; 101 102 cacheValid = false; 103 va &= ~(PTE.size()-1); 104 /* tr.va = va; 105 tr.size = PTE.size() - 1; 106 tr.contextId = context_id; 107 tr.partitionId = partition_id; 108 tr.real = real; 109*/ 110 111 DPRINTF(TLB, 112 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 113 va, PTE.paddr(), partition_id, context_id, (int)real, entry); 114 115 // Demap any entry that conflicts 116 for (x = 0; x < size; x++) { 117 if (tlb[x].range.real == real && 118 tlb[x].range.partitionId == partition_id && 119 tlb[x].range.va < va + PTE.size() - 1 && 120 tlb[x].range.va + tlb[x].range.size >= va && 121 (real || tlb[x].range.contextId == context_id )) 122 { 123 if (tlb[x].valid) { 124 freeList.push_front(&tlb[x]); 125 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 126 127 tlb[x].valid = false; 128 if (tlb[x].used) { 129 tlb[x].used = false; 130 usedEntries--; 131 } 132 lookupTable.erase(tlb[x].range); 133 } 134 } 135 } 136 137 if (entry != -1) { 138 assert(entry < size && entry >= 0); 139 new_entry = &tlb[entry]; 140 } else { 141 if (!freeList.empty()) { 142 new_entry = freeList.front(); 143 } else { 144 x = lastReplaced; 145 do { 146 ++x; 147 if (x == size) 148 x = 0; 149 if (x == lastReplaced) 150 goto insertAllLocked; 151 } while (tlb[x].pte.locked()); 152 lastReplaced = x; 153 new_entry = &tlb[x]; 154 } 155 } 156 157insertAllLocked: 158 // Update the last ently if their all locked 159 if (!new_entry) { 160 new_entry = &tlb[size-1]; 161 } 162 163 freeList.remove(new_entry); 164 if (new_entry->valid && new_entry->used) 165 usedEntries--; 166 if (new_entry->valid) 167 lookupTable.erase(new_entry->range); 168 169 170 assert(PTE.valid()); 171 new_entry->range.va = va; 172 new_entry->range.size = PTE.size() - 1; 173 new_entry->range.partitionId = partition_id; 174 new_entry->range.contextId = context_id; 175 new_entry->range.real = real; 176 new_entry->pte = PTE; 177 new_entry->used = true;; 178 new_entry->valid = true; 179 usedEntries++; 180 181 i = lookupTable.insert(new_entry->range, new_entry); 182 assert(i != lookupTable.end()); 183 184 // If all entries have their used bit set, clear it on them all, 185 // but the one we just inserted 186 if (usedEntries == size) { 187 clearUsedBits(); 188 new_entry->used = true; 189 usedEntries++; 190 } 191} 192 193 194TlbEntry* 195TLB::lookup(Addr va, int partition_id, bool real, int context_id, 196 bool update_used) 197{ 198 MapIter i; 199 TlbRange tr; 200 TlbEntry *t; 201 202 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 203 va, partition_id, context_id, real); 204 // Assemble full address structure 205 tr.va = va; 206 tr.size = 1; 207 tr.contextId = context_id; 208 tr.partitionId = partition_id; 209 tr.real = real; 210 211 // Try to find the entry 212 i = lookupTable.find(tr); 213 if (i == lookupTable.end()) { 214 DPRINTF(TLB, "TLB: No valid entry found\n"); 215 return NULL; 216 } 217 218 // Mark the entries used bit and clear other used bits in needed 219 t = i->second; 220 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 221 t->pte.size()); 222 223 // Update the used bits only if this is a real access (not a fake 224 // one from virttophys() 225 if (!t->used && update_used) { 226 t->used = true; 227 usedEntries++; 228 if (usedEntries == size) { 229 clearUsedBits(); 230 t->used = true; 231 usedEntries++; 232 } 233 } 234 235 return t; 236} 237 238void 239TLB::dumpAll() 240{ 241 MapIter i; 242 for (int x = 0; x < size; x++) { 243 if (tlb[x].valid) { 244 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 245 x, tlb[x].range.partitionId, tlb[x].range.contextId, 246 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 247 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 248 } 249 } 250} 251 252void 253TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 254{ 255 TlbRange tr; 256 MapIter i; 257 258 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 259 va, partition_id, context_id, real); 260 261 cacheValid = false; 262 263 // Assemble full address structure 264 tr.va = va; 265 tr.size = 1; 266 tr.contextId = context_id; 267 tr.partitionId = partition_id; 268 tr.real = real; 269 270 // Demap any entry that conflicts 271 i = lookupTable.find(tr); 272 if (i != lookupTable.end()) { 273 DPRINTF(IPR, "TLB: Demapped page\n"); 274 i->second->valid = false; 275 if (i->second->used) { 276 i->second->used = false; 277 usedEntries--; 278 } 279 freeList.push_front(i->second); 280 lookupTable.erase(i); 281 } 282} 283 284void 285TLB::demapContext(int partition_id, int context_id) 286{ 287 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 288 partition_id, context_id); 289 cacheValid = false; 290 for (int x = 0; x < size; x++) { 291 if (tlb[x].range.contextId == context_id && 292 tlb[x].range.partitionId == partition_id) { 293 if (tlb[x].valid) { 294 freeList.push_front(&tlb[x]); 295 } 296 tlb[x].valid = false; 297 if (tlb[x].used) { 298 tlb[x].used = false; 299 usedEntries--; 300 } 301 lookupTable.erase(tlb[x].range); 302 } 303 } 304} 305 306void 307TLB::demapAll(int partition_id) 308{ 309 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 310 cacheValid = false; 311 for (int x = 0; x < size; x++) { 312 if (tlb[x].valid && !tlb[x].pte.locked() && 313 tlb[x].range.partitionId == partition_id) { 314 freeList.push_front(&tlb[x]); 315 tlb[x].valid = false; 316 if (tlb[x].used) { 317 tlb[x].used = false; 318 usedEntries--; 319 } 320 lookupTable.erase(tlb[x].range); 321 } 322 } 323} 324 325void 326TLB::flushAll() 327{ 328 cacheValid = false; 329 lookupTable.clear(); 330 331 for (int x = 0; x < size; x++) { 332 if (tlb[x].valid) 333 freeList.push_back(&tlb[x]); 334 tlb[x].valid = false; 335 tlb[x].used = false; 336 } 337 usedEntries = 0; 338} 339 340uint64_t 341TLB::TteRead(int entry) 342{ 343 if (entry >= size) 344 panic("entry: %d\n", entry); 345 346 assert(entry < size); 347 if (tlb[entry].valid) 348 return tlb[entry].pte(); 349 else 350 return (uint64_t)-1ll; 351} 352 353uint64_t 354TLB::TagRead(int entry) 355{ 356 assert(entry < size); 357 uint64_t tag; 358 if (!tlb[entry].valid) 359 return (uint64_t)-1ll; 360 361 tag = tlb[entry].range.contextId; 362 tag |= tlb[entry].range.va; 363 tag |= (uint64_t)tlb[entry].range.partitionId << 61; 364 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 365 tag |= (uint64_t)~tlb[entry].pte._size() << 56; 366 return tag; 367} 368 369bool 370TLB::validVirtualAddress(Addr va, bool am) 371{ 372 if (am) 373 return true; 374 if (va >= StartVAddrHole && va <= EndVAddrHole) 375 return false; 376 return true; 377} 378 379void 380TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 381{ 382 if (sfsr & 0x1) 383 sfsr = 0x3; 384 else 385 sfsr = 1; 386 387 if (write) 388 sfsr |= 1 << 2; 389 sfsr |= ct << 4; 390 if (se) 391 sfsr |= 1 << 6; 392 sfsr |= ft << 7; 393 sfsr |= asi << 16; 394} 395 396void 397TLB::writeTagAccess(Addr va, int context) 398{ 399 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 400 va, context, mbits(va, 63,13) | mbits(context,12,0)); 401 402 tag_access = mbits(va, 63,13) | mbits(context,12,0); 403} 404 405void 406TLB::writeSfsr(Addr a, bool write, ContextType ct, 407 bool se, FaultTypes ft, int asi) 408{ 409 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 410 a, (int)write, ct, ft, asi); 411 TLB::writeSfsr(write, ct, se, ft, asi); 412 sfar = a; 413} 414 415Fault 416TLB::translateInst(RequestPtr req, ThreadContext *tc) 417{ 418 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 419 420 Addr vaddr = req->getVaddr(); 421 TlbEntry *e; 422 423 assert(req->getArchFlags() == ASI_IMPLICIT); 424 425 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 426 vaddr, req->getSize()); 427 428 // Be fast if we can! 429 if (cacheValid && cacheState == tlbdata) { 430 if (cacheEntry[0]) { 431 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 432 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 433 req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 434 return NoFault; 435 } 436 } else { 437 req->setPaddr(vaddr & PAddrImplMask); 438 return NoFault; 439 } 440 } 441 442 bool hpriv = bits(tlbdata,0,0); 443 bool red = bits(tlbdata,1,1); 444 bool priv = bits(tlbdata,2,2); 445 bool addr_mask = bits(tlbdata,3,3); 446 bool lsu_im = bits(tlbdata,4,4); 447 448 int part_id = bits(tlbdata,15,8); 449 int tl = bits(tlbdata,18,16); 450 int pri_context = bits(tlbdata,47,32); 451 int context; 452 ContextType ct; 453 int asi; 454 bool real = false; 455 456 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 457 priv, hpriv, red, lsu_im, part_id); 458 459 if (tl > 0) { 460 asi = ASI_N; 461 ct = Nucleus; 462 context = 0; 463 } else { 464 asi = ASI_P; 465 ct = Primary; 466 context = pri_context; 467 } 468 469 if ( hpriv || red ) { 470 cacheValid = true; 471 cacheState = tlbdata; 472 cacheEntry[0] = NULL; 473 req->setPaddr(vaddr & PAddrImplMask); 474 return NoFault; 475 } 476 477 // If the access is unaligned trap 478 if (vaddr & 0x3) { 479 writeSfsr(false, ct, false, OtherFault, asi); 480 return std::make_shared<MemAddressNotAligned>(); 481 } 482 483 if (addr_mask) 484 vaddr = vaddr & VAddrAMask; 485 486 if (!validVirtualAddress(vaddr, addr_mask)) { 487 writeSfsr(false, ct, false, VaOutOfRange, asi); 488 return std::make_shared<InstructionAccessException>(); 489 } 490 491 if (!lsu_im) { 492 e = lookup(vaddr, part_id, true); 493 real = true; 494 context = 0; 495 } else { 496 e = lookup(vaddr, part_id, false, context); 497 } 498 499 if (e == NULL || !e->valid) { 500 writeTagAccess(vaddr, context); 501 if (real) { 502 return std::make_shared<InstructionRealTranslationMiss>(); 503 } else { 504 if (FullSystem) 505 return std::make_shared<FastInstructionAccessMMUMiss>(); 506 else 507 return std::make_shared<FastInstructionAccessMMUMiss>( 508 req->getVaddr()); 509 } 510 } 511 512 // were not priviledged accesing priv page 513 if (!priv && e->pte.priv()) { 514 writeTagAccess(vaddr, context); 515 writeSfsr(false, ct, false, PrivViolation, asi); 516 return std::make_shared<InstructionAccessException>(); 517 } 518 519 // cache translation date for next translation 520 cacheValid = true; 521 cacheState = tlbdata; 522 cacheEntry[0] = e; 523 524 req->setPaddr(e->pte.translate(vaddr)); 525 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 526 return NoFault; 527} 528 529Fault 530TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 531{ 532 /* 533 * @todo this could really use some profiling and fixing to make 534 * it faster! 535 */ 536 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 537 Addr vaddr = req->getVaddr(); 538 Addr size = req->getSize(); 539 ASI asi; 540 asi = (ASI)req->getArchFlags(); 541 bool implicit = false; 542 bool hpriv = bits(tlbdata,0,0); 543 bool unaligned = vaddr & (size - 1); 544 545 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 546 vaddr, size, asi); 547 548 if (lookupTable.size() != 64 - freeList.size()) 549 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 550 freeList.size()); 551 if (asi == ASI_IMPLICIT) 552 implicit = true; 553 554 // Only use the fast path here if there doesn't need to be an unaligned 555 // trap later 556 if (!unaligned) { 557 if (hpriv && implicit) { 558 req->setPaddr(vaddr & PAddrImplMask); 559 return NoFault; 560 } 561 562 // Be fast if we can! 563 if (cacheValid && cacheState == tlbdata) { 564 565 566 567 if (cacheEntry[0]) { 568 TlbEntry *ce = cacheEntry[0]; 569 Addr ce_va = ce->range.va; 570 if (cacheAsi[0] == asi && 571 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 572 (!write || ce->pte.writable())) { 573 req->setPaddr(ce->pte.translate(vaddr)); 574 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 575 req->setFlags( 576 Request::UNCACHEABLE | Request::STRICT_ORDER); 577 } 578 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 579 return NoFault; 580 } // if matched 581 } // if cache entry valid 582 if (cacheEntry[1]) { 583 TlbEntry *ce = cacheEntry[1]; 584 Addr ce_va = ce->range.va; 585 if (cacheAsi[1] == asi && 586 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 587 (!write || ce->pte.writable())) { 588 req->setPaddr(ce->pte.translate(vaddr)); 589 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 590 req->setFlags( 591 Request::UNCACHEABLE | Request::STRICT_ORDER); 592 } 593 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 594 return NoFault; 595 } // if matched 596 } // if cache entry valid 597 } 598 } 599 600 bool red = bits(tlbdata,1,1); 601 bool priv = bits(tlbdata,2,2); 602 bool addr_mask = bits(tlbdata,3,3); 603 bool lsu_dm = bits(tlbdata,5,5); 604 605 int part_id = bits(tlbdata,15,8); 606 int tl = bits(tlbdata,18,16); 607 int pri_context = bits(tlbdata,47,32); 608 int sec_context = bits(tlbdata,63,48); 609 610 bool real = false; 611 ContextType ct = Primary; 612 int context = 0; 613 614 TlbEntry *e; 615 616 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 617 priv, hpriv, red, lsu_dm, part_id); 618 619 if (implicit) { 620 if (tl > 0) { 621 asi = ASI_N; 622 ct = Nucleus; 623 context = 0; 624 } else { 625 asi = ASI_P; 626 ct = Primary; 627 context = pri_context; 628 } 629 } else { 630 // We need to check for priv level/asi priv 631 if (!priv && !hpriv && !asiIsUnPriv(asi)) { 632 // It appears that context should be Nucleus in these cases? 633 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 634 return std::make_shared<PrivilegedAction>(); 635 } 636 637 if (!hpriv && asiIsHPriv(asi)) { 638 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 639 return std::make_shared<DataAccessException>(); 640 } 641 642 if (asiIsPrimary(asi)) { 643 context = pri_context; 644 ct = Primary; 645 } else if (asiIsSecondary(asi)) { 646 context = sec_context; 647 ct = Secondary; 648 } else if (asiIsNucleus(asi)) { 649 ct = Nucleus; 650 context = 0; 651 } else { // ???? 652 ct = Primary; 653 context = pri_context; 654 } 655 } 656 657 if (!implicit && asi != ASI_P && asi != ASI_S) { 658 if (asiIsLittle(asi)) 659 panic("Little Endian ASIs not supported\n"); 660 661 //XXX It's unclear from looking at the documentation how a no fault 662 // load differs from a regular one, other than what happens concerning 663 // nfo and e bits in the TTE 664// if (asiIsNoFault(asi)) 665// panic("No Fault ASIs not supported\n"); 666 667 if (asiIsPartialStore(asi)) 668 panic("Partial Store ASIs not supported\n"); 669 670 if (asiIsCmt(asi)) 671 panic("Cmt ASI registers not implmented\n"); 672 673 if (asiIsInterrupt(asi)) 674 goto handleIntRegAccess; 675 if (asiIsMmu(asi)) 676 goto handleMmuRegAccess; 677 if (asiIsScratchPad(asi)) 678 goto handleScratchRegAccess; 679 if (asiIsQueue(asi)) 680 goto handleQueueRegAccess; 681 if (asiIsSparcError(asi)) 682 goto handleSparcErrorRegAccess; 683 684 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 685 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 686 panic("Accessing ASI %#X. Should we?\n", asi); 687 } 688 689 // If the asi is unaligned trap 690 if (unaligned) { 691 writeSfsr(vaddr, false, ct, false, OtherFault, asi); 692 return std::make_shared<MemAddressNotAligned>(); 693 } 694 695 if (addr_mask) 696 vaddr = vaddr & VAddrAMask; 697 698 if (!validVirtualAddress(vaddr, addr_mask)) { 699 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 700 return std::make_shared<DataAccessException>(); 701 } 702 703 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 704 real = true; 705 context = 0; 706 } 707 708 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 709 req->setPaddr(vaddr & PAddrImplMask); 710 return NoFault; 711 } 712 713 e = lookup(vaddr, part_id, real, context); 714 715 if (e == NULL || !e->valid) { 716 writeTagAccess(vaddr, context); 717 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 718 if (real) { 719 return std::make_shared<DataRealTranslationMiss>(); 720 } else { 721 if (FullSystem) 722 return std::make_shared<FastDataAccessMMUMiss>(); 723 else 724 return std::make_shared<FastDataAccessMMUMiss>( 725 req->getVaddr()); 726 } 727 728 } 729 730 if (!priv && e->pte.priv()) { 731 writeTagAccess(vaddr, context); 732 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 733 return std::make_shared<DataAccessException>(); 734 } 735 736 if (write && !e->pte.writable()) { 737 writeTagAccess(vaddr, context); 738 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 739 return std::make_shared<FastDataAccessProtection>(); 740 } 741 742 if (e->pte.nofault() && !asiIsNoFault(asi)) { 743 writeTagAccess(vaddr, context); 744 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 745 return std::make_shared<DataAccessException>(); 746 } 747 748 if (e->pte.sideffect() && asiIsNoFault(asi)) { 749 writeTagAccess(vaddr, context); 750 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 751 return std::make_shared<DataAccessException>(); 752 } 753 754 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 755 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 756 757 // cache translation date for next translation 758 cacheState = tlbdata; 759 if (!cacheValid) { 760 cacheEntry[1] = NULL; 761 cacheEntry[0] = NULL; 762 } 763 764 if (cacheEntry[0] != e && cacheEntry[1] != e) { 765 cacheEntry[1] = cacheEntry[0]; 766 cacheEntry[0] = e; 767 cacheAsi[1] = cacheAsi[0]; 768 cacheAsi[0] = asi; 769 if (implicit) 770 cacheAsi[0] = (ASI)0; 771 } 772 cacheValid = true; 773 req->setPaddr(e->pte.translate(vaddr)); 774 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 775 return NoFault; 776 777 /** Normal flow ends here. */ 778handleIntRegAccess: 779 if (!hpriv) { 780 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 781 if (priv) 782 return std::make_shared<DataAccessException>(); 783 else 784 return std::make_shared<PrivilegedAction>(); 785 } 786 787 if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 788 (asi == ASI_SWVR_UDB_INTR_R && write)) { 789 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 790 return std::make_shared<DataAccessException>(); 791 } 792 793 goto regAccessOk; 794 795 796handleScratchRegAccess: 797 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 798 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 799 return std::make_shared<DataAccessException>(); 800 } 801 goto regAccessOk; 802 803handleQueueRegAccess: 804 if (!priv && !hpriv) { 805 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 806 return std::make_shared<PrivilegedAction>(); 807 } 808 if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 809 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 810 return std::make_shared<DataAccessException>(); 811 } 812 goto regAccessOk; 813 814handleSparcErrorRegAccess: 815 if (!hpriv) { 816 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 817 if (priv) 818 return std::make_shared<DataAccessException>(); 819 else 820 return std::make_shared<PrivilegedAction>(); 821 } 822 goto regAccessOk; 823 824 825regAccessOk: 826handleMmuRegAccess: 827 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 828 req->setFlags(Request::MMAPPED_IPR); 829 req->setPaddr(req->getVaddr()); 830 return NoFault; 831}; 832 833Fault 834TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 835{ 836 if (mode == Execute) 837 return translateInst(req, tc); 838 else 839 return translateData(req, tc, mode == Write); 840} 841 842void 843TLB::translateTiming(RequestPtr req, ThreadContext *tc, 844 Translation *translation, Mode mode) 845{ 846 assert(translation); 847 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 848} 849 850Fault 851TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 852{ 853 panic("Not implemented\n"); 854 return NoFault; 855} 856 857Fault 858TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 859{ 860 return NoFault; 861} 862 863Cycles 864TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 865{ 866 Addr va = pkt->getAddr(); 867 ASI asi = (ASI)pkt->req->getArchFlags(); 868 uint64_t temp; 869 870 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 871 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr()); 872 873 TLB *itb = tc->getITBPtr(); 874 875 switch (asi) { 876 case ASI_LSU_CONTROL_REG: 877 assert(va == 0); 878 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 879 break; 880 case ASI_MMU: 881 switch (va) { 882 case 0x8: 883 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 884 break; 885 case 0x10: 886 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 887 break; 888 default: 889 goto doMmuReadError; 890 } 891 break; 892 case ASI_QUEUE: 893 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 894 (va >> 4) - 0x3c)); 895 break; 896 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 897 assert(va == 0); 898 pkt->set(c0_tsb_ps0); 899 break; 900 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 901 assert(va == 0); 902 pkt->set(c0_tsb_ps1); 903 break; 904 case ASI_DMMU_CTXT_ZERO_CONFIG: 905 assert(va == 0); 906 pkt->set(c0_config); 907 break; 908 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 909 assert(va == 0); 910 pkt->set(itb->c0_tsb_ps0); 911 break; 912 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 913 assert(va == 0); 914 pkt->set(itb->c0_tsb_ps1); 915 break; 916 case ASI_IMMU_CTXT_ZERO_CONFIG: 917 assert(va == 0); 918 pkt->set(itb->c0_config); 919 break; 920 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 921 assert(va == 0); 922 pkt->set(cx_tsb_ps0); 923 break; 924 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 925 assert(va == 0); 926 pkt->set(cx_tsb_ps1); 927 break; 928 case ASI_DMMU_CTXT_NONZERO_CONFIG: 929 assert(va == 0); 930 pkt->set(cx_config); 931 break; 932 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 933 assert(va == 0); 934 pkt->set(itb->cx_tsb_ps0); 935 break; 936 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 937 assert(va == 0); 938 pkt->set(itb->cx_tsb_ps1); 939 break; 940 case ASI_IMMU_CTXT_NONZERO_CONFIG: 941 assert(va == 0); 942 pkt->set(itb->cx_config); 943 break; 944 case ASI_SPARC_ERROR_STATUS_REG: 945 pkt->set((uint64_t)0); 946 break; 947 case ASI_HYP_SCRATCHPAD: 948 case ASI_SCRATCHPAD: 949 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 950 break; 951 case ASI_IMMU: 952 switch (va) { 953 case 0x0: 954 temp = itb->tag_access; 955 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 956 break; 957 case 0x18: 958 pkt->set(itb->sfsr); 959 break; 960 case 0x30: 961 pkt->set(itb->tag_access); 962 break; 963 default: 964 goto doMmuReadError; 965 } 966 break; 967 case ASI_DMMU: 968 switch (va) { 969 case 0x0: 970 temp = tag_access; 971 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 972 break; 973 case 0x18: 974 pkt->set(sfsr); 975 break; 976 case 0x20: 977 pkt->set(sfar); 978 break; 979 case 0x30: 980 pkt->set(tag_access); 981 break; 982 case 0x80: 983 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 984 break; 985 default: 986 goto doMmuReadError; 987 } 988 break; 989 case ASI_DMMU_TSB_PS0_PTR_REG: 990 pkt->set(MakeTsbPtr(Ps0, 991 tag_access, 992 c0_tsb_ps0, 993 c0_config, 994 cx_tsb_ps0, 995 cx_config)); 996 break; 997 case ASI_DMMU_TSB_PS1_PTR_REG: 998 pkt->set(MakeTsbPtr(Ps1, 999 tag_access, 1000 c0_tsb_ps1, 1001 c0_config, 1002 cx_tsb_ps1, 1003 cx_config)); 1004 break; 1005 case ASI_IMMU_TSB_PS0_PTR_REG: 1006 pkt->set(MakeTsbPtr(Ps0, 1007 itb->tag_access, 1008 itb->c0_tsb_ps0, 1009 itb->c0_config, 1010 itb->cx_tsb_ps0, 1011 itb->cx_config)); 1012 break; 1013 case ASI_IMMU_TSB_PS1_PTR_REG: 1014 pkt->set(MakeTsbPtr(Ps1, 1015 itb->tag_access, 1016 itb->c0_tsb_ps1, 1017 itb->c0_config, 1018 itb->cx_tsb_ps1, 1019 itb->cx_config)); 1020 break; 1021 case ASI_SWVR_INTR_RECEIVE: 1022 { 1023 SparcISA::Interrupts * interrupts = 1024 dynamic_cast<SparcISA::Interrupts *>( 1025 tc->getCpuPtr()->getInterruptController(0)); 1026 pkt->set(interrupts->get_vec(IT_INT_VEC)); 1027 } 1028 break; 1029 case ASI_SWVR_UDB_INTR_R: 1030 { 1031 SparcISA::Interrupts * interrupts = 1032 dynamic_cast<SparcISA::Interrupts *>( 1033 tc->getCpuPtr()->getInterruptController(0)); 1034 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 1035 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp); 1036 pkt->set(temp); 1037 } 1038 break; 1039 default: 1040doMmuReadError: 1041 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 1042 (uint32_t)asi, va); 1043 } 1044 pkt->makeAtomicResponse(); 1045 return Cycles(1); 1046} 1047 1048Cycles 1049TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1050{ 1051 uint64_t data = pkt->get<uint64_t>(); 1052 Addr va = pkt->getAddr(); 1053 ASI asi = (ASI)pkt->req->getArchFlags(); 1054 1055 Addr ta_insert; 1056 Addr va_insert; 1057 Addr ct_insert; 1058 int part_insert; 1059 int entry_insert = -1; 1060 bool real_insert; 1061 bool ignore; 1062 int part_id; 1063 int ctx_id; 1064 PageTableEntry pte; 1065 1066 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1067 (uint32_t)asi, va, data); 1068 1069 TLB *itb = tc->getITBPtr(); 1070 1071 switch (asi) { 1072 case ASI_LSU_CONTROL_REG: 1073 assert(va == 0); 1074 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 1075 break; 1076 case ASI_MMU: 1077 switch (va) { 1078 case 0x8: 1079 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 1080 break; 1081 case 0x10: 1082 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 1083 break; 1084 default: 1085 goto doMmuWriteError; 1086 } 1087 break; 1088 case ASI_QUEUE: 1089 assert(mbits(data,13,6) == data); 1090 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 1091 (va >> 4) - 0x3c, data); 1092 break; 1093 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1094 assert(va == 0); 1095 c0_tsb_ps0 = data; 1096 break; 1097 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1098 assert(va == 0); 1099 c0_tsb_ps1 = data; 1100 break; 1101 case ASI_DMMU_CTXT_ZERO_CONFIG: 1102 assert(va == 0); 1103 c0_config = data; 1104 break; 1105 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1106 assert(va == 0); 1107 itb->c0_tsb_ps0 = data; 1108 break; 1109 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1110 assert(va == 0); 1111 itb->c0_tsb_ps1 = data; 1112 break; 1113 case ASI_IMMU_CTXT_ZERO_CONFIG: 1114 assert(va == 0); 1115 itb->c0_config = data; 1116 break; 1117 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1118 assert(va == 0); 1119 cx_tsb_ps0 = data; 1120 break; 1121 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1122 assert(va == 0); 1123 cx_tsb_ps1 = data; 1124 break; 1125 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1126 assert(va == 0); 1127 cx_config = data; 1128 break; 1129 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1130 assert(va == 0); 1131 itb->cx_tsb_ps0 = data; 1132 break; 1133 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1134 assert(va == 0); 1135 itb->cx_tsb_ps1 = data; 1136 break; 1137 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1138 assert(va == 0); 1139 itb->cx_config = data; 1140 break; 1141 case ASI_SPARC_ERROR_EN_REG: 1142 case ASI_SPARC_ERROR_STATUS_REG: 1143 inform("Ignoring write to SPARC ERROR regsiter\n"); 1144 break; 1145 case ASI_HYP_SCRATCHPAD: 1146 case ASI_SCRATCHPAD: 1147 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1148 break; 1149 case ASI_IMMU: 1150 switch (va) { 1151 case 0x18: 1152 itb->sfsr = data; 1153 break; 1154 case 0x30: 1155 sext<59>(bits(data, 59,0)); 1156 itb->tag_access = data; 1157 break; 1158 default: 1159 goto doMmuWriteError; 1160 } 1161 break; 1162 case ASI_ITLB_DATA_ACCESS_REG: 1163 entry_insert = bits(va, 8,3); 1164 case ASI_ITLB_DATA_IN_REG: 1165 assert(entry_insert != -1 || mbits(va,10,9) == va); 1166 ta_insert = itb->tag_access; 1167 va_insert = mbits(ta_insert, 63,13); 1168 ct_insert = mbits(ta_insert, 12,0); 1169 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1170 real_insert = bits(va, 9,9); 1171 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1172 PageTableEntry::sun4u); 1173 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1174 pte, entry_insert); 1175 break; 1176 case ASI_DTLB_DATA_ACCESS_REG: 1177 entry_insert = bits(va, 8,3); 1178 case ASI_DTLB_DATA_IN_REG: 1179 assert(entry_insert != -1 || mbits(va,10,9) == va); 1180 ta_insert = tag_access; 1181 va_insert = mbits(ta_insert, 63,13); 1182 ct_insert = mbits(ta_insert, 12,0); 1183 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1184 real_insert = bits(va, 9,9); 1185 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1186 PageTableEntry::sun4u); 1187 insert(va_insert, part_insert, ct_insert, real_insert, pte, 1188 entry_insert); 1189 break; 1190 case ASI_IMMU_DEMAP: 1191 ignore = false; 1192 ctx_id = -1; 1193 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1194 switch (bits(va,5,4)) { 1195 case 0: 1196 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1197 break; 1198 case 1: 1199 ignore = true; 1200 break; 1201 case 3: 1202 ctx_id = 0; 1203 break; 1204 default: 1205 ignore = true; 1206 } 1207 1208 switch (bits(va,7,6)) { 1209 case 0: // demap page 1210 if (!ignore) 1211 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1212 bits(va,9,9), ctx_id); 1213 break; 1214 case 1: // demap context 1215 if (!ignore) 1216 tc->getITBPtr()->demapContext(part_id, ctx_id); 1217 break; 1218 case 2: 1219 tc->getITBPtr()->demapAll(part_id); 1220 break; 1221 default: 1222 panic("Invalid type for IMMU demap\n"); 1223 } 1224 break; 1225 case ASI_DMMU: 1226 switch (va) { 1227 case 0x18: 1228 sfsr = data; 1229 break; 1230 case 0x30: 1231 sext<59>(bits(data, 59,0)); 1232 tag_access = data; 1233 break; 1234 case 0x80: 1235 tc->setMiscReg(MISCREG_MMU_PART_ID, data); 1236 break; 1237 default: 1238 goto doMmuWriteError; 1239 } 1240 break; 1241 case ASI_DMMU_DEMAP: 1242 ignore = false; 1243 ctx_id = -1; 1244 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1245 switch (bits(va,5,4)) { 1246 case 0: 1247 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1248 break; 1249 case 1: 1250 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 1251 break; 1252 case 3: 1253 ctx_id = 0; 1254 break; 1255 default: 1256 ignore = true; 1257 } 1258 1259 switch (bits(va,7,6)) { 1260 case 0: // demap page 1261 if (!ignore) 1262 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1263 break; 1264 case 1: // demap context 1265 if (!ignore) 1266 demapContext(part_id, ctx_id); 1267 break; 1268 case 2: 1269 demapAll(part_id); 1270 break; 1271 default: 1272 panic("Invalid type for IMMU demap\n"); 1273 } 1274 break; 1275 case ASI_SWVR_INTR_RECEIVE: 1276 { 1277 int msb; 1278 // clear all the interrupts that aren't set in the write 1279 SparcISA::Interrupts * interrupts = 1280 dynamic_cast<SparcISA::Interrupts *>( 1281 tc->getCpuPtr()->getInterruptController(0)); 1282 while (interrupts->get_vec(IT_INT_VEC) & data) { 1283 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 1284 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb); 1285 } 1286 } 1287 break; 1288 case ASI_SWVR_UDB_INTR_W: 1289 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 1290 postInterrupt(0, bits(data, 5, 0), 0); 1291 break; 1292 default: 1293doMmuWriteError: 1294 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 1295 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data); 1296 } 1297 pkt->makeAtomicResponse(); 1298 return Cycles(1); 1299} 1300 1301void 1302TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1303{ 1304 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 1305 TLB * itb = tc->getITBPtr(); 1306 ptrs[0] = MakeTsbPtr(Ps0, tag_access, 1307 c0_tsb_ps0, 1308 c0_config, 1309 cx_tsb_ps0, 1310 cx_config); 1311 ptrs[1] = MakeTsbPtr(Ps1, tag_access, 1312 c0_tsb_ps1, 1313 c0_config, 1314 cx_tsb_ps1, 1315 cx_config); 1316 ptrs[2] = MakeTsbPtr(Ps0, tag_access, 1317 itb->c0_tsb_ps0, 1318 itb->c0_config, 1319 itb->cx_tsb_ps0, 1320 itb->cx_config); 1321 ptrs[3] = MakeTsbPtr(Ps1, tag_access, 1322 itb->c0_tsb_ps1, 1323 itb->c0_config, 1324 itb->cx_tsb_ps1, 1325 itb->cx_config); 1326} 1327 1328uint64_t 1329TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1330 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 1331{ 1332 uint64_t tsb; 1333 uint64_t config; 1334 1335 if (bits(tag_access, 12,0) == 0) { 1336 tsb = c0_tsb; 1337 config = c0_config; 1338 } else { 1339 tsb = cX_tsb; 1340 config = cX_config; 1341 } 1342 1343 uint64_t ptr = mbits(tsb,63,13); 1344 bool split = bits(tsb,12,12); 1345 int tsb_size = bits(tsb,3,0); 1346 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 1347 1348 if (ps == Ps1 && split) 1349 ptr |= ULL(1) << (13 + tsb_size); 1350 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 1351 1352 return ptr; 1353} 1354 1355void 1356TLB::serialize(CheckpointOut &cp) const 1357{ 1358 SERIALIZE_SCALAR(size); 1359 SERIALIZE_SCALAR(usedEntries); 1360 SERIALIZE_SCALAR(lastReplaced); 1361 1362 // convert the pointer based free list into an index based one 1363 std::vector<int> free_list; 1364 for (const TlbEntry *entry : freeList) 1365 free_list.push_back(entry - tlb); 1366 1367 SERIALIZE_CONTAINER(free_list); 1368 1369 SERIALIZE_SCALAR(c0_tsb_ps0); 1370 SERIALIZE_SCALAR(c0_tsb_ps1); 1371 SERIALIZE_SCALAR(c0_config); 1372 SERIALIZE_SCALAR(cx_tsb_ps0); 1373 SERIALIZE_SCALAR(cx_tsb_ps1); 1374 SERIALIZE_SCALAR(cx_config); 1375 SERIALIZE_SCALAR(sfsr); 1376 SERIALIZE_SCALAR(tag_access); 1377 1378 for (int x = 0; x < size; x++) { 1379 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 1380 tlb[x].serialize(cp); 1381 } 1382 SERIALIZE_SCALAR(sfar); 1383} 1384 1385void 1386TLB::unserialize(CheckpointIn &cp) 1387{ 1388 int oldSize; 1389 1390 paramIn(cp, "size", oldSize); 1391 if (oldSize != size) 1392 panic("Don't support unserializing different sized TLBs\n"); 1393 UNSERIALIZE_SCALAR(usedEntries); 1394 UNSERIALIZE_SCALAR(lastReplaced); 1395 1396 std::vector<int> free_list; 1397 UNSERIALIZE_CONTAINER(free_list); 1398 freeList.clear(); 1399 for (int idx : free_list) 1400 freeList.push_back(&tlb[idx]); 1401 1402 UNSERIALIZE_SCALAR(c0_tsb_ps0); 1403 UNSERIALIZE_SCALAR(c0_tsb_ps1); 1404 UNSERIALIZE_SCALAR(c0_config); 1405 UNSERIALIZE_SCALAR(cx_tsb_ps0); 1406 UNSERIALIZE_SCALAR(cx_tsb_ps1); 1407 UNSERIALIZE_SCALAR(cx_config); 1408 UNSERIALIZE_SCALAR(sfsr); 1409 UNSERIALIZE_SCALAR(tag_access); 1410 1411 lookupTable.clear(); 1412 for (int x = 0; x < size; x++) { 1413 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 1414 tlb[x].unserialize(cp); 1415 if (tlb[x].valid) 1416 lookupTable.insert(tlb[x].range, &tlb[x]); 1417 1418 } 1419 UNSERIALIZE_SCALAR(sfar); 1420} 1421 1422} // namespace SparcISA 1423 1424SparcISA::TLB * 1425SparcTLBParams::create() 1426{ 1427 return new SparcISA::TLB(this); 1428} 1429