tlb.cc revision 7518
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 346335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 424103Ssaidi@eecs.umich.edu#include "sim/system.hh" 433569Sgblack@eecs.umich.edu 443804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 453804Ssaidi@eecs.umich.edu * */ 464088Sbinkertn@umich.edunamespace SparcISA { 473569Sgblack@eecs.umich.edu 485034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 495358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 503881Ssaidi@eecs.umich.edu cacheValid(false) 513804Ssaidi@eecs.umich.edu{ 523804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 533804Ssaidi@eecs.umich.edu if (size > 64) 545555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 553569Sgblack@eecs.umich.edu 563804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 573918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 583881Ssaidi@eecs.umich.edu 593881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 603881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 614990Sgblack@eecs.umich.edu 624990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 634990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 644990Sgblack@eecs.umich.edu c0_config = 0; 654990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 664990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 674990Sgblack@eecs.umich.edu cx_config = 0; 684990Sgblack@eecs.umich.edu sfsr = 0; 694990Sgblack@eecs.umich.edu tag_access = 0; 706022Sgblack@eecs.umich.edu sfar = 0; 716022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 726022Sgblack@eecs.umich.edu cacheEntry[1] = NULL; 733804Ssaidi@eecs.umich.edu} 743569Sgblack@eecs.umich.edu 753804Ssaidi@eecs.umich.eduvoid 763804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 773804Ssaidi@eecs.umich.edu{ 783804Ssaidi@eecs.umich.edu MapIter i; 793881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 803804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 813804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 823804Ssaidi@eecs.umich.edu t->used = false; 833804Ssaidi@eecs.umich.edu usedEntries--; 843804Ssaidi@eecs.umich.edu } 853804Ssaidi@eecs.umich.edu } 863804Ssaidi@eecs.umich.edu} 873569Sgblack@eecs.umich.edu 883569Sgblack@eecs.umich.edu 893804Ssaidi@eecs.umich.eduvoid 903804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 913826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 923804Ssaidi@eecs.umich.edu{ 933804Ssaidi@eecs.umich.edu MapIter i; 943826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 953907Ssaidi@eecs.umich.edu// TlbRange tr; 963826Ssaidi@eecs.umich.edu int x; 973811Ssaidi@eecs.umich.edu 983836Ssaidi@eecs.umich.edu cacheValid = false; 993915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1003907Ssaidi@eecs.umich.edu /* tr.va = va; 1013881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1023881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1033881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1043881Ssaidi@eecs.umich.edu tr.real = real; 1053907Ssaidi@eecs.umich.edu*/ 1063881Ssaidi@eecs.umich.edu 1075555Snate@binkert.org DPRINTF(TLB, 1085555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1095555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1103881Ssaidi@eecs.umich.edu 1113881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1123907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1133907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1143907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1153907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1163907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1173907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1183907Ssaidi@eecs.umich.edu { 1193907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1203907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1213907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1223907Ssaidi@eecs.umich.edu 1233907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1243907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1253907Ssaidi@eecs.umich.edu tlb[x].used = false; 1263907Ssaidi@eecs.umich.edu usedEntries--; 1273907Ssaidi@eecs.umich.edu } 1283907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1293907Ssaidi@eecs.umich.edu } 1303907Ssaidi@eecs.umich.edu } 1313907Ssaidi@eecs.umich.edu } 1323907Ssaidi@eecs.umich.edu 1333907Ssaidi@eecs.umich.edu/* 1343881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1353881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1363881Ssaidi@eecs.umich.edu i->second->valid = false; 1373881Ssaidi@eecs.umich.edu if (i->second->used) { 1383881Ssaidi@eecs.umich.edu i->second->used = false; 1393881Ssaidi@eecs.umich.edu usedEntries--; 1403881Ssaidi@eecs.umich.edu } 1413881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1423881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1433881Ssaidi@eecs.umich.edu i->second); 1443881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1453881Ssaidi@eecs.umich.edu } 1463907Ssaidi@eecs.umich.edu*/ 1473811Ssaidi@eecs.umich.edu 1483826Ssaidi@eecs.umich.edu if (entry != -1) { 1493826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1503826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1513826Ssaidi@eecs.umich.edu } else { 1523881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1533881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1543881Ssaidi@eecs.umich.edu } else { 1553881Ssaidi@eecs.umich.edu x = lastReplaced; 1563881Ssaidi@eecs.umich.edu do { 1573881Ssaidi@eecs.umich.edu ++x; 1583881Ssaidi@eecs.umich.edu if (x == size) 1593881Ssaidi@eecs.umich.edu x = 0; 1603881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1613881Ssaidi@eecs.umich.edu goto insertAllLocked; 1623881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1633881Ssaidi@eecs.umich.edu lastReplaced = x; 1643881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1653881Ssaidi@eecs.umich.edu } 1663881Ssaidi@eecs.umich.edu /* 1673826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1683826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1693826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1703826Ssaidi@eecs.umich.edu break; 1713826Ssaidi@eecs.umich.edu } 1723881Ssaidi@eecs.umich.edu }*/ 1733569Sgblack@eecs.umich.edu } 1743569Sgblack@eecs.umich.edu 1753881Ssaidi@eecs.umich.eduinsertAllLocked: 1763804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1773881Ssaidi@eecs.umich.edu if (!new_entry) { 1783826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1793881Ssaidi@eecs.umich.edu } 1803881Ssaidi@eecs.umich.edu 1813881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1823907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1833907Ssaidi@eecs.umich.edu usedEntries--; 1843929Ssaidi@eecs.umich.edu if (new_entry->valid) 1853929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1863907Ssaidi@eecs.umich.edu 1873907Ssaidi@eecs.umich.edu 1883804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1893804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1903881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1913804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1923804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1933804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1943804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1953804Ssaidi@eecs.umich.edu new_entry->used = true;; 1963804Ssaidi@eecs.umich.edu new_entry->valid = true; 1973804Ssaidi@eecs.umich.edu usedEntries++; 1983569Sgblack@eecs.umich.edu 1993863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 2003863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 2013804Ssaidi@eecs.umich.edu 2025555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 2035555Snate@binkert.org // but the one we just inserted 2043804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2053804Ssaidi@eecs.umich.edu clearUsedBits(); 2063804Ssaidi@eecs.umich.edu new_entry->used = true; 2073804Ssaidi@eecs.umich.edu usedEntries++; 2083804Ssaidi@eecs.umich.edu } 2093569Sgblack@eecs.umich.edu} 2103804Ssaidi@eecs.umich.edu 2113804Ssaidi@eecs.umich.edu 2123804Ssaidi@eecs.umich.eduTlbEntry* 2135555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 2145555Snate@binkert.org bool update_used) 2153804Ssaidi@eecs.umich.edu{ 2163804Ssaidi@eecs.umich.edu MapIter i; 2173804Ssaidi@eecs.umich.edu TlbRange tr; 2183804Ssaidi@eecs.umich.edu TlbEntry *t; 2193804Ssaidi@eecs.umich.edu 2203811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2213811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2223804Ssaidi@eecs.umich.edu // Assemble full address structure 2233804Ssaidi@eecs.umich.edu tr.va = va; 2245312Sgblack@eecs.umich.edu tr.size = 1; 2253804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2263804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2273804Ssaidi@eecs.umich.edu tr.real = real; 2283804Ssaidi@eecs.umich.edu 2293804Ssaidi@eecs.umich.edu // Try to find the entry 2303804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2313804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2323811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2333804Ssaidi@eecs.umich.edu return NULL; 2343804Ssaidi@eecs.umich.edu } 2353804Ssaidi@eecs.umich.edu 2363804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2373804Ssaidi@eecs.umich.edu t = i->second; 2383826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2393826Ssaidi@eecs.umich.edu t->pte.size()); 2404070Ssaidi@eecs.umich.edu 2415555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2425555Snate@binkert.org // one from virttophys() 2434070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2443804Ssaidi@eecs.umich.edu t->used = true; 2453804Ssaidi@eecs.umich.edu usedEntries++; 2463804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2473804Ssaidi@eecs.umich.edu clearUsedBits(); 2483804Ssaidi@eecs.umich.edu t->used = true; 2493804Ssaidi@eecs.umich.edu usedEntries++; 2503804Ssaidi@eecs.umich.edu } 2513804Ssaidi@eecs.umich.edu } 2523804Ssaidi@eecs.umich.edu 2533804Ssaidi@eecs.umich.edu return t; 2543804Ssaidi@eecs.umich.edu} 2553804Ssaidi@eecs.umich.edu 2563826Ssaidi@eecs.umich.eduvoid 2573826Ssaidi@eecs.umich.eduTLB::dumpAll() 2583826Ssaidi@eecs.umich.edu{ 2593863Ssaidi@eecs.umich.edu MapIter i; 2603826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2613826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2623826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2633826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2643826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2653826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2663826Ssaidi@eecs.umich.edu } 2673826Ssaidi@eecs.umich.edu } 2683826Ssaidi@eecs.umich.edu} 2693804Ssaidi@eecs.umich.edu 2703804Ssaidi@eecs.umich.eduvoid 2713804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2723804Ssaidi@eecs.umich.edu{ 2733804Ssaidi@eecs.umich.edu TlbRange tr; 2743804Ssaidi@eecs.umich.edu MapIter i; 2753804Ssaidi@eecs.umich.edu 2763863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2773863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2783863Ssaidi@eecs.umich.edu 2793836Ssaidi@eecs.umich.edu cacheValid = false; 2803836Ssaidi@eecs.umich.edu 2813804Ssaidi@eecs.umich.edu // Assemble full address structure 2823804Ssaidi@eecs.umich.edu tr.va = va; 2835312Sgblack@eecs.umich.edu tr.size = 1; 2843804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2853804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2863804Ssaidi@eecs.umich.edu tr.real = real; 2873804Ssaidi@eecs.umich.edu 2883804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2893804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2903804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2913863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2923804Ssaidi@eecs.umich.edu i->second->valid = false; 2933804Ssaidi@eecs.umich.edu if (i->second->used) { 2943804Ssaidi@eecs.umich.edu i->second->used = false; 2953804Ssaidi@eecs.umich.edu usedEntries--; 2963804Ssaidi@eecs.umich.edu } 2973881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2983804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2993804Ssaidi@eecs.umich.edu } 3003804Ssaidi@eecs.umich.edu} 3013804Ssaidi@eecs.umich.edu 3023804Ssaidi@eecs.umich.eduvoid 3033804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 3043804Ssaidi@eecs.umich.edu{ 3053863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3063863Ssaidi@eecs.umich.edu partition_id, context_id); 3073836Ssaidi@eecs.umich.edu cacheValid = false; 3085555Snate@binkert.org for (int x = 0; x < size; x++) { 3093804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3103804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3113881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3123881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3133881Ssaidi@eecs.umich.edu } 3143804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3153804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3163804Ssaidi@eecs.umich.edu tlb[x].used = false; 3173804Ssaidi@eecs.umich.edu usedEntries--; 3183804Ssaidi@eecs.umich.edu } 3193804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3203804Ssaidi@eecs.umich.edu } 3213804Ssaidi@eecs.umich.edu } 3223804Ssaidi@eecs.umich.edu} 3233804Ssaidi@eecs.umich.edu 3243804Ssaidi@eecs.umich.eduvoid 3253804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3263804Ssaidi@eecs.umich.edu{ 3273863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3283836Ssaidi@eecs.umich.edu cacheValid = false; 3295555Snate@binkert.org for (int x = 0; x < size; x++) { 3305288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3315288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3325288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3333804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3343804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3353804Ssaidi@eecs.umich.edu tlb[x].used = false; 3363804Ssaidi@eecs.umich.edu usedEntries--; 3373804Ssaidi@eecs.umich.edu } 3383804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3393804Ssaidi@eecs.umich.edu } 3403804Ssaidi@eecs.umich.edu } 3413804Ssaidi@eecs.umich.edu} 3423804Ssaidi@eecs.umich.edu 3433804Ssaidi@eecs.umich.eduvoid 3443804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3453804Ssaidi@eecs.umich.edu{ 3463836Ssaidi@eecs.umich.edu cacheValid = false; 3475555Snate@binkert.org lookupTable.clear(); 3483836Ssaidi@eecs.umich.edu 3495555Snate@binkert.org for (int x = 0; x < size; x++) { 3503881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3513881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3523804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3533907Ssaidi@eecs.umich.edu tlb[x].used = false; 3543804Ssaidi@eecs.umich.edu } 3553804Ssaidi@eecs.umich.edu usedEntries = 0; 3563804Ssaidi@eecs.umich.edu} 3573804Ssaidi@eecs.umich.edu 3583804Ssaidi@eecs.umich.eduuint64_t 3595555Snate@binkert.orgTLB::TteRead(int entry) 3605555Snate@binkert.org{ 3613881Ssaidi@eecs.umich.edu if (entry >= size) 3623881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3633881Ssaidi@eecs.umich.edu 3643804Ssaidi@eecs.umich.edu assert(entry < size); 3653881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3663881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3673881Ssaidi@eecs.umich.edu else 3683881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3693804Ssaidi@eecs.umich.edu} 3703804Ssaidi@eecs.umich.edu 3713804Ssaidi@eecs.umich.eduuint64_t 3725555Snate@binkert.orgTLB::TagRead(int entry) 3735555Snate@binkert.org{ 3743804Ssaidi@eecs.umich.edu assert(entry < size); 3753804Ssaidi@eecs.umich.edu uint64_t tag; 3763881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3773881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3783804Ssaidi@eecs.umich.edu 3793881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3803881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3813881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3823804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3833804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3843804Ssaidi@eecs.umich.edu return tag; 3853804Ssaidi@eecs.umich.edu} 3863804Ssaidi@eecs.umich.edu 3873804Ssaidi@eecs.umich.edubool 3883804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3893804Ssaidi@eecs.umich.edu{ 3903804Ssaidi@eecs.umich.edu if (am) 3913804Ssaidi@eecs.umich.edu return true; 3923804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3933804Ssaidi@eecs.umich.edu return false; 3943804Ssaidi@eecs.umich.edu return true; 3953804Ssaidi@eecs.umich.edu} 3963804Ssaidi@eecs.umich.edu 3973804Ssaidi@eecs.umich.eduvoid 3984990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3993804Ssaidi@eecs.umich.edu{ 4003804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4013804Ssaidi@eecs.umich.edu sfsr = 0x3; 4023804Ssaidi@eecs.umich.edu else 4033804Ssaidi@eecs.umich.edu sfsr = 1; 4043804Ssaidi@eecs.umich.edu 4053804Ssaidi@eecs.umich.edu if (write) 4063804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4073804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4083804Ssaidi@eecs.umich.edu if (se) 4093804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4103804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4113804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4123804Ssaidi@eecs.umich.edu} 4133804Ssaidi@eecs.umich.edu 4143826Ssaidi@eecs.umich.eduvoid 4154990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 4163826Ssaidi@eecs.umich.edu{ 4173916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4183916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4193916Ssaidi@eecs.umich.edu 4204990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4213826Ssaidi@eecs.umich.edu} 4223804Ssaidi@eecs.umich.edu 4233804Ssaidi@eecs.umich.eduvoid 4246022Sgblack@eecs.umich.eduTLB::writeSfsr(Addr a, bool write, ContextType ct, 4253804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4263804Ssaidi@eecs.umich.edu{ 4276022Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4283811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4294990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4304990Sgblack@eecs.umich.edu sfar = a; 4313804Ssaidi@eecs.umich.edu} 4323804Ssaidi@eecs.umich.edu 4333804Ssaidi@eecs.umich.eduFault 4346022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 4353804Ssaidi@eecs.umich.edu{ 4364172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4373833Ssaidi@eecs.umich.edu 4383836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4393836Ssaidi@eecs.umich.edu TlbEntry *e; 4403836Ssaidi@eecs.umich.edu 4413836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4423836Ssaidi@eecs.umich.edu 4433836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4443836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4453836Ssaidi@eecs.umich.edu 4463836Ssaidi@eecs.umich.edu // Be fast if we can! 4473836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4486022Sgblack@eecs.umich.edu if (cacheEntry[0]) { 4496022Sgblack@eecs.umich.edu if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 4506022Sgblack@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4516022Sgblack@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 4525555Snate@binkert.org return NoFault; 4533836Ssaidi@eecs.umich.edu } 4543836Ssaidi@eecs.umich.edu } else { 4553836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4563836Ssaidi@eecs.umich.edu return NoFault; 4573836Ssaidi@eecs.umich.edu } 4583836Ssaidi@eecs.umich.edu } 4593836Ssaidi@eecs.umich.edu 4603833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4613833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4623833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4633833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4643833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4653833Ssaidi@eecs.umich.edu 4663833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4673833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4683833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4693804Ssaidi@eecs.umich.edu int context; 4703804Ssaidi@eecs.umich.edu ContextType ct; 4713804Ssaidi@eecs.umich.edu int asi; 4723804Ssaidi@eecs.umich.edu bool real = false; 4733804Ssaidi@eecs.umich.edu 4743833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4753833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4763811Ssaidi@eecs.umich.edu 4773804Ssaidi@eecs.umich.edu if (tl > 0) { 4783804Ssaidi@eecs.umich.edu asi = ASI_N; 4793804Ssaidi@eecs.umich.edu ct = Nucleus; 4803804Ssaidi@eecs.umich.edu context = 0; 4813804Ssaidi@eecs.umich.edu } else { 4823804Ssaidi@eecs.umich.edu asi = ASI_P; 4833804Ssaidi@eecs.umich.edu ct = Primary; 4843833Ssaidi@eecs.umich.edu context = pri_context; 4853804Ssaidi@eecs.umich.edu } 4863804Ssaidi@eecs.umich.edu 4873833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4883836Ssaidi@eecs.umich.edu cacheValid = true; 4893836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4906022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 4913836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4923804Ssaidi@eecs.umich.edu return NoFault; 4933804Ssaidi@eecs.umich.edu } 4943804Ssaidi@eecs.umich.edu 4953836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4963836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4974990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 4983804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4993804Ssaidi@eecs.umich.edu } 5003804Ssaidi@eecs.umich.edu 5013804Ssaidi@eecs.umich.edu if (addr_mask) 5023804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5033804Ssaidi@eecs.umich.edu 5043804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5054990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 5063804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5073804Ssaidi@eecs.umich.edu } 5083804Ssaidi@eecs.umich.edu 5093833Ssaidi@eecs.umich.edu if (!lsu_im) { 5103836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5113804Ssaidi@eecs.umich.edu real = true; 5123804Ssaidi@eecs.umich.edu context = 0; 5133804Ssaidi@eecs.umich.edu } else { 5143804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5153804Ssaidi@eecs.umich.edu } 5163804Ssaidi@eecs.umich.edu 5173804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5184990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5193804Ssaidi@eecs.umich.edu if (real) 5203804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5213804Ssaidi@eecs.umich.edu else 5224997Sgblack@eecs.umich.edu#if FULL_SYSTEM 5233804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5244997Sgblack@eecs.umich.edu#else 5254997Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss(req->getVaddr()); 5264997Sgblack@eecs.umich.edu#endif 5273804Ssaidi@eecs.umich.edu } 5283804Ssaidi@eecs.umich.edu 5293804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5303804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5314990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5324990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5333804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5343804Ssaidi@eecs.umich.edu } 5353804Ssaidi@eecs.umich.edu 5363836Ssaidi@eecs.umich.edu // cache translation date for next translation 5373836Ssaidi@eecs.umich.edu cacheValid = true; 5383836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5396022Sgblack@eecs.umich.edu cacheEntry[0] = e; 5403836Ssaidi@eecs.umich.edu 5415555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5423836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5433804Ssaidi@eecs.umich.edu return NoFault; 5443804Ssaidi@eecs.umich.edu} 5453804Ssaidi@eecs.umich.edu 5463804Ssaidi@eecs.umich.eduFault 5476022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 5483804Ssaidi@eecs.umich.edu{ 5495555Snate@binkert.org /* 5505555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5515555Snate@binkert.org * it faster! 5525555Snate@binkert.org */ 5534172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5543836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5553836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5563836Ssaidi@eecs.umich.edu ASI asi; 5573836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5583836Ssaidi@eecs.umich.edu bool implicit = false; 5593836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5605570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5613833Ssaidi@eecs.umich.edu 5623836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5633836Ssaidi@eecs.umich.edu vaddr, size, asi); 5643836Ssaidi@eecs.umich.edu 5653929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5663929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5673929Ssaidi@eecs.umich.edu freeList.size()); 5683836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5693836Ssaidi@eecs.umich.edu implicit = true; 5703836Ssaidi@eecs.umich.edu 5714996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5724996Sgblack@eecs.umich.edu // trap later 5734996Sgblack@eecs.umich.edu if (!unaligned) { 5744996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5754996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5764996Sgblack@eecs.umich.edu return NoFault; 5774996Sgblack@eecs.umich.edu } 5784996Sgblack@eecs.umich.edu 5794996Sgblack@eecs.umich.edu // Be fast if we can! 5804996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5814996Sgblack@eecs.umich.edu 5824996Sgblack@eecs.umich.edu 5834996Sgblack@eecs.umich.edu 5844996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5854996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5864996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5874996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5884996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5894996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5905555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5915555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5925736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 5935555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5945555Snate@binkert.org return NoFault; 5954996Sgblack@eecs.umich.edu } // if matched 5964996Sgblack@eecs.umich.edu } // if cache entry valid 5974996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 5984996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 5994996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6004996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 6014996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6024996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6035555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 6045555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6055736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 6065555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6075555Snate@binkert.org return NoFault; 6084996Sgblack@eecs.umich.edu } // if matched 6094996Sgblack@eecs.umich.edu } // if cache entry valid 6104996Sgblack@eecs.umich.edu } 6113836Ssaidi@eecs.umich.edu } 6123836Ssaidi@eecs.umich.edu 6133833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6143833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6153833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6163833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6173833Ssaidi@eecs.umich.edu 6183833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6193833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6203833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6213916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6223833Ssaidi@eecs.umich.edu 6233804Ssaidi@eecs.umich.edu bool real = false; 6243832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6253832Ssaidi@eecs.umich.edu int context = 0; 6263804Ssaidi@eecs.umich.edu 6273804Ssaidi@eecs.umich.edu TlbEntry *e; 6283804Ssaidi@eecs.umich.edu 6293833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6305555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6313804Ssaidi@eecs.umich.edu 6323804Ssaidi@eecs.umich.edu if (implicit) { 6333804Ssaidi@eecs.umich.edu if (tl > 0) { 6343804Ssaidi@eecs.umich.edu asi = ASI_N; 6353804Ssaidi@eecs.umich.edu ct = Nucleus; 6363804Ssaidi@eecs.umich.edu context = 0; 6373804Ssaidi@eecs.umich.edu } else { 6383804Ssaidi@eecs.umich.edu asi = ASI_P; 6393804Ssaidi@eecs.umich.edu ct = Primary; 6403833Ssaidi@eecs.umich.edu context = pri_context; 6413804Ssaidi@eecs.umich.edu } 6423910Ssaidi@eecs.umich.edu } else { 6433804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6443910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6453804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6464990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6473804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6483804Ssaidi@eecs.umich.edu } 6493910Ssaidi@eecs.umich.edu 6503910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6514990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6523804Ssaidi@eecs.umich.edu return new DataAccessException; 6533804Ssaidi@eecs.umich.edu } 6543804Ssaidi@eecs.umich.edu 6553910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6563910Ssaidi@eecs.umich.edu context = pri_context; 6573910Ssaidi@eecs.umich.edu ct = Primary; 6583910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6593910Ssaidi@eecs.umich.edu context = sec_context; 6603910Ssaidi@eecs.umich.edu ct = Secondary; 6613910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6623910Ssaidi@eecs.umich.edu ct = Nucleus; 6633910Ssaidi@eecs.umich.edu context = 0; 6643910Ssaidi@eecs.umich.edu } else { // ???? 6653910Ssaidi@eecs.umich.edu ct = Primary; 6663910Ssaidi@eecs.umich.edu context = pri_context; 6673910Ssaidi@eecs.umich.edu } 6683902Ssaidi@eecs.umich.edu } 6693804Ssaidi@eecs.umich.edu 6703926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6713804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6723804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6734989Sgblack@eecs.umich.edu 6744989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6754989Sgblack@eecs.umich.edu //load differs from a regular one, other than what happens concerning 6764989Sgblack@eecs.umich.edu //nfo and e bits in the TTE 6774989Sgblack@eecs.umich.edu// if (AsiIsNoFault(asi)) 6784989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6793856Ssaidi@eecs.umich.edu 6803804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6813804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6824103Ssaidi@eecs.umich.edu 6834191Ssaidi@eecs.umich.edu if (AsiIsCmt(asi)) 6844191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6854191Ssaidi@eecs.umich.edu 6863824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6874103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6883804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6893804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6903804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6913804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6923824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6933824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6943825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 6953825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6963823Ssaidi@eecs.umich.edu 6973926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 6984989Sgblack@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 6993823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 7003804Ssaidi@eecs.umich.edu } 7013804Ssaidi@eecs.umich.edu 7023826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 7034996Sgblack@eecs.umich.edu if (unaligned) { 7044990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 7053826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7063826Ssaidi@eecs.umich.edu } 7073826Ssaidi@eecs.umich.edu 7083826Ssaidi@eecs.umich.edu if (addr_mask) 7093826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7103826Ssaidi@eecs.umich.edu 7113826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7124990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 7133826Ssaidi@eecs.umich.edu return new DataAccessException; 7143826Ssaidi@eecs.umich.edu } 7153826Ssaidi@eecs.umich.edu 7163910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7173804Ssaidi@eecs.umich.edu real = true; 7183804Ssaidi@eecs.umich.edu context = 0; 7195555Snate@binkert.org } 7203804Ssaidi@eecs.umich.edu 7213804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7223836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7233804Ssaidi@eecs.umich.edu return NoFault; 7243804Ssaidi@eecs.umich.edu } 7253804Ssaidi@eecs.umich.edu 7263836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7273804Ssaidi@eecs.umich.edu 7283804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7294990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7303811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7313804Ssaidi@eecs.umich.edu if (real) 7323804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7333804Ssaidi@eecs.umich.edu else 7344997Sgblack@eecs.umich.edu#if FULL_SYSTEM 7353804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7364997Sgblack@eecs.umich.edu#else 7374997Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss(req->getVaddr()); 7384997Sgblack@eecs.umich.edu#endif 7393804Ssaidi@eecs.umich.edu 7403804Ssaidi@eecs.umich.edu } 7413804Ssaidi@eecs.umich.edu 7423928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7434990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7444990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7453928Ssaidi@eecs.umich.edu return new DataAccessException; 7463928Ssaidi@eecs.umich.edu } 7473804Ssaidi@eecs.umich.edu 7483804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7494990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7504990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7513804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7523804Ssaidi@eecs.umich.edu } 7533804Ssaidi@eecs.umich.edu 7543804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7554990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7564990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7573804Ssaidi@eecs.umich.edu return new DataAccessException; 7583804Ssaidi@eecs.umich.edu } 7593804Ssaidi@eecs.umich.edu 7603928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7614990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7624990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7633928Ssaidi@eecs.umich.edu return new DataAccessException; 7643928Ssaidi@eecs.umich.edu } 7653928Ssaidi@eecs.umich.edu 7664090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7675736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 7683804Ssaidi@eecs.umich.edu 7693836Ssaidi@eecs.umich.edu // cache translation date for next translation 7703836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7713881Ssaidi@eecs.umich.edu if (!cacheValid) { 7723881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7733881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7743881Ssaidi@eecs.umich.edu } 7753881Ssaidi@eecs.umich.edu 7763836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7773836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7783836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7793836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7803836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7813836Ssaidi@eecs.umich.edu if (implicit) 7823836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7833836Ssaidi@eecs.umich.edu } 7843881Ssaidi@eecs.umich.edu cacheValid = true; 7855555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7863836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7873804Ssaidi@eecs.umich.edu return NoFault; 7884103Ssaidi@eecs.umich.edu 7893806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7904103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7914103Ssaidi@eecs.umich.edu if (!hpriv) { 7924990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7934103Ssaidi@eecs.umich.edu if (priv) 7944103Ssaidi@eecs.umich.edu return new DataAccessException; 7954103Ssaidi@eecs.umich.edu else 7964103Ssaidi@eecs.umich.edu return new PrivilegedAction; 7974103Ssaidi@eecs.umich.edu } 7984103Ssaidi@eecs.umich.edu 7995570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 8005570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 8014990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8024103Ssaidi@eecs.umich.edu return new DataAccessException; 8034103Ssaidi@eecs.umich.edu } 8044103Ssaidi@eecs.umich.edu 8054103Ssaidi@eecs.umich.edu goto regAccessOk; 8064103Ssaidi@eecs.umich.edu 8073804Ssaidi@eecs.umich.edu 8083806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8093806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8104990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8113806Ssaidi@eecs.umich.edu return new DataAccessException; 8123806Ssaidi@eecs.umich.edu } 8133824Ssaidi@eecs.umich.edu goto regAccessOk; 8143824Ssaidi@eecs.umich.edu 8153824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8163824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8174990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8183824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8193824Ssaidi@eecs.umich.edu } 8205570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8214990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8223824Ssaidi@eecs.umich.edu return new DataAccessException; 8233824Ssaidi@eecs.umich.edu } 8243824Ssaidi@eecs.umich.edu goto regAccessOk; 8253824Ssaidi@eecs.umich.edu 8263825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8273825Ssaidi@eecs.umich.edu if (!hpriv) { 8284990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8294070Ssaidi@eecs.umich.edu if (priv) 8303825Ssaidi@eecs.umich.edu return new DataAccessException; 8314070Ssaidi@eecs.umich.edu else 8323825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8333825Ssaidi@eecs.umich.edu } 8343825Ssaidi@eecs.umich.edu goto regAccessOk; 8353825Ssaidi@eecs.umich.edu 8363825Ssaidi@eecs.umich.edu 8373824Ssaidi@eecs.umich.eduregAccessOk: 8383804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8393811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8406428Ssteve.reinhardt@amd.com req->setFlags(Request::MMAPED_IPR); 8413806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8423806Ssaidi@eecs.umich.edu return NoFault; 8433804Ssaidi@eecs.umich.edu}; 8443804Ssaidi@eecs.umich.edu 8456022Sgblack@eecs.umich.eduFault 8466023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 8476022Sgblack@eecs.umich.edu{ 8486023Snate@binkert.org if (mode == Execute) 8496022Sgblack@eecs.umich.edu return translateInst(req, tc); 8506022Sgblack@eecs.umich.edu else 8516023Snate@binkert.org return translateData(req, tc, mode == Write); 8526022Sgblack@eecs.umich.edu} 8536022Sgblack@eecs.umich.edu 8545894Sgblack@eecs.umich.eduvoid 8556022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 8566023Snate@binkert.org Translation *translation, Mode mode) 8575894Sgblack@eecs.umich.edu{ 8585894Sgblack@eecs.umich.edu assert(translation); 8596023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 8605894Sgblack@eecs.umich.edu} 8615894Sgblack@eecs.umich.edu 8624997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8634997Sgblack@eecs.umich.edu 8643806Ssaidi@eecs.umich.eduTick 8656022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8663806Ssaidi@eecs.umich.edu{ 8673823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8683823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8694070Ssaidi@eecs.umich.edu uint64_t temp; 8703823Ssaidi@eecs.umich.edu 8713823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8723823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8733823Ssaidi@eecs.umich.edu 8746022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 8754990Sgblack@eecs.umich.edu 8763823Ssaidi@eecs.umich.edu switch (asi) { 8773823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8783823Ssaidi@eecs.umich.edu assert(va == 0); 8794172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8803823Ssaidi@eecs.umich.edu break; 8813823Ssaidi@eecs.umich.edu case ASI_MMU: 8823823Ssaidi@eecs.umich.edu switch (va) { 8833823Ssaidi@eecs.umich.edu case 0x8: 8844172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8853823Ssaidi@eecs.umich.edu break; 8863823Ssaidi@eecs.umich.edu case 0x10: 8874172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8883823Ssaidi@eecs.umich.edu break; 8893823Ssaidi@eecs.umich.edu default: 8903823Ssaidi@eecs.umich.edu goto doMmuReadError; 8913823Ssaidi@eecs.umich.edu } 8923823Ssaidi@eecs.umich.edu break; 8933824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8944172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8953824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8963824Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8983823Ssaidi@eecs.umich.edu assert(va == 0); 8994990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 9003823Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 9034990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9074990Sgblack@eecs.umich.edu pkt->set(c0_config); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 9114990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 9154990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 9194990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 9234990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 9274990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 9314990Sgblack@eecs.umich.edu pkt->set(cx_config); 9323823Ssaidi@eecs.umich.edu break; 9333823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9343823Ssaidi@eecs.umich.edu assert(va == 0); 9354990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9363823Ssaidi@eecs.umich.edu break; 9373823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9383823Ssaidi@eecs.umich.edu assert(va == 0); 9394990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9403823Ssaidi@eecs.umich.edu break; 9413823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9423823Ssaidi@eecs.umich.edu assert(va == 0); 9434990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9443823Ssaidi@eecs.umich.edu break; 9453826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9463912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9473826Ssaidi@eecs.umich.edu break; 9483823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9493823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9504172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9513823Ssaidi@eecs.umich.edu break; 9523826Ssaidi@eecs.umich.edu case ASI_IMMU: 9533826Ssaidi@eecs.umich.edu switch (va) { 9543833Ssaidi@eecs.umich.edu case 0x0: 9554990Sgblack@eecs.umich.edu temp = itb->tag_access; 9563833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9573833Ssaidi@eecs.umich.edu break; 9583906Ssaidi@eecs.umich.edu case 0x18: 9594990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9603906Ssaidi@eecs.umich.edu break; 9613826Ssaidi@eecs.umich.edu case 0x30: 9624990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9633826Ssaidi@eecs.umich.edu break; 9643826Ssaidi@eecs.umich.edu default: 9653826Ssaidi@eecs.umich.edu goto doMmuReadError; 9663826Ssaidi@eecs.umich.edu } 9673826Ssaidi@eecs.umich.edu break; 9683823Ssaidi@eecs.umich.edu case ASI_DMMU: 9693823Ssaidi@eecs.umich.edu switch (va) { 9703833Ssaidi@eecs.umich.edu case 0x0: 9714990Sgblack@eecs.umich.edu temp = tag_access; 9723833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9733833Ssaidi@eecs.umich.edu break; 9743906Ssaidi@eecs.umich.edu case 0x18: 9754990Sgblack@eecs.umich.edu pkt->set(sfsr); 9763906Ssaidi@eecs.umich.edu break; 9773906Ssaidi@eecs.umich.edu case 0x20: 9784990Sgblack@eecs.umich.edu pkt->set(sfar); 9793906Ssaidi@eecs.umich.edu break; 9803826Ssaidi@eecs.umich.edu case 0x30: 9814990Sgblack@eecs.umich.edu pkt->set(tag_access); 9823826Ssaidi@eecs.umich.edu break; 9833823Ssaidi@eecs.umich.edu case 0x80: 9844172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9853823Ssaidi@eecs.umich.edu break; 9863823Ssaidi@eecs.umich.edu default: 9873823Ssaidi@eecs.umich.edu goto doMmuReadError; 9883823Ssaidi@eecs.umich.edu } 9893823Ssaidi@eecs.umich.edu break; 9903833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9914070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9924990Sgblack@eecs.umich.edu tag_access, 9934990Sgblack@eecs.umich.edu c0_tsb_ps0, 9944990Sgblack@eecs.umich.edu c0_config, 9954990Sgblack@eecs.umich.edu cx_tsb_ps0, 9964990Sgblack@eecs.umich.edu cx_config)); 9973833Ssaidi@eecs.umich.edu break; 9983833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9994070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10004990Sgblack@eecs.umich.edu tag_access, 10014990Sgblack@eecs.umich.edu c0_tsb_ps1, 10024990Sgblack@eecs.umich.edu c0_config, 10034990Sgblack@eecs.umich.edu cx_tsb_ps1, 10044990Sgblack@eecs.umich.edu cx_config)); 10053833Ssaidi@eecs.umich.edu break; 10063899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 10074070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10084990Sgblack@eecs.umich.edu itb->tag_access, 10094990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10104990Sgblack@eecs.umich.edu itb->c0_config, 10114990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10124990Sgblack@eecs.umich.edu itb->cx_config)); 10133899Ssaidi@eecs.umich.edu break; 10143899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10154070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10164990Sgblack@eecs.umich.edu itb->tag_access, 10174990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10184990Sgblack@eecs.umich.edu itb->c0_config, 10194990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10204990Sgblack@eecs.umich.edu itb->cx_config)); 10213899Ssaidi@eecs.umich.edu break; 10224103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10235646Sgblack@eecs.umich.edu { 10245646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10255646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10265646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10275646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10285646Sgblack@eecs.umich.edu } 10294103Ssaidi@eecs.umich.edu break; 10304103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10315646Sgblack@eecs.umich.edu { 10325646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10335646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10345646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10355646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 10365704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); 10375646Sgblack@eecs.umich.edu pkt->set(temp); 10385646Sgblack@eecs.umich.edu } 10394103Ssaidi@eecs.umich.edu break; 10403823Ssaidi@eecs.umich.edu default: 10413823Ssaidi@eecs.umich.edudoMmuReadError: 10423823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10433823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10443823Ssaidi@eecs.umich.edu } 10454870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10465100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 10473806Ssaidi@eecs.umich.edu} 10483806Ssaidi@eecs.umich.edu 10493806Ssaidi@eecs.umich.eduTick 10506022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10513806Ssaidi@eecs.umich.edu{ 10527518Sgblack@eecs.umich.edu uint64_t data = pkt->get<uint64_t>(); 10533823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10543823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10553823Ssaidi@eecs.umich.edu 10563826Ssaidi@eecs.umich.edu Addr ta_insert; 10573826Ssaidi@eecs.umich.edu Addr va_insert; 10583826Ssaidi@eecs.umich.edu Addr ct_insert; 10593826Ssaidi@eecs.umich.edu int part_insert; 10603826Ssaidi@eecs.umich.edu int entry_insert = -1; 10613826Ssaidi@eecs.umich.edu bool real_insert; 10623863Ssaidi@eecs.umich.edu bool ignore; 10633863Ssaidi@eecs.umich.edu int part_id; 10643863Ssaidi@eecs.umich.edu int ctx_id; 10653826Ssaidi@eecs.umich.edu PageTableEntry pte; 10663826Ssaidi@eecs.umich.edu 10673825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10683823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10693823Ssaidi@eecs.umich.edu 10706022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 10714990Sgblack@eecs.umich.edu 10723823Ssaidi@eecs.umich.edu switch (asi) { 10733823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10743823Ssaidi@eecs.umich.edu assert(va == 0); 10754172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10763823Ssaidi@eecs.umich.edu break; 10773823Ssaidi@eecs.umich.edu case ASI_MMU: 10783823Ssaidi@eecs.umich.edu switch (va) { 10793823Ssaidi@eecs.umich.edu case 0x8: 10804172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10813823Ssaidi@eecs.umich.edu break; 10823823Ssaidi@eecs.umich.edu case 0x10: 10834172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10843823Ssaidi@eecs.umich.edu break; 10853823Ssaidi@eecs.umich.edu default: 10863823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10873823Ssaidi@eecs.umich.edu } 10883823Ssaidi@eecs.umich.edu break; 10893824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10903825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10914172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10923824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10933824Ssaidi@eecs.umich.edu break; 10943823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10953823Ssaidi@eecs.umich.edu assert(va == 0); 10964990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10973823Ssaidi@eecs.umich.edu break; 10983823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10993823Ssaidi@eecs.umich.edu assert(va == 0); 11004990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 11013823Ssaidi@eecs.umich.edu break; 11023823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 11033823Ssaidi@eecs.umich.edu assert(va == 0); 11044990Sgblack@eecs.umich.edu c0_config = data; 11053823Ssaidi@eecs.umich.edu break; 11063823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 11073823Ssaidi@eecs.umich.edu assert(va == 0); 11084990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 11093823Ssaidi@eecs.umich.edu break; 11103823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 11113823Ssaidi@eecs.umich.edu assert(va == 0); 11124990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11133823Ssaidi@eecs.umich.edu break; 11143823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11153823Ssaidi@eecs.umich.edu assert(va == 0); 11164990Sgblack@eecs.umich.edu itb->c0_config = data; 11173823Ssaidi@eecs.umich.edu break; 11183823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11193823Ssaidi@eecs.umich.edu assert(va == 0); 11204990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11213823Ssaidi@eecs.umich.edu break; 11223823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11233823Ssaidi@eecs.umich.edu assert(va == 0); 11244990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11253823Ssaidi@eecs.umich.edu break; 11263823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11273823Ssaidi@eecs.umich.edu assert(va == 0); 11284990Sgblack@eecs.umich.edu cx_config = data; 11293823Ssaidi@eecs.umich.edu break; 11303823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11313823Ssaidi@eecs.umich.edu assert(va == 0); 11324990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11333823Ssaidi@eecs.umich.edu break; 11343823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11353823Ssaidi@eecs.umich.edu assert(va == 0); 11364990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11373823Ssaidi@eecs.umich.edu break; 11383823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11393823Ssaidi@eecs.umich.edu assert(va == 0); 11404990Sgblack@eecs.umich.edu itb->cx_config = data; 11413823Ssaidi@eecs.umich.edu break; 11423825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11433825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11445823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11453825Ssaidi@eecs.umich.edu break; 11463823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11473823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11484172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11493823Ssaidi@eecs.umich.edu break; 11503826Ssaidi@eecs.umich.edu case ASI_IMMU: 11513826Ssaidi@eecs.umich.edu switch (va) { 11523906Ssaidi@eecs.umich.edu case 0x18: 11534990Sgblack@eecs.umich.edu itb->sfsr = data; 11543906Ssaidi@eecs.umich.edu break; 11553826Ssaidi@eecs.umich.edu case 0x30: 11563916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11574990Sgblack@eecs.umich.edu itb->tag_access = data; 11583826Ssaidi@eecs.umich.edu break; 11593826Ssaidi@eecs.umich.edu default: 11603826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11613826Ssaidi@eecs.umich.edu } 11623826Ssaidi@eecs.umich.edu break; 11633826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11643826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11653826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11663826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11674990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11683826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11693826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11704172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11713826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11723826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11733826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11743826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11753826Ssaidi@eecs.umich.edu pte, entry_insert); 11763826Ssaidi@eecs.umich.edu break; 11773826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11783826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11793826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11803826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11814990Sgblack@eecs.umich.edu ta_insert = tag_access; 11823826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11833826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11844172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11853826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11863826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11873826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11885555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11895555Snate@binkert.org entry_insert); 11903826Ssaidi@eecs.umich.edu break; 11913863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11923863Ssaidi@eecs.umich.edu ignore = false; 11933863Ssaidi@eecs.umich.edu ctx_id = -1; 11944172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11953863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11963863Ssaidi@eecs.umich.edu case 0: 11974172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11983863Ssaidi@eecs.umich.edu break; 11993863Ssaidi@eecs.umich.edu case 1: 12003863Ssaidi@eecs.umich.edu ignore = true; 12013863Ssaidi@eecs.umich.edu break; 12023863Ssaidi@eecs.umich.edu case 3: 12033863Ssaidi@eecs.umich.edu ctx_id = 0; 12043863Ssaidi@eecs.umich.edu break; 12053863Ssaidi@eecs.umich.edu default: 12063863Ssaidi@eecs.umich.edu ignore = true; 12073863Ssaidi@eecs.umich.edu } 12083863Ssaidi@eecs.umich.edu 12093863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12103863Ssaidi@eecs.umich.edu case 0: // demap page 12113863Ssaidi@eecs.umich.edu if (!ignore) 12123863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 12133863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 12143863Ssaidi@eecs.umich.edu break; 12153863Ssaidi@eecs.umich.edu case 1: //demap context 12163863Ssaidi@eecs.umich.edu if (!ignore) 12173863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 12183863Ssaidi@eecs.umich.edu break; 12193863Ssaidi@eecs.umich.edu case 2: 12203863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12213863Ssaidi@eecs.umich.edu break; 12223863Ssaidi@eecs.umich.edu default: 12233863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12243863Ssaidi@eecs.umich.edu } 12253863Ssaidi@eecs.umich.edu break; 12263823Ssaidi@eecs.umich.edu case ASI_DMMU: 12273823Ssaidi@eecs.umich.edu switch (va) { 12283906Ssaidi@eecs.umich.edu case 0x18: 12294990Sgblack@eecs.umich.edu sfsr = data; 12303906Ssaidi@eecs.umich.edu break; 12313826Ssaidi@eecs.umich.edu case 0x30: 12323916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12334990Sgblack@eecs.umich.edu tag_access = data; 12343826Ssaidi@eecs.umich.edu break; 12353823Ssaidi@eecs.umich.edu case 0x80: 12364172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12373823Ssaidi@eecs.umich.edu break; 12383823Ssaidi@eecs.umich.edu default: 12393823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12403823Ssaidi@eecs.umich.edu } 12413823Ssaidi@eecs.umich.edu break; 12423863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12433863Ssaidi@eecs.umich.edu ignore = false; 12443863Ssaidi@eecs.umich.edu ctx_id = -1; 12454172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12463863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12473863Ssaidi@eecs.umich.edu case 0: 12484172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12493863Ssaidi@eecs.umich.edu break; 12503863Ssaidi@eecs.umich.edu case 1: 12514172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12523863Ssaidi@eecs.umich.edu break; 12533863Ssaidi@eecs.umich.edu case 3: 12543863Ssaidi@eecs.umich.edu ctx_id = 0; 12553863Ssaidi@eecs.umich.edu break; 12563863Ssaidi@eecs.umich.edu default: 12573863Ssaidi@eecs.umich.edu ignore = true; 12583863Ssaidi@eecs.umich.edu } 12593863Ssaidi@eecs.umich.edu 12603863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12613863Ssaidi@eecs.umich.edu case 0: // demap page 12623863Ssaidi@eecs.umich.edu if (!ignore) 12633863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12643863Ssaidi@eecs.umich.edu break; 12653863Ssaidi@eecs.umich.edu case 1: //demap context 12663863Ssaidi@eecs.umich.edu if (!ignore) 12673863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12683863Ssaidi@eecs.umich.edu break; 12693863Ssaidi@eecs.umich.edu case 2: 12703863Ssaidi@eecs.umich.edu demapAll(part_id); 12713863Ssaidi@eecs.umich.edu break; 12723863Ssaidi@eecs.umich.edu default: 12733863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12743863Ssaidi@eecs.umich.edu } 12753863Ssaidi@eecs.umich.edu break; 12764103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12775646Sgblack@eecs.umich.edu { 12785646Sgblack@eecs.umich.edu int msb; 12795646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12805646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12815646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 12825646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 12835704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12845646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 12855704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); 12865646Sgblack@eecs.umich.edu } 12874103Ssaidi@eecs.umich.edu } 12884103Ssaidi@eecs.umich.edu break; 12894103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12904103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12915704Snate@binkert.org postInterrupt(bits(data, 5, 0), 0); 12924103Ssaidi@eecs.umich.edu break; 12935555Snate@binkert.org default: 12943823Ssaidi@eecs.umich.edudoMmuWriteError: 12953823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12963823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12973823Ssaidi@eecs.umich.edu } 12984870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12995100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 13003806Ssaidi@eecs.umich.edu} 13013806Ssaidi@eecs.umich.edu 13024997Sgblack@eecs.umich.edu#endif 13034997Sgblack@eecs.umich.edu 13043804Ssaidi@eecs.umich.eduvoid 13056022Sgblack@eecs.umich.eduTLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 13064070Ssaidi@eecs.umich.edu{ 13074070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 13086022Sgblack@eecs.umich.edu TLB * itb = tc->getITBPtr(); 13094070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 13104990Sgblack@eecs.umich.edu c0_tsb_ps0, 13114990Sgblack@eecs.umich.edu c0_config, 13124990Sgblack@eecs.umich.edu cx_tsb_ps0, 13134990Sgblack@eecs.umich.edu cx_config); 13144070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 13154990Sgblack@eecs.umich.edu c0_tsb_ps1, 13164990Sgblack@eecs.umich.edu c0_config, 13174990Sgblack@eecs.umich.edu cx_tsb_ps1, 13184990Sgblack@eecs.umich.edu cx_config); 13194070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13204990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13214990Sgblack@eecs.umich.edu itb->c0_config, 13224990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13234990Sgblack@eecs.umich.edu itb->cx_config); 13244070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13254990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13264990Sgblack@eecs.umich.edu itb->c0_config, 13274990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13284990Sgblack@eecs.umich.edu itb->cx_config); 13294070Ssaidi@eecs.umich.edu} 13304070Ssaidi@eecs.umich.edu 13314070Ssaidi@eecs.umich.eduuint64_t 13326022Sgblack@eecs.umich.eduTLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13334070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13344070Ssaidi@eecs.umich.edu{ 13354070Ssaidi@eecs.umich.edu uint64_t tsb; 13364070Ssaidi@eecs.umich.edu uint64_t config; 13374070Ssaidi@eecs.umich.edu 13384070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13394070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13404070Ssaidi@eecs.umich.edu config = c0_config; 13414070Ssaidi@eecs.umich.edu } else { 13424070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13434070Ssaidi@eecs.umich.edu config = cX_config; 13444070Ssaidi@eecs.umich.edu } 13454070Ssaidi@eecs.umich.edu 13464070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13474070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13484070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13494070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13504070Ssaidi@eecs.umich.edu 13514070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13524070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13534070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13544070Ssaidi@eecs.umich.edu 13554070Ssaidi@eecs.umich.edu return ptr; 13564070Ssaidi@eecs.umich.edu} 13574070Ssaidi@eecs.umich.edu 13584070Ssaidi@eecs.umich.eduvoid 13593804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13603804Ssaidi@eecs.umich.edu{ 13614000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13624000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13634000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13644000Ssaidi@eecs.umich.edu 13654000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13664000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13674000Ssaidi@eecs.umich.edu int cntr = 0; 13684000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13694000Ssaidi@eecs.umich.edu i = freeList.begin(); 13704000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13714000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13724000Ssaidi@eecs.umich.edu i++; 13734000Ssaidi@eecs.umich.edu } 13744000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13754000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13764000Ssaidi@eecs.umich.edu 13774990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13784990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13794990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13804990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13814990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13824990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13834990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13844990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13855276Ssaidi@eecs.umich.edu 13865276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13875276Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13885276Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13895276Ssaidi@eecs.umich.edu } 13906022Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 13913804Ssaidi@eecs.umich.edu} 13923804Ssaidi@eecs.umich.edu 13933804Ssaidi@eecs.umich.eduvoid 13943804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13953804Ssaidi@eecs.umich.edu{ 13964000Ssaidi@eecs.umich.edu int oldSize; 13974000Ssaidi@eecs.umich.edu 13984000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13994000Ssaidi@eecs.umich.edu if (oldSize != size) 14004000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 14014000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 14024000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 14034000Ssaidi@eecs.umich.edu 14044000Ssaidi@eecs.umich.edu int cntr; 14054000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 14064000Ssaidi@eecs.umich.edu 14074000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 14084000Ssaidi@eecs.umich.edu freeList.clear(); 14094000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 14104000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 14114000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 14124000Ssaidi@eecs.umich.edu 14134990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 14144990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14154990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14164990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14174990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14184990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14194990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14204990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14215276Ssaidi@eecs.umich.edu 14225276Ssaidi@eecs.umich.edu lookupTable.clear(); 14235276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 14245276Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 14255276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14265276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14275276Ssaidi@eecs.umich.edu 14285276Ssaidi@eecs.umich.edu } 14294990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14303804Ssaidi@eecs.umich.edu} 14313804Ssaidi@eecs.umich.edu 14324088Sbinkertn@umich.edu/* end namespace SparcISA */ } 14334088Sbinkertn@umich.edu 14346022Sgblack@eecs.umich.eduSparcISA::TLB * 14356022Sgblack@eecs.umich.eduSparcTLBParams::create() 14363804Ssaidi@eecs.umich.edu{ 14376022Sgblack@eecs.umich.edu return new SparcISA::TLB(this); 14383804Ssaidi@eecs.umich.edu} 1439