tlb.cc revision 4996
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 424762Snate@binkert.org#include "params/SparcDTB.hh" 434762Snate@binkert.org#include "params/SparcITB.hh" 444103Ssaidi@eecs.umich.edu#include "sim/system.hh" 453569Sgblack@eecs.umich.edu 463804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 473804Ssaidi@eecs.umich.edu * */ 484088Sbinkertn@umich.edunamespace SparcISA { 493569Sgblack@eecs.umich.edu 503804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 513881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 523881Ssaidi@eecs.umich.edu cacheValid(false) 533804Ssaidi@eecs.umich.edu{ 543804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 553804Ssaidi@eecs.umich.edu if (size > 64) 563804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 573569Sgblack@eecs.umich.edu 583804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 593918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 603881Ssaidi@eecs.umich.edu 613881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 623881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 634990Sgblack@eecs.umich.edu 644990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 654990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 664990Sgblack@eecs.umich.edu c0_config = 0; 674990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 684990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 694990Sgblack@eecs.umich.edu cx_config = 0; 704990Sgblack@eecs.umich.edu sfsr = 0; 714990Sgblack@eecs.umich.edu tag_access = 0; 723804Ssaidi@eecs.umich.edu} 733569Sgblack@eecs.umich.edu 743804Ssaidi@eecs.umich.eduvoid 753804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 763804Ssaidi@eecs.umich.edu{ 773804Ssaidi@eecs.umich.edu MapIter i; 783881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 793804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 803804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 813804Ssaidi@eecs.umich.edu t->used = false; 823804Ssaidi@eecs.umich.edu usedEntries--; 833804Ssaidi@eecs.umich.edu } 843804Ssaidi@eecs.umich.edu } 853804Ssaidi@eecs.umich.edu} 863569Sgblack@eecs.umich.edu 873569Sgblack@eecs.umich.edu 883804Ssaidi@eecs.umich.eduvoid 893804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 903826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 913804Ssaidi@eecs.umich.edu{ 923569Sgblack@eecs.umich.edu 933569Sgblack@eecs.umich.edu 943804Ssaidi@eecs.umich.edu MapIter i; 953826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 963907Ssaidi@eecs.umich.edu// TlbRange tr; 973826Ssaidi@eecs.umich.edu int x; 983811Ssaidi@eecs.umich.edu 993836Ssaidi@eecs.umich.edu cacheValid = false; 1003915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1013907Ssaidi@eecs.umich.edu /* tr.va = va; 1023881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1033881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1043881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1053881Ssaidi@eecs.umich.edu tr.real = real; 1063907Ssaidi@eecs.umich.edu*/ 1073881Ssaidi@eecs.umich.edu 1083881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1093881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1103881Ssaidi@eecs.umich.edu 1113881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1123907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1133907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1143907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1153907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1163907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1173907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1183907Ssaidi@eecs.umich.edu { 1193907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1203907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1213907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1223907Ssaidi@eecs.umich.edu 1233907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1243907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1253907Ssaidi@eecs.umich.edu tlb[x].used = false; 1263907Ssaidi@eecs.umich.edu usedEntries--; 1273907Ssaidi@eecs.umich.edu } 1283907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1293907Ssaidi@eecs.umich.edu } 1303907Ssaidi@eecs.umich.edu } 1313907Ssaidi@eecs.umich.edu } 1323907Ssaidi@eecs.umich.edu 1333907Ssaidi@eecs.umich.edu 1343907Ssaidi@eecs.umich.edu/* 1353881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1363881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1373881Ssaidi@eecs.umich.edu i->second->valid = false; 1383881Ssaidi@eecs.umich.edu if (i->second->used) { 1393881Ssaidi@eecs.umich.edu i->second->used = false; 1403881Ssaidi@eecs.umich.edu usedEntries--; 1413881Ssaidi@eecs.umich.edu } 1423881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1433881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1443881Ssaidi@eecs.umich.edu i->second); 1453881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1463881Ssaidi@eecs.umich.edu } 1473907Ssaidi@eecs.umich.edu*/ 1483811Ssaidi@eecs.umich.edu 1493826Ssaidi@eecs.umich.edu if (entry != -1) { 1503826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1513826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1523826Ssaidi@eecs.umich.edu } else { 1533881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1543881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1553881Ssaidi@eecs.umich.edu } else { 1563881Ssaidi@eecs.umich.edu x = lastReplaced; 1573881Ssaidi@eecs.umich.edu do { 1583881Ssaidi@eecs.umich.edu ++x; 1593881Ssaidi@eecs.umich.edu if (x == size) 1603881Ssaidi@eecs.umich.edu x = 0; 1613881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1623881Ssaidi@eecs.umich.edu goto insertAllLocked; 1633881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1643881Ssaidi@eecs.umich.edu lastReplaced = x; 1653881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1663881Ssaidi@eecs.umich.edu } 1673881Ssaidi@eecs.umich.edu /* 1683826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1693826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1703826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1713826Ssaidi@eecs.umich.edu break; 1723826Ssaidi@eecs.umich.edu } 1733881Ssaidi@eecs.umich.edu }*/ 1743569Sgblack@eecs.umich.edu } 1753569Sgblack@eecs.umich.edu 1763881Ssaidi@eecs.umich.eduinsertAllLocked: 1773804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1783881Ssaidi@eecs.umich.edu if (!new_entry) { 1793826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1803881Ssaidi@eecs.umich.edu } 1813881Ssaidi@eecs.umich.edu 1823881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1833907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1843907Ssaidi@eecs.umich.edu usedEntries--; 1853929Ssaidi@eecs.umich.edu if (new_entry->valid) 1863929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1873907Ssaidi@eecs.umich.edu 1883907Ssaidi@eecs.umich.edu 1893804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1903804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1913881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1923804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1933804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1943804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1953804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1963804Ssaidi@eecs.umich.edu new_entry->used = true;; 1973804Ssaidi@eecs.umich.edu new_entry->valid = true; 1983804Ssaidi@eecs.umich.edu usedEntries++; 1993569Sgblack@eecs.umich.edu 2003569Sgblack@eecs.umich.edu 2013569Sgblack@eecs.umich.edu 2023863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 2033863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 2063804Ssaidi@eecs.umich.edu // one we just inserted 2073804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2083804Ssaidi@eecs.umich.edu clearUsedBits(); 2093804Ssaidi@eecs.umich.edu new_entry->used = true; 2103804Ssaidi@eecs.umich.edu usedEntries++; 2113804Ssaidi@eecs.umich.edu } 2123804Ssaidi@eecs.umich.edu 2133569Sgblack@eecs.umich.edu} 2143804Ssaidi@eecs.umich.edu 2153804Ssaidi@eecs.umich.edu 2163804Ssaidi@eecs.umich.eduTlbEntry* 2174070Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id, bool 2184070Ssaidi@eecs.umich.edu update_used) 2193804Ssaidi@eecs.umich.edu{ 2203804Ssaidi@eecs.umich.edu MapIter i; 2213804Ssaidi@eecs.umich.edu TlbRange tr; 2223804Ssaidi@eecs.umich.edu TlbEntry *t; 2233804Ssaidi@eecs.umich.edu 2243811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2253811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2263804Ssaidi@eecs.umich.edu // Assemble full address structure 2273804Ssaidi@eecs.umich.edu tr.va = va; 2283863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2293804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2303804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2313804Ssaidi@eecs.umich.edu tr.real = real; 2323804Ssaidi@eecs.umich.edu 2333804Ssaidi@eecs.umich.edu // Try to find the entry 2343804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2353804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2363811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2373804Ssaidi@eecs.umich.edu return NULL; 2383804Ssaidi@eecs.umich.edu } 2393804Ssaidi@eecs.umich.edu 2403804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2413804Ssaidi@eecs.umich.edu t = i->second; 2423826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2433826Ssaidi@eecs.umich.edu t->pte.size()); 2444070Ssaidi@eecs.umich.edu 2454070Ssaidi@eecs.umich.edu // Update the used bits only if this is a real access (not a fake one from 2464070Ssaidi@eecs.umich.edu // virttophys() 2474070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2483804Ssaidi@eecs.umich.edu t->used = true; 2493804Ssaidi@eecs.umich.edu usedEntries++; 2503804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2513804Ssaidi@eecs.umich.edu clearUsedBits(); 2523804Ssaidi@eecs.umich.edu t->used = true; 2533804Ssaidi@eecs.umich.edu usedEntries++; 2543804Ssaidi@eecs.umich.edu } 2553804Ssaidi@eecs.umich.edu } 2563804Ssaidi@eecs.umich.edu 2573804Ssaidi@eecs.umich.edu return t; 2583804Ssaidi@eecs.umich.edu} 2593804Ssaidi@eecs.umich.edu 2603826Ssaidi@eecs.umich.eduvoid 2613826Ssaidi@eecs.umich.eduTLB::dumpAll() 2623826Ssaidi@eecs.umich.edu{ 2633863Ssaidi@eecs.umich.edu MapIter i; 2643826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2653826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2663826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2673826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2683826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2693826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2703826Ssaidi@eecs.umich.edu } 2713826Ssaidi@eecs.umich.edu } 2723826Ssaidi@eecs.umich.edu} 2733804Ssaidi@eecs.umich.edu 2743804Ssaidi@eecs.umich.eduvoid 2753804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2763804Ssaidi@eecs.umich.edu{ 2773804Ssaidi@eecs.umich.edu TlbRange tr; 2783804Ssaidi@eecs.umich.edu MapIter i; 2793804Ssaidi@eecs.umich.edu 2803863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2813863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2823863Ssaidi@eecs.umich.edu 2833836Ssaidi@eecs.umich.edu cacheValid = false; 2843836Ssaidi@eecs.umich.edu 2853804Ssaidi@eecs.umich.edu // Assemble full address structure 2863804Ssaidi@eecs.umich.edu tr.va = va; 2873863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2883804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2893804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2903804Ssaidi@eecs.umich.edu tr.real = real; 2913804Ssaidi@eecs.umich.edu 2923804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2933804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2943804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2953863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2963804Ssaidi@eecs.umich.edu i->second->valid = false; 2973804Ssaidi@eecs.umich.edu if (i->second->used) { 2983804Ssaidi@eecs.umich.edu i->second->used = false; 2993804Ssaidi@eecs.umich.edu usedEntries--; 3003804Ssaidi@eecs.umich.edu } 3013881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 3023804Ssaidi@eecs.umich.edu lookupTable.erase(i); 3033804Ssaidi@eecs.umich.edu } 3043804Ssaidi@eecs.umich.edu} 3053804Ssaidi@eecs.umich.edu 3063804Ssaidi@eecs.umich.eduvoid 3073804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 3083804Ssaidi@eecs.umich.edu{ 3093804Ssaidi@eecs.umich.edu int x; 3103863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3113863Ssaidi@eecs.umich.edu partition_id, context_id); 3123836Ssaidi@eecs.umich.edu cacheValid = false; 3133804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3143804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3153804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3163881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3173881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3183881Ssaidi@eecs.umich.edu } 3193804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3203804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3213804Ssaidi@eecs.umich.edu tlb[x].used = false; 3223804Ssaidi@eecs.umich.edu usedEntries--; 3233804Ssaidi@eecs.umich.edu } 3243804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3253804Ssaidi@eecs.umich.edu } 3263804Ssaidi@eecs.umich.edu } 3273804Ssaidi@eecs.umich.edu} 3283804Ssaidi@eecs.umich.edu 3293804Ssaidi@eecs.umich.eduvoid 3303804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3313804Ssaidi@eecs.umich.edu{ 3323804Ssaidi@eecs.umich.edu int x; 3333863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3343836Ssaidi@eecs.umich.edu cacheValid = false; 3353804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3363804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3373881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3383881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3393881Ssaidi@eecs.umich.edu } 3403804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3413804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3423804Ssaidi@eecs.umich.edu tlb[x].used = false; 3433804Ssaidi@eecs.umich.edu usedEntries--; 3443804Ssaidi@eecs.umich.edu } 3453804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3463804Ssaidi@eecs.umich.edu } 3473804Ssaidi@eecs.umich.edu } 3483804Ssaidi@eecs.umich.edu} 3493804Ssaidi@eecs.umich.edu 3503804Ssaidi@eecs.umich.eduvoid 3513804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3523804Ssaidi@eecs.umich.edu{ 3533804Ssaidi@eecs.umich.edu int x; 3543836Ssaidi@eecs.umich.edu cacheValid = false; 3553836Ssaidi@eecs.umich.edu 3563881Ssaidi@eecs.umich.edu freeList.clear(); 3573907Ssaidi@eecs.umich.edu lookupTable.clear(); 3583804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3593881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3603881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3613804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3623907Ssaidi@eecs.umich.edu tlb[x].used = false; 3633804Ssaidi@eecs.umich.edu } 3643804Ssaidi@eecs.umich.edu usedEntries = 0; 3653804Ssaidi@eecs.umich.edu} 3663804Ssaidi@eecs.umich.edu 3673804Ssaidi@eecs.umich.eduuint64_t 3683804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3693881Ssaidi@eecs.umich.edu if (entry >= size) 3703881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3713881Ssaidi@eecs.umich.edu 3723804Ssaidi@eecs.umich.edu assert(entry < size); 3733881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3743881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3753881Ssaidi@eecs.umich.edu else 3763881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3773804Ssaidi@eecs.umich.edu} 3783804Ssaidi@eecs.umich.edu 3793804Ssaidi@eecs.umich.eduuint64_t 3803804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3813804Ssaidi@eecs.umich.edu assert(entry < size); 3823804Ssaidi@eecs.umich.edu uint64_t tag; 3833881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3843881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3853804Ssaidi@eecs.umich.edu 3863881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3873881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3883881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3893804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3903804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3913804Ssaidi@eecs.umich.edu return tag; 3923804Ssaidi@eecs.umich.edu} 3933804Ssaidi@eecs.umich.edu 3943804Ssaidi@eecs.umich.edubool 3953804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3963804Ssaidi@eecs.umich.edu{ 3973804Ssaidi@eecs.umich.edu if (am) 3983804Ssaidi@eecs.umich.edu return true; 3993804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 4003804Ssaidi@eecs.umich.edu return false; 4013804Ssaidi@eecs.umich.edu return true; 4023804Ssaidi@eecs.umich.edu} 4033804Ssaidi@eecs.umich.edu 4043804Ssaidi@eecs.umich.eduvoid 4054990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 4063804Ssaidi@eecs.umich.edu{ 4073804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4083804Ssaidi@eecs.umich.edu sfsr = 0x3; 4093804Ssaidi@eecs.umich.edu else 4103804Ssaidi@eecs.umich.edu sfsr = 1; 4113804Ssaidi@eecs.umich.edu 4123804Ssaidi@eecs.umich.edu if (write) 4133804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4143804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4153804Ssaidi@eecs.umich.edu if (se) 4163804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4173804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4183804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4193804Ssaidi@eecs.umich.edu} 4203804Ssaidi@eecs.umich.edu 4213826Ssaidi@eecs.umich.eduvoid 4224990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 4233826Ssaidi@eecs.umich.edu{ 4243916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4253916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4263916Ssaidi@eecs.umich.edu 4274990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4283826Ssaidi@eecs.umich.edu} 4293804Ssaidi@eecs.umich.edu 4303804Ssaidi@eecs.umich.eduvoid 4314990Sgblack@eecs.umich.eduITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 4323804Ssaidi@eecs.umich.edu{ 4333811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4343811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4354990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4363804Ssaidi@eecs.umich.edu} 4373804Ssaidi@eecs.umich.edu 4383804Ssaidi@eecs.umich.eduvoid 4394990Sgblack@eecs.umich.eduDTB::writeSfsr(Addr a, bool write, ContextType ct, 4403804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4413804Ssaidi@eecs.umich.edu{ 4423811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4433811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4444990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4454990Sgblack@eecs.umich.edu sfar = a; 4463804Ssaidi@eecs.umich.edu} 4473804Ssaidi@eecs.umich.edu 4483804Ssaidi@eecs.umich.eduFault 4493804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4503804Ssaidi@eecs.umich.edu{ 4514172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4523833Ssaidi@eecs.umich.edu 4533836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4543836Ssaidi@eecs.umich.edu TlbEntry *e; 4553836Ssaidi@eecs.umich.edu 4563836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4573836Ssaidi@eecs.umich.edu 4583836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4593836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4603836Ssaidi@eecs.umich.edu 4613836Ssaidi@eecs.umich.edu // Be fast if we can! 4623836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4633836Ssaidi@eecs.umich.edu if (cacheEntry) { 4643836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4653836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4663836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4673836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4683836Ssaidi@eecs.umich.edu return NoFault; 4693836Ssaidi@eecs.umich.edu } 4703836Ssaidi@eecs.umich.edu } else { 4713836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4723836Ssaidi@eecs.umich.edu return NoFault; 4733836Ssaidi@eecs.umich.edu } 4743836Ssaidi@eecs.umich.edu } 4753836Ssaidi@eecs.umich.edu 4763833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4773833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4783833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4793833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4803833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4813833Ssaidi@eecs.umich.edu 4823833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4833833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4843833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4853804Ssaidi@eecs.umich.edu int context; 4863804Ssaidi@eecs.umich.edu ContextType ct; 4873804Ssaidi@eecs.umich.edu int asi; 4883804Ssaidi@eecs.umich.edu bool real = false; 4893804Ssaidi@eecs.umich.edu 4903833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4913833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4923811Ssaidi@eecs.umich.edu 4933804Ssaidi@eecs.umich.edu if (tl > 0) { 4943804Ssaidi@eecs.umich.edu asi = ASI_N; 4953804Ssaidi@eecs.umich.edu ct = Nucleus; 4963804Ssaidi@eecs.umich.edu context = 0; 4973804Ssaidi@eecs.umich.edu } else { 4983804Ssaidi@eecs.umich.edu asi = ASI_P; 4993804Ssaidi@eecs.umich.edu ct = Primary; 5003833Ssaidi@eecs.umich.edu context = pri_context; 5013804Ssaidi@eecs.umich.edu } 5023804Ssaidi@eecs.umich.edu 5033833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5043836Ssaidi@eecs.umich.edu cacheValid = true; 5053836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5063836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5073836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5083804Ssaidi@eecs.umich.edu return NoFault; 5093804Ssaidi@eecs.umich.edu } 5103804Ssaidi@eecs.umich.edu 5113836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5123836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5134990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 5143804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5153804Ssaidi@eecs.umich.edu } 5163804Ssaidi@eecs.umich.edu 5173804Ssaidi@eecs.umich.edu if (addr_mask) 5183804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5193804Ssaidi@eecs.umich.edu 5203804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5214990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 5223804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5233804Ssaidi@eecs.umich.edu } 5243804Ssaidi@eecs.umich.edu 5253833Ssaidi@eecs.umich.edu if (!lsu_im) { 5263836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5273804Ssaidi@eecs.umich.edu real = true; 5283804Ssaidi@eecs.umich.edu context = 0; 5293804Ssaidi@eecs.umich.edu } else { 5303804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5313804Ssaidi@eecs.umich.edu } 5323804Ssaidi@eecs.umich.edu 5333804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5344990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5353804Ssaidi@eecs.umich.edu if (real) 5363804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5373804Ssaidi@eecs.umich.edu else 5383804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5393804Ssaidi@eecs.umich.edu } 5403804Ssaidi@eecs.umich.edu 5413804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5423804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5434990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5444990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5453804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5463804Ssaidi@eecs.umich.edu } 5473804Ssaidi@eecs.umich.edu 5483836Ssaidi@eecs.umich.edu // cache translation date for next translation 5493836Ssaidi@eecs.umich.edu cacheValid = true; 5503836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5513836Ssaidi@eecs.umich.edu cacheEntry = e; 5523836Ssaidi@eecs.umich.edu 5533826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5543836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5553836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5563804Ssaidi@eecs.umich.edu return NoFault; 5573804Ssaidi@eecs.umich.edu} 5583804Ssaidi@eecs.umich.edu 5593804Ssaidi@eecs.umich.edu 5603804Ssaidi@eecs.umich.edu 5613804Ssaidi@eecs.umich.eduFault 5623804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5633804Ssaidi@eecs.umich.edu{ 5643804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5654172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5663836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5673836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5683836Ssaidi@eecs.umich.edu ASI asi; 5693836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5703836Ssaidi@eecs.umich.edu bool implicit = false; 5713836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5724996Sgblack@eecs.umich.edu bool unaligned = (vaddr & size-1); 5733833Ssaidi@eecs.umich.edu 5743836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5753836Ssaidi@eecs.umich.edu vaddr, size, asi); 5763836Ssaidi@eecs.umich.edu 5773929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5783929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5793929Ssaidi@eecs.umich.edu freeList.size()); 5803836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5813836Ssaidi@eecs.umich.edu implicit = true; 5823836Ssaidi@eecs.umich.edu 5834996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5844996Sgblack@eecs.umich.edu // trap later 5854996Sgblack@eecs.umich.edu if (!unaligned) { 5864996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5874996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5884996Sgblack@eecs.umich.edu return NoFault; 5894996Sgblack@eecs.umich.edu } 5904996Sgblack@eecs.umich.edu 5914996Sgblack@eecs.umich.edu // Be fast if we can! 5924996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5934996Sgblack@eecs.umich.edu 5944996Sgblack@eecs.umich.edu 5954996Sgblack@eecs.umich.edu 5964996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5974996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5984996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5994996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 6004996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6014996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6024996Sgblack@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6034996Sgblack@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6044996Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6054996Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6064996Sgblack@eecs.umich.edu return NoFault; 6074996Sgblack@eecs.umich.edu } // if matched 6084996Sgblack@eecs.umich.edu } // if cache entry valid 6094996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 6104996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 6114996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6124996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 6134996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6144996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6154996Sgblack@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6164996Sgblack@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6174996Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6184996Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6194996Sgblack@eecs.umich.edu return NoFault; 6204996Sgblack@eecs.umich.edu } // if matched 6214996Sgblack@eecs.umich.edu } // if cache entry valid 6224996Sgblack@eecs.umich.edu } 6233836Ssaidi@eecs.umich.edu } 6243836Ssaidi@eecs.umich.edu 6253833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6263833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6273833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6283833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6293833Ssaidi@eecs.umich.edu 6303833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6313833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6323833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6333916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6343833Ssaidi@eecs.umich.edu 6353804Ssaidi@eecs.umich.edu bool real = false; 6363832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6373832Ssaidi@eecs.umich.edu int context = 0; 6383804Ssaidi@eecs.umich.edu 6393804Ssaidi@eecs.umich.edu TlbEntry *e; 6403804Ssaidi@eecs.umich.edu 6413833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6423833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6433804Ssaidi@eecs.umich.edu 6443804Ssaidi@eecs.umich.edu if (implicit) { 6453804Ssaidi@eecs.umich.edu if (tl > 0) { 6463804Ssaidi@eecs.umich.edu asi = ASI_N; 6473804Ssaidi@eecs.umich.edu ct = Nucleus; 6483804Ssaidi@eecs.umich.edu context = 0; 6493804Ssaidi@eecs.umich.edu } else { 6503804Ssaidi@eecs.umich.edu asi = ASI_P; 6513804Ssaidi@eecs.umich.edu ct = Primary; 6523833Ssaidi@eecs.umich.edu context = pri_context; 6533804Ssaidi@eecs.umich.edu } 6543910Ssaidi@eecs.umich.edu } else { 6553804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6563910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6573804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6584990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6593804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6603804Ssaidi@eecs.umich.edu } 6613910Ssaidi@eecs.umich.edu 6623910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6634990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6643804Ssaidi@eecs.umich.edu return new DataAccessException; 6653804Ssaidi@eecs.umich.edu } 6663804Ssaidi@eecs.umich.edu 6673910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6683910Ssaidi@eecs.umich.edu context = pri_context; 6693910Ssaidi@eecs.umich.edu ct = Primary; 6703910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6713910Ssaidi@eecs.umich.edu context = sec_context; 6723910Ssaidi@eecs.umich.edu ct = Secondary; 6733910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6743910Ssaidi@eecs.umich.edu ct = Nucleus; 6753910Ssaidi@eecs.umich.edu context = 0; 6763910Ssaidi@eecs.umich.edu } else { // ???? 6773910Ssaidi@eecs.umich.edu ct = Primary; 6783910Ssaidi@eecs.umich.edu context = pri_context; 6793910Ssaidi@eecs.umich.edu } 6803902Ssaidi@eecs.umich.edu } 6813804Ssaidi@eecs.umich.edu 6823926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6833804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6843804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6854989Sgblack@eecs.umich.edu 6864989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6874989Sgblack@eecs.umich.edu //load differs from a regular one, other than what happens concerning 6884989Sgblack@eecs.umich.edu //nfo and e bits in the TTE 6894989Sgblack@eecs.umich.edu// if (AsiIsNoFault(asi)) 6904989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6913856Ssaidi@eecs.umich.edu 6923804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6933804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6944103Ssaidi@eecs.umich.edu 6954191Ssaidi@eecs.umich.edu if (AsiIsCmt(asi)) 6964191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6974191Ssaidi@eecs.umich.edu 6983824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6994103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 7003804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 7013804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 7023804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 7033804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 7043824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 7053824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 7063825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 7073825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 7083823Ssaidi@eecs.umich.edu 7093926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 7104989Sgblack@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 7113823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 7123804Ssaidi@eecs.umich.edu } 7133804Ssaidi@eecs.umich.edu 7143826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 7154996Sgblack@eecs.umich.edu if (unaligned) { 7164990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 7173826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7183826Ssaidi@eecs.umich.edu } 7193826Ssaidi@eecs.umich.edu 7203826Ssaidi@eecs.umich.edu if (addr_mask) 7213826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7223826Ssaidi@eecs.umich.edu 7233826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7244990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 7253826Ssaidi@eecs.umich.edu return new DataAccessException; 7263826Ssaidi@eecs.umich.edu } 7273826Ssaidi@eecs.umich.edu 7283826Ssaidi@eecs.umich.edu 7293910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7303804Ssaidi@eecs.umich.edu real = true; 7313804Ssaidi@eecs.umich.edu context = 0; 7323804Ssaidi@eecs.umich.edu }; 7333804Ssaidi@eecs.umich.edu 7343804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7353836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7363804Ssaidi@eecs.umich.edu return NoFault; 7373804Ssaidi@eecs.umich.edu } 7383804Ssaidi@eecs.umich.edu 7393836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7403804Ssaidi@eecs.umich.edu 7413804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7424990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7433811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7443804Ssaidi@eecs.umich.edu if (real) 7453804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7463804Ssaidi@eecs.umich.edu else 7473804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7483804Ssaidi@eecs.umich.edu 7493804Ssaidi@eecs.umich.edu } 7503804Ssaidi@eecs.umich.edu 7513928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7524990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7534990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7543928Ssaidi@eecs.umich.edu return new DataAccessException; 7553928Ssaidi@eecs.umich.edu } 7563804Ssaidi@eecs.umich.edu 7573804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7584990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7594990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7603804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7613804Ssaidi@eecs.umich.edu } 7623804Ssaidi@eecs.umich.edu 7633804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7644990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7654990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7663804Ssaidi@eecs.umich.edu return new DataAccessException; 7673804Ssaidi@eecs.umich.edu } 7683804Ssaidi@eecs.umich.edu 7693928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7704990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7714990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7723928Ssaidi@eecs.umich.edu return new DataAccessException; 7733928Ssaidi@eecs.umich.edu } 7743928Ssaidi@eecs.umich.edu 7753928Ssaidi@eecs.umich.edu 7764090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7773804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7783804Ssaidi@eecs.umich.edu 7793836Ssaidi@eecs.umich.edu // cache translation date for next translation 7803836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7813881Ssaidi@eecs.umich.edu if (!cacheValid) { 7823881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7833881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7843881Ssaidi@eecs.umich.edu } 7853881Ssaidi@eecs.umich.edu 7863836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7873836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7883836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7893836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7903836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7913836Ssaidi@eecs.umich.edu if (implicit) 7923836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7933836Ssaidi@eecs.umich.edu } 7943881Ssaidi@eecs.umich.edu cacheValid = true; 7953826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 7963836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 7973836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7983804Ssaidi@eecs.umich.edu return NoFault; 7994103Ssaidi@eecs.umich.edu 8003806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 8014103Ssaidi@eecs.umich.eduhandleIntRegAccess: 8024103Ssaidi@eecs.umich.edu if (!hpriv) { 8034990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8044103Ssaidi@eecs.umich.edu if (priv) 8054103Ssaidi@eecs.umich.edu return new DataAccessException; 8064103Ssaidi@eecs.umich.edu else 8074103Ssaidi@eecs.umich.edu return new PrivilegedAction; 8084103Ssaidi@eecs.umich.edu } 8094103Ssaidi@eecs.umich.edu 8104103Ssaidi@eecs.umich.edu if (asi == ASI_SWVR_UDB_INTR_W && !write || 8114103Ssaidi@eecs.umich.edu asi == ASI_SWVR_UDB_INTR_R && write) { 8124990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8134103Ssaidi@eecs.umich.edu return new DataAccessException; 8144103Ssaidi@eecs.umich.edu } 8154103Ssaidi@eecs.umich.edu 8164103Ssaidi@eecs.umich.edu goto regAccessOk; 8174103Ssaidi@eecs.umich.edu 8183804Ssaidi@eecs.umich.edu 8193806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8203806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8214990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8223806Ssaidi@eecs.umich.edu return new DataAccessException; 8233806Ssaidi@eecs.umich.edu } 8243824Ssaidi@eecs.umich.edu goto regAccessOk; 8253824Ssaidi@eecs.umich.edu 8263824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8273824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8284990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8293824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8303824Ssaidi@eecs.umich.edu } 8313881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 8324990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8333824Ssaidi@eecs.umich.edu return new DataAccessException; 8343824Ssaidi@eecs.umich.edu } 8353824Ssaidi@eecs.umich.edu goto regAccessOk; 8363824Ssaidi@eecs.umich.edu 8373825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8383825Ssaidi@eecs.umich.edu if (!hpriv) { 8394990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8404070Ssaidi@eecs.umich.edu if (priv) 8413825Ssaidi@eecs.umich.edu return new DataAccessException; 8424070Ssaidi@eecs.umich.edu else 8433825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8443825Ssaidi@eecs.umich.edu } 8453825Ssaidi@eecs.umich.edu goto regAccessOk; 8463825Ssaidi@eecs.umich.edu 8473825Ssaidi@eecs.umich.edu 8483824Ssaidi@eecs.umich.eduregAccessOk: 8493804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8503811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8513806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8523806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8533806Ssaidi@eecs.umich.edu return NoFault; 8543804Ssaidi@eecs.umich.edu}; 8553804Ssaidi@eecs.umich.edu 8563806Ssaidi@eecs.umich.eduTick 8573806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8583806Ssaidi@eecs.umich.edu{ 8593823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8603823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8614070Ssaidi@eecs.umich.edu uint64_t temp; 8623823Ssaidi@eecs.umich.edu 8633823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8643823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8653823Ssaidi@eecs.umich.edu 8664990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 8674990Sgblack@eecs.umich.edu 8683823Ssaidi@eecs.umich.edu switch (asi) { 8693823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8703823Ssaidi@eecs.umich.edu assert(va == 0); 8714172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8723823Ssaidi@eecs.umich.edu break; 8733823Ssaidi@eecs.umich.edu case ASI_MMU: 8743823Ssaidi@eecs.umich.edu switch (va) { 8753823Ssaidi@eecs.umich.edu case 0x8: 8764172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8773823Ssaidi@eecs.umich.edu break; 8783823Ssaidi@eecs.umich.edu case 0x10: 8794172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8803823Ssaidi@eecs.umich.edu break; 8813823Ssaidi@eecs.umich.edu default: 8823823Ssaidi@eecs.umich.edu goto doMmuReadError; 8833823Ssaidi@eecs.umich.edu } 8843823Ssaidi@eecs.umich.edu break; 8853824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8864172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8873824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8883824Ssaidi@eecs.umich.edu break; 8893823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8903823Ssaidi@eecs.umich.edu assert(va == 0); 8914990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 8923823Ssaidi@eecs.umich.edu break; 8933823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8943823Ssaidi@eecs.umich.edu assert(va == 0); 8954990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 8963823Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8983823Ssaidi@eecs.umich.edu assert(va == 0); 8994990Sgblack@eecs.umich.edu pkt->set(c0_config); 9003823Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 9034990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9074990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 9114990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 9154990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 9194990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 9234990Sgblack@eecs.umich.edu pkt->set(cx_config); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 9274990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 9314990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9323823Ssaidi@eecs.umich.edu break; 9333823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9343823Ssaidi@eecs.umich.edu assert(va == 0); 9354990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9363823Ssaidi@eecs.umich.edu break; 9373826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9383912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9393826Ssaidi@eecs.umich.edu break; 9403823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9413823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9424172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9433823Ssaidi@eecs.umich.edu break; 9443826Ssaidi@eecs.umich.edu case ASI_IMMU: 9453826Ssaidi@eecs.umich.edu switch (va) { 9463833Ssaidi@eecs.umich.edu case 0x0: 9474990Sgblack@eecs.umich.edu temp = itb->tag_access; 9483833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9493833Ssaidi@eecs.umich.edu break; 9503906Ssaidi@eecs.umich.edu case 0x18: 9514990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9523906Ssaidi@eecs.umich.edu break; 9533826Ssaidi@eecs.umich.edu case 0x30: 9544990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9553826Ssaidi@eecs.umich.edu break; 9563826Ssaidi@eecs.umich.edu default: 9573826Ssaidi@eecs.umich.edu goto doMmuReadError; 9583826Ssaidi@eecs.umich.edu } 9593826Ssaidi@eecs.umich.edu break; 9603823Ssaidi@eecs.umich.edu case ASI_DMMU: 9613823Ssaidi@eecs.umich.edu switch (va) { 9623833Ssaidi@eecs.umich.edu case 0x0: 9634990Sgblack@eecs.umich.edu temp = tag_access; 9643833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9653833Ssaidi@eecs.umich.edu break; 9663906Ssaidi@eecs.umich.edu case 0x18: 9674990Sgblack@eecs.umich.edu pkt->set(sfsr); 9683906Ssaidi@eecs.umich.edu break; 9693906Ssaidi@eecs.umich.edu case 0x20: 9704990Sgblack@eecs.umich.edu pkt->set(sfar); 9713906Ssaidi@eecs.umich.edu break; 9723826Ssaidi@eecs.umich.edu case 0x30: 9734990Sgblack@eecs.umich.edu pkt->set(tag_access); 9743826Ssaidi@eecs.umich.edu break; 9753823Ssaidi@eecs.umich.edu case 0x80: 9764172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9773823Ssaidi@eecs.umich.edu break; 9783823Ssaidi@eecs.umich.edu default: 9793823Ssaidi@eecs.umich.edu goto doMmuReadError; 9803823Ssaidi@eecs.umich.edu } 9813823Ssaidi@eecs.umich.edu break; 9823833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9834070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9844990Sgblack@eecs.umich.edu tag_access, 9854990Sgblack@eecs.umich.edu c0_tsb_ps0, 9864990Sgblack@eecs.umich.edu c0_config, 9874990Sgblack@eecs.umich.edu cx_tsb_ps0, 9884990Sgblack@eecs.umich.edu cx_config)); 9893833Ssaidi@eecs.umich.edu break; 9903833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9914070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9924990Sgblack@eecs.umich.edu tag_access, 9934990Sgblack@eecs.umich.edu c0_tsb_ps1, 9944990Sgblack@eecs.umich.edu c0_config, 9954990Sgblack@eecs.umich.edu cx_tsb_ps1, 9964990Sgblack@eecs.umich.edu cx_config)); 9973833Ssaidi@eecs.umich.edu break; 9983899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9994070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10004990Sgblack@eecs.umich.edu itb->tag_access, 10014990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10024990Sgblack@eecs.umich.edu itb->c0_config, 10034990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10044990Sgblack@eecs.umich.edu itb->cx_config)); 10053899Ssaidi@eecs.umich.edu break; 10063899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10074070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10084990Sgblack@eecs.umich.edu itb->tag_access, 10094990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10104990Sgblack@eecs.umich.edu itb->c0_config, 10114990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10124990Sgblack@eecs.umich.edu itb->cx_config)); 10133899Ssaidi@eecs.umich.edu break; 10144103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10154103Ssaidi@eecs.umich.edu pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10164103Ssaidi@eecs.umich.edu break; 10174103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10184103Ssaidi@eecs.umich.edu temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10194103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); 10204103Ssaidi@eecs.umich.edu pkt->set(temp); 10214103Ssaidi@eecs.umich.edu break; 10223823Ssaidi@eecs.umich.edu default: 10233823Ssaidi@eecs.umich.edudoMmuReadError: 10243823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10253823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10263823Ssaidi@eecs.umich.edu } 10274870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10283823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 10293806Ssaidi@eecs.umich.edu} 10303806Ssaidi@eecs.umich.edu 10313806Ssaidi@eecs.umich.eduTick 10323806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10333806Ssaidi@eecs.umich.edu{ 10343823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10353823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10363823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10373823Ssaidi@eecs.umich.edu 10383826Ssaidi@eecs.umich.edu Addr ta_insert; 10393826Ssaidi@eecs.umich.edu Addr va_insert; 10403826Ssaidi@eecs.umich.edu Addr ct_insert; 10413826Ssaidi@eecs.umich.edu int part_insert; 10423826Ssaidi@eecs.umich.edu int entry_insert = -1; 10433826Ssaidi@eecs.umich.edu bool real_insert; 10443863Ssaidi@eecs.umich.edu bool ignore; 10453863Ssaidi@eecs.umich.edu int part_id; 10463863Ssaidi@eecs.umich.edu int ctx_id; 10473826Ssaidi@eecs.umich.edu PageTableEntry pte; 10483826Ssaidi@eecs.umich.edu 10493825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10503823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10513823Ssaidi@eecs.umich.edu 10524990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 10534990Sgblack@eecs.umich.edu 10543823Ssaidi@eecs.umich.edu switch (asi) { 10553823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10563823Ssaidi@eecs.umich.edu assert(va == 0); 10574172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10583823Ssaidi@eecs.umich.edu break; 10593823Ssaidi@eecs.umich.edu case ASI_MMU: 10603823Ssaidi@eecs.umich.edu switch (va) { 10613823Ssaidi@eecs.umich.edu case 0x8: 10624172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10633823Ssaidi@eecs.umich.edu break; 10643823Ssaidi@eecs.umich.edu case 0x10: 10654172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10663823Ssaidi@eecs.umich.edu break; 10673823Ssaidi@eecs.umich.edu default: 10683823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10693823Ssaidi@eecs.umich.edu } 10703823Ssaidi@eecs.umich.edu break; 10713824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10723825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10734172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10743824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10753824Ssaidi@eecs.umich.edu break; 10763823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10773823Ssaidi@eecs.umich.edu assert(va == 0); 10784990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10793823Ssaidi@eecs.umich.edu break; 10803823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10813823Ssaidi@eecs.umich.edu assert(va == 0); 10824990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10833823Ssaidi@eecs.umich.edu break; 10843823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10853823Ssaidi@eecs.umich.edu assert(va == 0); 10864990Sgblack@eecs.umich.edu c0_config = data; 10873823Ssaidi@eecs.umich.edu break; 10883823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10893823Ssaidi@eecs.umich.edu assert(va == 0); 10904990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 10913823Ssaidi@eecs.umich.edu break; 10923823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10933823Ssaidi@eecs.umich.edu assert(va == 0); 10944990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 10953823Ssaidi@eecs.umich.edu break; 10963823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10973823Ssaidi@eecs.umich.edu assert(va == 0); 10984990Sgblack@eecs.umich.edu itb->c0_config = data; 10993823Ssaidi@eecs.umich.edu break; 11003823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11013823Ssaidi@eecs.umich.edu assert(va == 0); 11024990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11033823Ssaidi@eecs.umich.edu break; 11043823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11053823Ssaidi@eecs.umich.edu assert(va == 0); 11064990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11073823Ssaidi@eecs.umich.edu break; 11083823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11093823Ssaidi@eecs.umich.edu assert(va == 0); 11104990Sgblack@eecs.umich.edu cx_config = data; 11113823Ssaidi@eecs.umich.edu break; 11123823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11133823Ssaidi@eecs.umich.edu assert(va == 0); 11144990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11153823Ssaidi@eecs.umich.edu break; 11163823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11173823Ssaidi@eecs.umich.edu assert(va == 0); 11184990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11193823Ssaidi@eecs.umich.edu break; 11203823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11213823Ssaidi@eecs.umich.edu assert(va == 0); 11224990Sgblack@eecs.umich.edu itb->cx_config = data; 11233823Ssaidi@eecs.umich.edu break; 11243825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11253825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11263825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11273825Ssaidi@eecs.umich.edu break; 11283823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11293823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11304172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11313823Ssaidi@eecs.umich.edu break; 11323826Ssaidi@eecs.umich.edu case ASI_IMMU: 11333826Ssaidi@eecs.umich.edu switch (va) { 11343906Ssaidi@eecs.umich.edu case 0x18: 11354990Sgblack@eecs.umich.edu itb->sfsr = data; 11363906Ssaidi@eecs.umich.edu break; 11373826Ssaidi@eecs.umich.edu case 0x30: 11383916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11394990Sgblack@eecs.umich.edu itb->tag_access = data; 11403826Ssaidi@eecs.umich.edu break; 11413826Ssaidi@eecs.umich.edu default: 11423826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11433826Ssaidi@eecs.umich.edu } 11443826Ssaidi@eecs.umich.edu break; 11453826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11463826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11473826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11483826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11494990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11503826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11513826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11524172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11533826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11543826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11553826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11563826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11573826Ssaidi@eecs.umich.edu pte, entry_insert); 11583826Ssaidi@eecs.umich.edu break; 11593826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11603826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11613826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11623826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11634990Sgblack@eecs.umich.edu ta_insert = tag_access; 11643826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11653826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11664172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11673826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11683826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11693826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11703826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11713826Ssaidi@eecs.umich.edu break; 11723863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11733863Ssaidi@eecs.umich.edu ignore = false; 11743863Ssaidi@eecs.umich.edu ctx_id = -1; 11754172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11763863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11773863Ssaidi@eecs.umich.edu case 0: 11784172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11793863Ssaidi@eecs.umich.edu break; 11803863Ssaidi@eecs.umich.edu case 1: 11813863Ssaidi@eecs.umich.edu ignore = true; 11823863Ssaidi@eecs.umich.edu break; 11833863Ssaidi@eecs.umich.edu case 3: 11843863Ssaidi@eecs.umich.edu ctx_id = 0; 11853863Ssaidi@eecs.umich.edu break; 11863863Ssaidi@eecs.umich.edu default: 11873863Ssaidi@eecs.umich.edu ignore = true; 11883863Ssaidi@eecs.umich.edu } 11893863Ssaidi@eecs.umich.edu 11903863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11913863Ssaidi@eecs.umich.edu case 0: // demap page 11923863Ssaidi@eecs.umich.edu if (!ignore) 11933863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11943863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11953863Ssaidi@eecs.umich.edu break; 11963863Ssaidi@eecs.umich.edu case 1: //demap context 11973863Ssaidi@eecs.umich.edu if (!ignore) 11983863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11993863Ssaidi@eecs.umich.edu break; 12003863Ssaidi@eecs.umich.edu case 2: 12013863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12023863Ssaidi@eecs.umich.edu break; 12033863Ssaidi@eecs.umich.edu default: 12043863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12053863Ssaidi@eecs.umich.edu } 12063863Ssaidi@eecs.umich.edu break; 12073823Ssaidi@eecs.umich.edu case ASI_DMMU: 12083823Ssaidi@eecs.umich.edu switch (va) { 12093906Ssaidi@eecs.umich.edu case 0x18: 12104990Sgblack@eecs.umich.edu sfsr = data; 12113906Ssaidi@eecs.umich.edu break; 12123826Ssaidi@eecs.umich.edu case 0x30: 12133916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12144990Sgblack@eecs.umich.edu tag_access = data; 12153826Ssaidi@eecs.umich.edu break; 12163823Ssaidi@eecs.umich.edu case 0x80: 12174172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12183823Ssaidi@eecs.umich.edu break; 12193823Ssaidi@eecs.umich.edu default: 12203823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12213823Ssaidi@eecs.umich.edu } 12223823Ssaidi@eecs.umich.edu break; 12233863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12243863Ssaidi@eecs.umich.edu ignore = false; 12253863Ssaidi@eecs.umich.edu ctx_id = -1; 12264172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12273863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12283863Ssaidi@eecs.umich.edu case 0: 12294172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12303863Ssaidi@eecs.umich.edu break; 12313863Ssaidi@eecs.umich.edu case 1: 12324172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12333863Ssaidi@eecs.umich.edu break; 12343863Ssaidi@eecs.umich.edu case 3: 12353863Ssaidi@eecs.umich.edu ctx_id = 0; 12363863Ssaidi@eecs.umich.edu break; 12373863Ssaidi@eecs.umich.edu default: 12383863Ssaidi@eecs.umich.edu ignore = true; 12393863Ssaidi@eecs.umich.edu } 12403863Ssaidi@eecs.umich.edu 12413863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12423863Ssaidi@eecs.umich.edu case 0: // demap page 12433863Ssaidi@eecs.umich.edu if (!ignore) 12443863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12453863Ssaidi@eecs.umich.edu break; 12463863Ssaidi@eecs.umich.edu case 1: //demap context 12473863Ssaidi@eecs.umich.edu if (!ignore) 12483863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12493863Ssaidi@eecs.umich.edu break; 12503863Ssaidi@eecs.umich.edu case 2: 12513863Ssaidi@eecs.umich.edu demapAll(part_id); 12523863Ssaidi@eecs.umich.edu break; 12533863Ssaidi@eecs.umich.edu default: 12543863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12553863Ssaidi@eecs.umich.edu } 12563863Ssaidi@eecs.umich.edu break; 12574103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12584103Ssaidi@eecs.umich.edu int msb; 12594103Ssaidi@eecs.umich.edu // clear all the interrupts that aren't set in the write 12604103Ssaidi@eecs.umich.edu while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) { 12614103Ssaidi@eecs.umich.edu msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data); 12624103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); 12634103Ssaidi@eecs.umich.edu } 12644103Ssaidi@eecs.umich.edu break; 12654103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12664103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12674103Ssaidi@eecs.umich.edu post_interrupt(bits(data,5,0),0); 12684103Ssaidi@eecs.umich.edu break; 12694103Ssaidi@eecs.umich.edu default: 12703823Ssaidi@eecs.umich.edudoMmuWriteError: 12713823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12723823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12733823Ssaidi@eecs.umich.edu } 12744870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12753823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 12763806Ssaidi@eecs.umich.edu} 12773806Ssaidi@eecs.umich.edu 12783804Ssaidi@eecs.umich.eduvoid 12794070Ssaidi@eecs.umich.eduDTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12804070Ssaidi@eecs.umich.edu{ 12814070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12824990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 12834070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12844990Sgblack@eecs.umich.edu c0_tsb_ps0, 12854990Sgblack@eecs.umich.edu c0_config, 12864990Sgblack@eecs.umich.edu cx_tsb_ps0, 12874990Sgblack@eecs.umich.edu cx_config); 12884070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 12894990Sgblack@eecs.umich.edu c0_tsb_ps1, 12904990Sgblack@eecs.umich.edu c0_config, 12914990Sgblack@eecs.umich.edu cx_tsb_ps1, 12924990Sgblack@eecs.umich.edu cx_config); 12934070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 12944990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 12954990Sgblack@eecs.umich.edu itb->c0_config, 12964990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 12974990Sgblack@eecs.umich.edu itb->cx_config); 12984070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 12994990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13004990Sgblack@eecs.umich.edu itb->c0_config, 13014990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13024990Sgblack@eecs.umich.edu itb->cx_config); 13034070Ssaidi@eecs.umich.edu} 13044070Ssaidi@eecs.umich.edu 13054070Ssaidi@eecs.umich.edu 13064070Ssaidi@eecs.umich.edu 13074070Ssaidi@eecs.umich.edu 13084070Ssaidi@eecs.umich.edu 13094070Ssaidi@eecs.umich.eduuint64_t 13104070Ssaidi@eecs.umich.eduDTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13114070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13124070Ssaidi@eecs.umich.edu{ 13134070Ssaidi@eecs.umich.edu uint64_t tsb; 13144070Ssaidi@eecs.umich.edu uint64_t config; 13154070Ssaidi@eecs.umich.edu 13164070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13174070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13184070Ssaidi@eecs.umich.edu config = c0_config; 13194070Ssaidi@eecs.umich.edu } else { 13204070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13214070Ssaidi@eecs.umich.edu config = cX_config; 13224070Ssaidi@eecs.umich.edu } 13234070Ssaidi@eecs.umich.edu 13244070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13254070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13264070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13274070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13284070Ssaidi@eecs.umich.edu 13294070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13304070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13314070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13324070Ssaidi@eecs.umich.edu 13334070Ssaidi@eecs.umich.edu return ptr; 13344070Ssaidi@eecs.umich.edu} 13354070Ssaidi@eecs.umich.edu 13364070Ssaidi@eecs.umich.edu 13374070Ssaidi@eecs.umich.eduvoid 13383804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13393804Ssaidi@eecs.umich.edu{ 13404000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13414000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13424000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13434000Ssaidi@eecs.umich.edu 13444000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13454000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13464000Ssaidi@eecs.umich.edu int cntr = 0; 13474000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13484000Ssaidi@eecs.umich.edu i = freeList.begin(); 13494000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13504000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13514000Ssaidi@eecs.umich.edu i++; 13524000Ssaidi@eecs.umich.edu } 13534000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13544000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13554000Ssaidi@eecs.umich.edu 13564000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13574000Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13584000Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13594000Ssaidi@eecs.umich.edu } 13604990Sgblack@eecs.umich.edu 13614990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13624990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13634990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13644990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13654990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13664990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13674990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13684990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13693804Ssaidi@eecs.umich.edu} 13703804Ssaidi@eecs.umich.edu 13713804Ssaidi@eecs.umich.eduvoid 13723804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13733804Ssaidi@eecs.umich.edu{ 13744000Ssaidi@eecs.umich.edu int oldSize; 13754000Ssaidi@eecs.umich.edu 13764000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13774000Ssaidi@eecs.umich.edu if (oldSize != size) 13784000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13794000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13804000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13814000Ssaidi@eecs.umich.edu 13824000Ssaidi@eecs.umich.edu int cntr; 13834000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13844000Ssaidi@eecs.umich.edu 13854000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13864000Ssaidi@eecs.umich.edu freeList.clear(); 13874000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13884000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13894000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 13904000Ssaidi@eecs.umich.edu 13914000Ssaidi@eecs.umich.edu lookupTable.clear(); 13924000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13934000Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 13944000Ssaidi@eecs.umich.edu if (tlb[x].valid) 13954000Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 13964000Ssaidi@eecs.umich.edu 13974000Ssaidi@eecs.umich.edu } 13984990Sgblack@eecs.umich.edu 13994990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 14004990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14014990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14024990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14034990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14044990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14054990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14064990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14074990Sgblack@eecs.umich.edu} 14084990Sgblack@eecs.umich.edu 14094990Sgblack@eecs.umich.eduvoid 14104990Sgblack@eecs.umich.eduDTB::serialize(std::ostream &os) 14114990Sgblack@eecs.umich.edu{ 14124990Sgblack@eecs.umich.edu TLB::serialize(os); 14134990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 14144990Sgblack@eecs.umich.edu} 14154990Sgblack@eecs.umich.edu 14164990Sgblack@eecs.umich.eduvoid 14174990Sgblack@eecs.umich.eduDTB::unserialize(Checkpoint *cp, const std::string §ion) 14184990Sgblack@eecs.umich.edu{ 14194990Sgblack@eecs.umich.edu TLB::unserialize(cp, section); 14204990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14213804Ssaidi@eecs.umich.edu} 14223804Ssaidi@eecs.umich.edu 14234088Sbinkertn@umich.edu/* end namespace SparcISA */ } 14244088Sbinkertn@umich.edu 14254762Snate@binkert.orgSparcISA::ITB * 14264762Snate@binkert.orgSparcITBParams::create() 14273804Ssaidi@eecs.umich.edu{ 14284762Snate@binkert.org return new SparcISA::ITB(name, size); 14293804Ssaidi@eecs.umich.edu} 14303804Ssaidi@eecs.umich.edu 14314762Snate@binkert.orgSparcISA::DTB * 14324762Snate@binkert.orgSparcDTBParams::create() 14333804Ssaidi@eecs.umich.edu{ 14344762Snate@binkert.org return new SparcISA::DTB(name, size); 14353804Ssaidi@eecs.umich.edu} 1436