tlb.cc revision 4172
13931Ssaidi@eecs.umich.edu/* 23388Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33388Sgblack@eecs.umich.edu * All rights reserved. 43388Sgblack@eecs.umich.edu * 53388Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63388Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73388Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83388Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93388Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103388Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113388Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123388Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133388Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143388Sgblack@eecs.umich.edu * this software without specific prior written permission. 153388Sgblack@eecs.umich.edu * 163388Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173388Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183388Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193388Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203388Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213388Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223388Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233388Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243388Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253388Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263388Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273388Sgblack@eecs.umich.edu * 283388Sgblack@eecs.umich.edu * Authors: Ali Saidi 293388Sgblack@eecs.umich.edu */ 303388Sgblack@eecs.umich.edu 313388Sgblack@eecs.umich.edu#include <cstring> 323388Sgblack@eecs.umich.edu 333388Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 343388Sgblack@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353388Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363441Sgblack@eecs.umich.edu#include "base/bitfield.hh" 373441Sgblack@eecs.umich.edu#include "base/trace.hh" 383441Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 393441Sgblack@eecs.umich.edu#include "cpu/base.hh" 403441Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 413441Sgblack@eecs.umich.edu#include "mem/request.hh" 423441Sgblack@eecs.umich.edu#include "sim/builder.hh" 433441Sgblack@eecs.umich.edu#include "sim/system.hh" 443441Sgblack@eecs.umich.edu 453441Sgblack@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 463441Sgblack@eecs.umich.edu * */ 473441Sgblack@eecs.umich.edunamespace SparcISA { 483441Sgblack@eecs.umich.edu 493441Sgblack@eecs.umich.eduTLB::TLB(const std::string &name, int s) 503441Sgblack@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 513441Sgblack@eecs.umich.edu cacheValid(false) 523441Sgblack@eecs.umich.edu{ 533441Sgblack@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 543441Sgblack@eecs.umich.edu if (size > 64) 553441Sgblack@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 563441Sgblack@eecs.umich.edu 573441Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 583441Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 593441Sgblack@eecs.umich.edu 603441Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) 613441Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 623441Sgblack@eecs.umich.edu} 633441Sgblack@eecs.umich.edu 643441Sgblack@eecs.umich.eduvoid 653441Sgblack@eecs.umich.eduTLB::clearUsedBits() 663441Sgblack@eecs.umich.edu{ 673441Sgblack@eecs.umich.edu MapIter i; 683441Sgblack@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 693441Sgblack@eecs.umich.edu TlbEntry *t = i->second; 703441Sgblack@eecs.umich.edu if (!t->pte.locked()) { 713441Sgblack@eecs.umich.edu t->used = false; 723441Sgblack@eecs.umich.edu usedEntries--; 733441Sgblack@eecs.umich.edu } 743441Sgblack@eecs.umich.edu } 753441Sgblack@eecs.umich.edu} 763441Sgblack@eecs.umich.edu 773441Sgblack@eecs.umich.edu 783441Sgblack@eecs.umich.eduvoid 793627Sgblack@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 803441Sgblack@eecs.umich.edu const PageTableEntry& PTE, int entry) 813441Sgblack@eecs.umich.edu{ 827741Sgblack@eecs.umich.edu 833627Sgblack@eecs.umich.edu 843441Sgblack@eecs.umich.edu MapIter i; 853441Sgblack@eecs.umich.edu TlbEntry *new_entry = NULL; 863627Sgblack@eecs.umich.edu// TlbRange tr; 877741Sgblack@eecs.umich.edu int x; 883627Sgblack@eecs.umich.edu 893627Sgblack@eecs.umich.edu cacheValid = false; 903627Sgblack@eecs.umich.edu va &= ~(PTE.size()-1); 913627Sgblack@eecs.umich.edu /* tr.va = va; 923627Sgblack@eecs.umich.edu tr.size = PTE.size() - 1; 937741Sgblack@eecs.umich.edu tr.contextId = context_id; 943441Sgblack@eecs.umich.edu tr.partitionId = partition_id; 953627Sgblack@eecs.umich.edu tr.real = real; 963441Sgblack@eecs.umich.edu*/ 973441Sgblack@eecs.umich.edu 983441Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 993441Sgblack@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1003441Sgblack@eecs.umich.edu 1013441Sgblack@eecs.umich.edu // Demap any entry that conflicts 1023441Sgblack@eecs.umich.edu for (x = 0; x < size; x++) { 1033441Sgblack@eecs.umich.edu if (tlb[x].range.real == real && 1043441Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1053441Sgblack@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1063441Sgblack@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1073441Sgblack@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1083441Sgblack@eecs.umich.edu { 1097741Sgblack@eecs.umich.edu if (tlb[x].valid) { 1103627Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 1113441Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1123441Sgblack@eecs.umich.edu 1133627Sgblack@eecs.umich.edu tlb[x].valid = false; 1147741Sgblack@eecs.umich.edu if (tlb[x].used) { 1153627Sgblack@eecs.umich.edu tlb[x].used = false; 1163627Sgblack@eecs.umich.edu usedEntries--; 1173627Sgblack@eecs.umich.edu } 1187741Sgblack@eecs.umich.edu lookupTable.erase(tlb[x].range); 1193627Sgblack@eecs.umich.edu } 1203441Sgblack@eecs.umich.edu } 1213627Sgblack@eecs.umich.edu } 1227741Sgblack@eecs.umich.edu 1233441Sgblack@eecs.umich.edu 1243627Sgblack@eecs.umich.edu/* 1253441Sgblack@eecs.umich.edu i = lookupTable.find(tr); 1263441Sgblack@eecs.umich.edu if (i != lookupTable.end()) { 1273441Sgblack@eecs.umich.edu i->second->valid = false; 1283441Sgblack@eecs.umich.edu if (i->second->used) { 1293441Sgblack@eecs.umich.edu i->second->used = false; 1303441Sgblack@eecs.umich.edu usedEntries--; 1317741Sgblack@eecs.umich.edu } 1323388Sgblack@eecs.umich.edu freeList.push_front(i->second); 13310196SCurtis.Dunham@arm.com DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1343388Sgblack@eecs.umich.edu i->second); 1353388Sgblack@eecs.umich.edu lookupTable.erase(i); 1363388Sgblack@eecs.umich.edu } 1373388Sgblack@eecs.umich.edu*/ 1383931Ssaidi@eecs.umich.edu 1393388Sgblack@eecs.umich.edu if (entry != -1) { 1403388Sgblack@eecs.umich.edu assert(entry < size && entry >= 0); 1413388Sgblack@eecs.umich.edu new_entry = &tlb[entry]; 1423766Sgblack@eecs.umich.edu } else { 1433391Sgblack@eecs.umich.edu if (!freeList.empty()) { 1447741Sgblack@eecs.umich.edu new_entry = freeList.front(); 1454648Sgblack@eecs.umich.edu } else { 1468442Sgblack@eecs.umich.edu x = lastReplaced; 1473391Sgblack@eecs.umich.edu do { 1487741Sgblack@eecs.umich.edu ++x; 1493391Sgblack@eecs.umich.edu if (x == size) 1503391Sgblack@eecs.umich.edu x = 0; 1517741Sgblack@eecs.umich.edu if (x == lastReplaced) 1527741Sgblack@eecs.umich.edu goto insertAllLocked; 1537741Sgblack@eecs.umich.edu } while (tlb[x].pte.locked()); 1543388Sgblack@eecs.umich.edu lastReplaced = x; 1553388Sgblack@eecs.umich.edu new_entry = &tlb[x]; 1563388Sgblack@eecs.umich.edu } 1573388Sgblack@eecs.umich.edu /* 1583792Sgblack@eecs.umich.edu for (x = 0; x < size; x++) { 1593388Sgblack@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1603792Sgblack@eecs.umich.edu new_entry = &tlb[x]; 16110196SCurtis.Dunham@arm.com break; 1623388Sgblack@eecs.umich.edu } 1633388Sgblack@eecs.umich.edu }*/ 1643388Sgblack@eecs.umich.edu } 1653388Sgblack@eecs.umich.edu 1663931Ssaidi@eecs.umich.eduinsertAllLocked: 1673792Sgblack@eecs.umich.edu // Update the last ently if their all locked 1683792Sgblack@eecs.umich.edu if (!new_entry) { 1693388Sgblack@eecs.umich.edu new_entry = &tlb[size-1]; 1703766Sgblack@eecs.umich.edu } 1713391Sgblack@eecs.umich.edu 1727741Sgblack@eecs.umich.edu freeList.remove(new_entry); 1734648Sgblack@eecs.umich.edu if (new_entry->valid && new_entry->used) 1748442Sgblack@eecs.umich.edu usedEntries--; 1753391Sgblack@eecs.umich.edu if (new_entry->valid) 1763388Sgblack@eecs.umich.edu lookupTable.erase(new_entry->range); 1773388Sgblack@eecs.umich.edu 1783792Sgblack@eecs.umich.edu 1793388Sgblack@eecs.umich.edu assert(PTE.valid()); 1803792Sgblack@eecs.umich.edu new_entry->range.va = va; 18110196SCurtis.Dunham@arm.com new_entry->range.size = PTE.size() - 1; 1823388Sgblack@eecs.umich.edu new_entry->range.partitionId = partition_id; 1833388Sgblack@eecs.umich.edu new_entry->range.contextId = context_id; 1843388Sgblack@eecs.umich.edu new_entry->range.real = real; 1853792Sgblack@eecs.umich.edu new_entry->pte = PTE; 1863792Sgblack@eecs.umich.edu new_entry->used = true;; 1878442Sgblack@eecs.umich.edu new_entry->valid = true; 1883388Sgblack@eecs.umich.edu usedEntries++; 1897741Sgblack@eecs.umich.edu 1903792Sgblack@eecs.umich.edu 1913388Sgblack@eecs.umich.edu 1923388Sgblack@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1933388Sgblack@eecs.umich.edu assert(i != lookupTable.end()); 1943388Sgblack@eecs.umich.edu 1953388Sgblack@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1967741Sgblack@eecs.umich.edu // one we just inserted 1973388Sgblack@eecs.umich.edu if (usedEntries == size) { 19810196SCurtis.Dunham@arm.com clearUsedBits(); 1993388Sgblack@eecs.umich.edu new_entry->used = true; 2003388Sgblack@eecs.umich.edu usedEntries++; 2013388Sgblack@eecs.umich.edu } 2027741Sgblack@eecs.umich.edu 2037741Sgblack@eecs.umich.edu} 2043439Sgblack@eecs.umich.edu 2053388Sgblack@eecs.umich.edu 2063931Ssaidi@eecs.umich.eduTlbEntry* 2073388Sgblack@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id, bool 2083388Sgblack@eecs.umich.edu update_used) 2093388Sgblack@eecs.umich.edu{ 2103766Sgblack@eecs.umich.edu MapIter i; 2113391Sgblack@eecs.umich.edu TlbRange tr; 2127741Sgblack@eecs.umich.edu TlbEntry *t; 2133391Sgblack@eecs.umich.edu 2143391Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2157741Sgblack@eecs.umich.edu va, partition_id, context_id, real); 2164648Sgblack@eecs.umich.edu // Assemble full address structure 2178442Sgblack@eecs.umich.edu tr.va = va; 2183388Sgblack@eecs.umich.edu tr.size = MachineBytes; 2197741Sgblack@eecs.umich.edu tr.contextId = context_id; 2207741Sgblack@eecs.umich.edu tr.partitionId = partition_id; 2217741Sgblack@eecs.umich.edu tr.real = real; 2223388Sgblack@eecs.umich.edu 2233388Sgblack@eecs.umich.edu // Try to find the entry 2243388Sgblack@eecs.umich.edu i = lookupTable.find(tr); 2253388Sgblack@eecs.umich.edu if (i == lookupTable.end()) { 2263792Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2273388Sgblack@eecs.umich.edu return NULL; 2283792Sgblack@eecs.umich.edu } 22910196SCurtis.Dunham@arm.com 2303388Sgblack@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2313388Sgblack@eecs.umich.edu t = i->second; 2323388Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2333439Sgblack@eecs.umich.edu t->pte.size()); 2343388Sgblack@eecs.umich.edu 2353931Ssaidi@eecs.umich.edu // Update the used bits only if this is a real access (not a fake one from 2363388Sgblack@eecs.umich.edu // virttophys() 2374040Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2383388Sgblack@eecs.umich.edu t->used = true; 2393388Sgblack@eecs.umich.edu usedEntries++; 2403766Sgblack@eecs.umich.edu if (usedEntries == size) { 2413391Sgblack@eecs.umich.edu clearUsedBits(); 2427741Sgblack@eecs.umich.edu t->used = true; 2433391Sgblack@eecs.umich.edu usedEntries++; 2443391Sgblack@eecs.umich.edu } 2457741Sgblack@eecs.umich.edu } 2464648Sgblack@eecs.umich.edu 2478442Sgblack@eecs.umich.edu return t; 2483388Sgblack@eecs.umich.edu} 2493388Sgblack@eecs.umich.edu 2503388Sgblack@eecs.umich.eduvoid 2513792Sgblack@eecs.umich.eduTLB::dumpAll() 2523388Sgblack@eecs.umich.edu{ 2533792Sgblack@eecs.umich.edu MapIter i; 25410196SCurtis.Dunham@arm.com for (int x = 0; x < size; x++) { 2553388Sgblack@eecs.umich.edu if (tlb[x].valid) { 2563388Sgblack@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2573388Sgblack@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2583388Sgblack@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2593388Sgblack@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2603388Sgblack@eecs.umich.edu } 2618342Sksewell@umich.edu } 2628342Sksewell@umich.edu} 26310196SCurtis.Dunham@arm.com 2648342Sksewell@umich.eduvoid 2658342Sksewell@umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2668342Sksewell@umich.edu{ 2678342Sksewell@umich.edu TlbRange tr; 2688342Sksewell@umich.edu MapIter i; 2698342Sksewell@umich.edu 2708342Sksewell@umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2718342Sksewell@umich.edu va, partition_id, context_id, real); 2728342Sksewell@umich.edu 2738342Sksewell@umich.edu cacheValid = false; 2748342Sksewell@umich.edu 2758342Sksewell@umich.edu // Assemble full address structure 2768342Sksewell@umich.edu tr.va = va; 2778342Sksewell@umich.edu tr.size = MachineBytes; 2788342Sksewell@umich.edu tr.contextId = context_id; 2798342Sksewell@umich.edu tr.partitionId = partition_id; 2808342Sksewell@umich.edu tr.real = real; 2818342Sksewell@umich.edu 2828342Sksewell@umich.edu // Demap any entry that conflicts 2838342Sksewell@umich.edu i = lookupTable.find(tr); 2848342Sksewell@umich.edu if (i != lookupTable.end()) { 2858342Sksewell@umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2868342Sksewell@umich.edu i->second->valid = false; 2877741Sgblack@eecs.umich.edu if (i->second->used) { 2883388Sgblack@eecs.umich.edu i->second->used = false; 2893388Sgblack@eecs.umich.edu usedEntries--; 2903388Sgblack@eecs.umich.edu } 2913388Sgblack@eecs.umich.edu freeList.push_front(i->second); 2927741Sgblack@eecs.umich.edu lookupTable.erase(i); 2933388Sgblack@eecs.umich.edu } 2943388Sgblack@eecs.umich.edu} 2953388Sgblack@eecs.umich.edu 2963388Sgblack@eecs.umich.eduvoid 2977741Sgblack@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2983391Sgblack@eecs.umich.edu{ 2993792Sgblack@eecs.umich.edu int x; 3003792Sgblack@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3014040Ssaidi@eecs.umich.edu partition_id, context_id); 3023391Sgblack@eecs.umich.edu cacheValid = false; 3033391Sgblack@eecs.umich.edu for (x = 0; x < size; x++) { 3043391Sgblack@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3057741Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 30610474Sandreas.hansson@arm.com if (tlb[x].valid == true) { 3077741Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 30810474Sandreas.hansson@arm.com } 3093391Sgblack@eecs.umich.edu tlb[x].valid = false; 3103835Sgblack@eecs.umich.edu if (tlb[x].used) { 3117741Sgblack@eecs.umich.edu tlb[x].used = false; 31210474Sandreas.hansson@arm.com usedEntries--; 3137741Sgblack@eecs.umich.edu } 31410474Sandreas.hansson@arm.com lookupTable.erase(tlb[x].range); 3153835Sgblack@eecs.umich.edu } 3163391Sgblack@eecs.umich.edu } 3173391Sgblack@eecs.umich.edu} 3183391Sgblack@eecs.umich.edu 3193391Sgblack@eecs.umich.eduvoid 3208829Sgblack@eecs.umich.eduTLB::demapAll(int partition_id) 3217741Sgblack@eecs.umich.edu{ 3228829Sgblack@eecs.umich.edu int x; 32310474Sandreas.hansson@arm.com DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3248829Sgblack@eecs.umich.edu cacheValid = false; 32510474Sandreas.hansson@arm.com for (x = 0; x < size; x++) { 3263391Sgblack@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3273391Sgblack@eecs.umich.edu if (tlb[x].valid == true){ 3284648Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3298795Sgblack@eecs.umich.edu } 3308829Sgblack@eecs.umich.edu tlb[x].valid = false; 3314648Sgblack@eecs.umich.edu if (tlb[x].used) { 3323391Sgblack@eecs.umich.edu tlb[x].used = false; 3333391Sgblack@eecs.umich.edu usedEntries--; 3347741Sgblack@eecs.umich.edu } 3357741Sgblack@eecs.umich.edu lookupTable.erase(tlb[x].range); 3363391Sgblack@eecs.umich.edu } 3373391Sgblack@eecs.umich.edu } 3383616Sgblack@eecs.umich.edu} 3393391Sgblack@eecs.umich.edu 3403391Sgblack@eecs.umich.eduvoid 3417741Sgblack@eecs.umich.eduTLB::invalidateAll() 3427741Sgblack@eecs.umich.edu{ 3437741Sgblack@eecs.umich.edu int x; 3447741Sgblack@eecs.umich.edu cacheValid = false; 3457741Sgblack@eecs.umich.edu 3463388Sgblack@eecs.umich.edu freeList.clear(); 3473949Sgblack@eecs.umich.edu lookupTable.clear(); 3483810Sgblack@eecs.umich.edu for (x = 0; x < size; x++) { 3493792Sgblack@eecs.umich.edu if (tlb[x].valid == true) 3503792Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 3513792Sgblack@eecs.umich.edu tlb[x].valid = false; 3523439Sgblack@eecs.umich.edu tlb[x].used = false; 3533439Sgblack@eecs.umich.edu } 3544040Ssaidi@eecs.umich.edu usedEntries = 0; 3553810Sgblack@eecs.umich.edu} 3563388Sgblack@eecs.umich.edu 3573388Sgblack@eecs.umich.eduuint64_t 3583388Sgblack@eecs.umich.eduTLB::TteRead(int entry) { 3593388Sgblack@eecs.umich.edu if (entry >= size) 3604040Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3614648Sgblack@eecs.umich.edu 3624648Sgblack@eecs.umich.edu assert(entry < size); 3633792Sgblack@eecs.umich.edu if (tlb[entry].valid) 3643810Sgblack@eecs.umich.edu return tlb[entry].pte(); 3653388Sgblack@eecs.umich.edu else 3663388Sgblack@eecs.umich.edu return (uint64_t)-1ll; 367} 368 369uint64_t 370TLB::TagRead(int entry) { 371 assert(entry < size); 372 uint64_t tag; 373 if (!tlb[entry].valid) 374 return (uint64_t)-1ll; 375 376 tag = tlb[entry].range.contextId; 377 tag |= tlb[entry].range.va; 378 tag |= (uint64_t)tlb[entry].range.partitionId << 61; 379 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 380 tag |= (uint64_t)~tlb[entry].pte._size() << 56; 381 return tag; 382} 383 384bool 385TLB::validVirtualAddress(Addr va, bool am) 386{ 387 if (am) 388 return true; 389 if (va >= StartVAddrHole && va <= EndVAddrHole) 390 return false; 391 return true; 392} 393 394void 395TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 396 bool se, FaultTypes ft, int asi) 397{ 398 uint64_t sfsr; 399 sfsr = tc->readMiscRegNoEffect(reg); 400 401 if (sfsr & 0x1) 402 sfsr = 0x3; 403 else 404 sfsr = 1; 405 406 if (write) 407 sfsr |= 1 << 2; 408 sfsr |= ct << 4; 409 if (se) 410 sfsr |= 1 << 6; 411 sfsr |= ft << 7; 412 sfsr |= asi << 16; 413 tc->setMiscReg(reg, sfsr); 414} 415 416void 417TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 418{ 419 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 420 va, context, mbits(va, 63,13) | mbits(context,12,0)); 421 422 tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0)); 423} 424 425void 426ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 427 bool se, FaultTypes ft, int asi) 428{ 429 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 430 (int)write, ct, ft, asi); 431 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 432} 433 434void 435ITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 436{ 437 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 438} 439 440void 441DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 442 bool se, FaultTypes ft, int asi) 443{ 444 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 445 a, (int)write, ct, ft, asi); 446 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 447 tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); 448} 449 450void 451DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 452{ 453 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 454} 455 456 457 458Fault 459ITB::translate(RequestPtr &req, ThreadContext *tc) 460{ 461 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 462 463 Addr vaddr = req->getVaddr(); 464 TlbEntry *e; 465 466 assert(req->getAsi() == ASI_IMPLICIT); 467 468 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 469 vaddr, req->getSize()); 470 471 // Be fast if we can! 472 if (cacheValid && cacheState == tlbdata) { 473 if (cacheEntry) { 474 if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 475 cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 476 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 477 vaddr & cacheEntry->pte.size()-1 ); 478 return NoFault; 479 } 480 } else { 481 req->setPaddr(vaddr & PAddrImplMask); 482 return NoFault; 483 } 484 } 485 486 bool hpriv = bits(tlbdata,0,0); 487 bool red = bits(tlbdata,1,1); 488 bool priv = bits(tlbdata,2,2); 489 bool addr_mask = bits(tlbdata,3,3); 490 bool lsu_im = bits(tlbdata,4,4); 491 492 int part_id = bits(tlbdata,15,8); 493 int tl = bits(tlbdata,18,16); 494 int pri_context = bits(tlbdata,47,32); 495 int context; 496 ContextType ct; 497 int asi; 498 bool real = false; 499 500 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 501 priv, hpriv, red, lsu_im, part_id); 502 503 if (tl > 0) { 504 asi = ASI_N; 505 ct = Nucleus; 506 context = 0; 507 } else { 508 asi = ASI_P; 509 ct = Primary; 510 context = pri_context; 511 } 512 513 if ( hpriv || red ) { 514 cacheValid = true; 515 cacheState = tlbdata; 516 cacheEntry = NULL; 517 req->setPaddr(vaddr & PAddrImplMask); 518 return NoFault; 519 } 520 521 // If the access is unaligned trap 522 if (vaddr & 0x3) { 523 writeSfsr(tc, false, ct, false, OtherFault, asi); 524 return new MemAddressNotAligned; 525 } 526 527 if (addr_mask) 528 vaddr = vaddr & VAddrAMask; 529 530 if (!validVirtualAddress(vaddr, addr_mask)) { 531 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 532 return new InstructionAccessException; 533 } 534 535 if (!lsu_im) { 536 e = lookup(vaddr, part_id, true); 537 real = true; 538 context = 0; 539 } else { 540 e = lookup(vaddr, part_id, false, context); 541 } 542 543 if (e == NULL || !e->valid) { 544 writeTagAccess(tc, vaddr, context); 545 if (real) 546 return new InstructionRealTranslationMiss; 547 else 548 return new FastInstructionAccessMMUMiss; 549 } 550 551 // were not priviledged accesing priv page 552 if (!priv && e->pte.priv()) { 553 writeTagAccess(tc, vaddr, context); 554 writeSfsr(tc, false, ct, false, PrivViolation, asi); 555 return new InstructionAccessException; 556 } 557 558 // cache translation date for next translation 559 cacheValid = true; 560 cacheState = tlbdata; 561 cacheEntry = e; 562 563 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 564 vaddr & e->pte.size()-1 ); 565 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 566 return NoFault; 567} 568 569 570 571Fault 572DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 573{ 574 /* @todo this could really use some profiling and fixing to make it faster! */ 575 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 576 Addr vaddr = req->getVaddr(); 577 Addr size = req->getSize(); 578 ASI asi; 579 asi = (ASI)req->getAsi(); 580 bool implicit = false; 581 bool hpriv = bits(tlbdata,0,0); 582 583 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 584 vaddr, size, asi); 585 586 if (lookupTable.size() != 64 - freeList.size()) 587 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 588 freeList.size()); 589 if (asi == ASI_IMPLICIT) 590 implicit = true; 591 592 if (hpriv && implicit) { 593 req->setPaddr(vaddr & PAddrImplMask); 594 return NoFault; 595 } 596 597 // Be fast if we can! 598 if (cacheValid && cacheState == tlbdata) { 599 600 601 602 if (cacheEntry[0]) { 603 TlbEntry *ce = cacheEntry[0]; 604 Addr ce_va = ce->range.va; 605 if (cacheAsi[0] == asi && 606 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 607 (!write || ce->pte.writable())) { 608 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 609 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 610 req->setFlags(req->getFlags() | UNCACHEABLE); 611 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 612 return NoFault; 613 } // if matched 614 } // if cache entry valid 615 if (cacheEntry[1]) { 616 TlbEntry *ce = cacheEntry[1]; 617 Addr ce_va = ce->range.va; 618 if (cacheAsi[1] == asi && 619 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 620 (!write || ce->pte.writable())) { 621 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 622 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 623 req->setFlags(req->getFlags() | UNCACHEABLE); 624 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 625 return NoFault; 626 } // if matched 627 } // if cache entry valid 628 } 629 630 bool red = bits(tlbdata,1,1); 631 bool priv = bits(tlbdata,2,2); 632 bool addr_mask = bits(tlbdata,3,3); 633 bool lsu_dm = bits(tlbdata,5,5); 634 635 int part_id = bits(tlbdata,15,8); 636 int tl = bits(tlbdata,18,16); 637 int pri_context = bits(tlbdata,47,32); 638 int sec_context = bits(tlbdata,63,48); 639 640 bool real = false; 641 ContextType ct = Primary; 642 int context = 0; 643 644 TlbEntry *e; 645 646 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 647 priv, hpriv, red, lsu_dm, part_id); 648 649 if (implicit) { 650 if (tl > 0) { 651 asi = ASI_N; 652 ct = Nucleus; 653 context = 0; 654 } else { 655 asi = ASI_P; 656 ct = Primary; 657 context = pri_context; 658 } 659 } else { 660 // We need to check for priv level/asi priv 661 if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 662 // It appears that context should be Nucleus in these cases? 663 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 664 return new PrivilegedAction; 665 } 666 667 if (!hpriv && AsiIsHPriv(asi)) { 668 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 669 return new DataAccessException; 670 } 671 672 if (AsiIsPrimary(asi)) { 673 context = pri_context; 674 ct = Primary; 675 } else if (AsiIsSecondary(asi)) { 676 context = sec_context; 677 ct = Secondary; 678 } else if (AsiIsNucleus(asi)) { 679 ct = Nucleus; 680 context = 0; 681 } else { // ???? 682 ct = Primary; 683 context = pri_context; 684 } 685 } 686 687 if (!implicit && asi != ASI_P && asi != ASI_S) { 688 if (AsiIsLittle(asi)) 689 panic("Little Endian ASIs not supported\n"); 690 if (AsiIsNoFault(asi)) 691 panic("No Fault ASIs not supported\n"); 692 693 if (AsiIsPartialStore(asi)) 694 panic("Partial Store ASIs not supported\n"); 695 696 if (AsiIsInterrupt(asi)) 697 goto handleIntRegAccess; 698 if (AsiIsMmu(asi)) 699 goto handleMmuRegAccess; 700 if (AsiIsScratchPad(asi)) 701 goto handleScratchRegAccess; 702 if (AsiIsQueue(asi)) 703 goto handleQueueRegAccess; 704 if (AsiIsSparcError(asi)) 705 goto handleSparcErrorRegAccess; 706 707 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 708 !AsiIsTwin(asi) && !AsiIsBlock(asi)) 709 panic("Accessing ASI %#X. Should we?\n", asi); 710 } 711 712 // If the asi is unaligned trap 713 if (vaddr & size-1) { 714 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 715 return new MemAddressNotAligned; 716 } 717 718 if (addr_mask) 719 vaddr = vaddr & VAddrAMask; 720 721 if (!validVirtualAddress(vaddr, addr_mask)) { 722 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 723 return new DataAccessException; 724 } 725 726 727 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 728 real = true; 729 context = 0; 730 }; 731 732 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 733 req->setPaddr(vaddr & PAddrImplMask); 734 return NoFault; 735 } 736 737 e = lookup(vaddr, part_id, real, context); 738 739 if (e == NULL || !e->valid) { 740 writeTagAccess(tc, vaddr, context); 741 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 742 if (real) 743 return new DataRealTranslationMiss; 744 else 745 return new FastDataAccessMMUMiss; 746 747 } 748 749 if (!priv && e->pte.priv()) { 750 writeTagAccess(tc, vaddr, context); 751 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 752 return new DataAccessException; 753 } 754 755 if (write && !e->pte.writable()) { 756 writeTagAccess(tc, vaddr, context); 757 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 758 return new FastDataAccessProtection; 759 } 760 761 if (e->pte.nofault() && !AsiIsNoFault(asi)) { 762 writeTagAccess(tc, vaddr, context); 763 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 764 return new DataAccessException; 765 } 766 767 if (e->pte.sideffect() && AsiIsNoFault(asi)) { 768 writeTagAccess(tc, vaddr, context); 769 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 770 return new DataAccessException; 771 } 772 773 774 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 775 req->setFlags(req->getFlags() | UNCACHEABLE); 776 777 // cache translation date for next translation 778 cacheState = tlbdata; 779 if (!cacheValid) { 780 cacheEntry[1] = NULL; 781 cacheEntry[0] = NULL; 782 } 783 784 if (cacheEntry[0] != e && cacheEntry[1] != e) { 785 cacheEntry[1] = cacheEntry[0]; 786 cacheEntry[0] = e; 787 cacheAsi[1] = cacheAsi[0]; 788 cacheAsi[0] = asi; 789 if (implicit) 790 cacheAsi[0] = (ASI)0; 791 } 792 cacheValid = true; 793 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 794 vaddr & e->pte.size()-1); 795 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 796 return NoFault; 797 798 /** Normal flow ends here. */ 799handleIntRegAccess: 800 if (!hpriv) { 801 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 802 if (priv) 803 return new DataAccessException; 804 else 805 return new PrivilegedAction; 806 } 807 808 if (asi == ASI_SWVR_UDB_INTR_W && !write || 809 asi == ASI_SWVR_UDB_INTR_R && write) { 810 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 811 return new DataAccessException; 812 } 813 814 goto regAccessOk; 815 816 817handleScratchRegAccess: 818 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 819 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 820 return new DataAccessException; 821 } 822 goto regAccessOk; 823 824handleQueueRegAccess: 825 if (!priv && !hpriv) { 826 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 827 return new PrivilegedAction; 828 } 829 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 830 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 831 return new DataAccessException; 832 } 833 goto regAccessOk; 834 835handleSparcErrorRegAccess: 836 if (!hpriv) { 837 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 838 if (priv) 839 return new DataAccessException; 840 else 841 return new PrivilegedAction; 842 } 843 goto regAccessOk; 844 845 846regAccessOk: 847handleMmuRegAccess: 848 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 849 req->setMmapedIpr(true); 850 req->setPaddr(req->getVaddr()); 851 return NoFault; 852}; 853 854Tick 855DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 856{ 857 Addr va = pkt->getAddr(); 858 ASI asi = (ASI)pkt->req->getAsi(); 859 uint64_t temp; 860 861 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 862 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 863 864 switch (asi) { 865 case ASI_LSU_CONTROL_REG: 866 assert(va == 0); 867 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 868 break; 869 case ASI_MMU: 870 switch (va) { 871 case 0x8: 872 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 873 break; 874 case 0x10: 875 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 876 break; 877 default: 878 goto doMmuReadError; 879 } 880 break; 881 case ASI_QUEUE: 882 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 883 (va >> 4) - 0x3c)); 884 break; 885 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 886 assert(va == 0); 887 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0)); 888 break; 889 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 890 assert(va == 0); 891 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1)); 892 break; 893 case ASI_DMMU_CTXT_ZERO_CONFIG: 894 assert(va == 0); 895 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG)); 896 break; 897 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 898 assert(va == 0); 899 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0)); 900 break; 901 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 902 assert(va == 0); 903 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1)); 904 break; 905 case ASI_IMMU_CTXT_ZERO_CONFIG: 906 assert(va == 0); 907 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG)); 908 break; 909 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 910 assert(va == 0); 911 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0)); 912 break; 913 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 914 assert(va == 0); 915 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1)); 916 break; 917 case ASI_DMMU_CTXT_NONZERO_CONFIG: 918 assert(va == 0); 919 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); 920 break; 921 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 922 assert(va == 0); 923 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0)); 924 break; 925 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 926 assert(va == 0); 927 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1)); 928 break; 929 case ASI_IMMU_CTXT_NONZERO_CONFIG: 930 assert(va == 0); 931 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); 932 break; 933 case ASI_SPARC_ERROR_STATUS_REG: 934 pkt->set((uint64_t)0); 935 break; 936 case ASI_HYP_SCRATCHPAD: 937 case ASI_SCRATCHPAD: 938 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 939 break; 940 case ASI_IMMU: 941 switch (va) { 942 case 0x0: 943 temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); 944 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 945 break; 946 case 0x18: 947 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR)); 948 break; 949 case 0x30: 950 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS)); 951 break; 952 default: 953 goto doMmuReadError; 954 } 955 break; 956 case ASI_DMMU: 957 switch (va) { 958 case 0x0: 959 temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); 960 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 961 break; 962 case 0x18: 963 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR)); 964 break; 965 case 0x20: 966 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR)); 967 break; 968 case 0x30: 969 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS)); 970 break; 971 case 0x80: 972 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 973 break; 974 default: 975 goto doMmuReadError; 976 } 977 break; 978 case ASI_DMMU_TSB_PS0_PTR_REG: 979 pkt->set(MakeTsbPtr(Ps0, 980 tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), 981 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), 982 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 983 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), 984 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); 985 break; 986 case ASI_DMMU_TSB_PS1_PTR_REG: 987 pkt->set(MakeTsbPtr(Ps1, 988 tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), 989 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), 990 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 991 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), 992 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); 993 break; 994 case ASI_IMMU_TSB_PS0_PTR_REG: 995 pkt->set(MakeTsbPtr(Ps0, 996 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), 997 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), 998 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 999 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), 1000 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); 1001 break; 1002 case ASI_IMMU_TSB_PS1_PTR_REG: 1003 pkt->set(MakeTsbPtr(Ps1, 1004 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), 1005 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), 1006 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 1007 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), 1008 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); 1009 break; 1010 case ASI_SWVR_INTR_RECEIVE: 1011 pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 1012 break; 1013 case ASI_SWVR_UDB_INTR_R: 1014 temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 1015 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); 1016 pkt->set(temp); 1017 break; 1018 default: 1019doMmuReadError: 1020 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 1021 (uint32_t)asi, va); 1022 } 1023 pkt->result = Packet::Success; 1024 return tc->getCpuPtr()->cycles(1); 1025} 1026 1027Tick 1028DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1029{ 1030 uint64_t data = gtoh(pkt->get<uint64_t>()); 1031 Addr va = pkt->getAddr(); 1032 ASI asi = (ASI)pkt->req->getAsi(); 1033 1034 Addr ta_insert; 1035 Addr va_insert; 1036 Addr ct_insert; 1037 int part_insert; 1038 int entry_insert = -1; 1039 bool real_insert; 1040 bool ignore; 1041 int part_id; 1042 int ctx_id; 1043 PageTableEntry pte; 1044 1045 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1046 (uint32_t)asi, va, data); 1047 1048 switch (asi) { 1049 case ASI_LSU_CONTROL_REG: 1050 assert(va == 0); 1051 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 1052 break; 1053 case ASI_MMU: 1054 switch (va) { 1055 case 0x8: 1056 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 1057 break; 1058 case 0x10: 1059 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 1060 break; 1061 default: 1062 goto doMmuWriteError; 1063 } 1064 break; 1065 case ASI_QUEUE: 1066 assert(mbits(data,13,6) == data); 1067 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 1068 (va >> 4) - 0x3c, data); 1069 break; 1070 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1071 assert(va == 0); 1072 tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 1073 break; 1074 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1075 assert(va == 0); 1076 tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 1077 break; 1078 case ASI_DMMU_CTXT_ZERO_CONFIG: 1079 assert(va == 0); 1080 tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data); 1081 break; 1082 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1083 assert(va == 0); 1084 tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 1085 break; 1086 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1087 assert(va == 0); 1088 tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 1089 break; 1090 case ASI_IMMU_CTXT_ZERO_CONFIG: 1091 assert(va == 0); 1092 tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data); 1093 break; 1094 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1095 assert(va == 0); 1096 tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 1097 break; 1098 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1099 assert(va == 0); 1100 tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 1101 break; 1102 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1103 assert(va == 0); 1104 tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data); 1105 break; 1106 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1107 assert(va == 0); 1108 tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 1109 break; 1110 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1111 assert(va == 0); 1112 tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 1113 break; 1114 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1115 assert(va == 0); 1116 tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data); 1117 break; 1118 case ASI_SPARC_ERROR_EN_REG: 1119 case ASI_SPARC_ERROR_STATUS_REG: 1120 warn("Ignoring write to SPARC ERROR regsiter\n"); 1121 break; 1122 case ASI_HYP_SCRATCHPAD: 1123 case ASI_SCRATCHPAD: 1124 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1125 break; 1126 case ASI_IMMU: 1127 switch (va) { 1128 case 0x18: 1129 tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data); 1130 break; 1131 case 0x30: 1132 sext<59>(bits(data, 59,0)); 1133 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data); 1134 break; 1135 default: 1136 goto doMmuWriteError; 1137 } 1138 break; 1139 case ASI_ITLB_DATA_ACCESS_REG: 1140 entry_insert = bits(va, 8,3); 1141 case ASI_ITLB_DATA_IN_REG: 1142 assert(entry_insert != -1 || mbits(va,10,9) == va); 1143 ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); 1144 va_insert = mbits(ta_insert, 63,13); 1145 ct_insert = mbits(ta_insert, 12,0); 1146 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1147 real_insert = bits(va, 9,9); 1148 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1149 PageTableEntry::sun4u); 1150 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1151 pte, entry_insert); 1152 break; 1153 case ASI_DTLB_DATA_ACCESS_REG: 1154 entry_insert = bits(va, 8,3); 1155 case ASI_DTLB_DATA_IN_REG: 1156 assert(entry_insert != -1 || mbits(va,10,9) == va); 1157 ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); 1158 va_insert = mbits(ta_insert, 63,13); 1159 ct_insert = mbits(ta_insert, 12,0); 1160 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1161 real_insert = bits(va, 9,9); 1162 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1163 PageTableEntry::sun4u); 1164 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 1165 break; 1166 case ASI_IMMU_DEMAP: 1167 ignore = false; 1168 ctx_id = -1; 1169 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1170 switch (bits(va,5,4)) { 1171 case 0: 1172 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1173 break; 1174 case 1: 1175 ignore = true; 1176 break; 1177 case 3: 1178 ctx_id = 0; 1179 break; 1180 default: 1181 ignore = true; 1182 } 1183 1184 switch(bits(va,7,6)) { 1185 case 0: // demap page 1186 if (!ignore) 1187 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1188 bits(va,9,9), ctx_id); 1189 break; 1190 case 1: //demap context 1191 if (!ignore) 1192 tc->getITBPtr()->demapContext(part_id, ctx_id); 1193 break; 1194 case 2: 1195 tc->getITBPtr()->demapAll(part_id); 1196 break; 1197 default: 1198 panic("Invalid type for IMMU demap\n"); 1199 } 1200 break; 1201 case ASI_DMMU: 1202 switch (va) { 1203 case 0x18: 1204 tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data); 1205 break; 1206 case 0x30: 1207 sext<59>(bits(data, 59,0)); 1208 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data); 1209 break; 1210 case 0x80: 1211 tc->setMiscReg(MISCREG_MMU_PART_ID, data); 1212 break; 1213 default: 1214 goto doMmuWriteError; 1215 } 1216 break; 1217 case ASI_DMMU_DEMAP: 1218 ignore = false; 1219 ctx_id = -1; 1220 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1221 switch (bits(va,5,4)) { 1222 case 0: 1223 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1224 break; 1225 case 1: 1226 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 1227 break; 1228 case 3: 1229 ctx_id = 0; 1230 break; 1231 default: 1232 ignore = true; 1233 } 1234 1235 switch(bits(va,7,6)) { 1236 case 0: // demap page 1237 if (!ignore) 1238 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1239 break; 1240 case 1: //demap context 1241 if (!ignore) 1242 demapContext(part_id, ctx_id); 1243 break; 1244 case 2: 1245 demapAll(part_id); 1246 break; 1247 default: 1248 panic("Invalid type for IMMU demap\n"); 1249 } 1250 break; 1251 case ASI_SWVR_INTR_RECEIVE: 1252 int msb; 1253 // clear all the interrupts that aren't set in the write 1254 while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) { 1255 msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data); 1256 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); 1257 } 1258 break; 1259 case ASI_SWVR_UDB_INTR_W: 1260 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 1261 post_interrupt(bits(data,5,0),0); 1262 break; 1263 default: 1264doMmuWriteError: 1265 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 1266 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 1267 } 1268 pkt->result = Packet::Success; 1269 return tc->getCpuPtr()->cycles(1); 1270} 1271 1272void 1273DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1274{ 1275 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 1276 ptrs[0] = MakeTsbPtr(Ps0, tag_access, 1277 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), 1278 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 1279 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), 1280 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); 1281 ptrs[1] = MakeTsbPtr(Ps1, tag_access, 1282 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), 1283 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 1284 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), 1285 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); 1286 ptrs[2] = MakeTsbPtr(Ps0, tag_access, 1287 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), 1288 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 1289 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), 1290 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); 1291 ptrs[3] = MakeTsbPtr(Ps1, tag_access, 1292 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), 1293 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 1294 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), 1295 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); 1296} 1297 1298 1299 1300 1301 1302uint64_t 1303DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1304 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 1305{ 1306 uint64_t tsb; 1307 uint64_t config; 1308 1309 if (bits(tag_access, 12,0) == 0) { 1310 tsb = c0_tsb; 1311 config = c0_config; 1312 } else { 1313 tsb = cX_tsb; 1314 config = cX_config; 1315 } 1316 1317 uint64_t ptr = mbits(tsb,63,13); 1318 bool split = bits(tsb,12,12); 1319 int tsb_size = bits(tsb,3,0); 1320 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 1321 1322 if (ps == Ps1 && split) 1323 ptr |= ULL(1) << (13 + tsb_size); 1324 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 1325 1326 return ptr; 1327} 1328 1329 1330void 1331TLB::serialize(std::ostream &os) 1332{ 1333 SERIALIZE_SCALAR(size); 1334 SERIALIZE_SCALAR(usedEntries); 1335 SERIALIZE_SCALAR(lastReplaced); 1336 1337 // convert the pointer based free list into an index based one 1338 int *free_list = (int*)malloc(sizeof(int) * size); 1339 int cntr = 0; 1340 std::list<TlbEntry*>::iterator i; 1341 i = freeList.begin(); 1342 while (i != freeList.end()) { 1343 free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 1344 i++; 1345 } 1346 SERIALIZE_SCALAR(cntr); 1347 SERIALIZE_ARRAY(free_list, cntr); 1348 1349 for (int x = 0; x < size; x++) { 1350 nameOut(os, csprintf("%s.PTE%d", name(), x)); 1351 tlb[x].serialize(os); 1352 } 1353} 1354 1355void 1356TLB::unserialize(Checkpoint *cp, const std::string §ion) 1357{ 1358 int oldSize; 1359 1360 paramIn(cp, section, "size", oldSize); 1361 if (oldSize != size) 1362 panic("Don't support unserializing different sized TLBs\n"); 1363 UNSERIALIZE_SCALAR(usedEntries); 1364 UNSERIALIZE_SCALAR(lastReplaced); 1365 1366 int cntr; 1367 UNSERIALIZE_SCALAR(cntr); 1368 1369 int *free_list = (int*)malloc(sizeof(int) * cntr); 1370 freeList.clear(); 1371 UNSERIALIZE_ARRAY(free_list, cntr); 1372 for (int x = 0; x < cntr; x++) 1373 freeList.push_back(&tlb[free_list[x]]); 1374 1375 lookupTable.clear(); 1376 for (int x = 0; x < size; x++) { 1377 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1378 if (tlb[x].valid) 1379 lookupTable.insert(tlb[x].range, &tlb[x]); 1380 1381 } 1382} 1383 1384/* end namespace SparcISA */ } 1385 1386using namespace SparcISA; 1387 1388DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 1389 1390BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 1391 1392 Param<int> size; 1393 1394END_DECLARE_SIM_OBJECT_PARAMS(ITB) 1395 1396BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 1397 1398 INIT_PARAM_DFLT(size, "TLB size", 48) 1399 1400END_INIT_SIM_OBJECT_PARAMS(ITB) 1401 1402 1403CREATE_SIM_OBJECT(ITB) 1404{ 1405 return new ITB(getInstanceName(), size); 1406} 1407 1408REGISTER_SIM_OBJECT("SparcITB", ITB) 1409 1410BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 1411 1412 Param<int> size; 1413 1414END_DECLARE_SIM_OBJECT_PARAMS(DTB) 1415 1416BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 1417 1418 INIT_PARAM_DFLT(size, "TLB size", 64) 1419 1420END_INIT_SIM_OBJECT_PARAMS(DTB) 1421 1422 1423CREATE_SIM_OBJECT(DTB) 1424{ 1425 return new DTB(getInstanceName(), size); 1426} 1427 1428REGISTER_SIM_OBJECT("SparcDTB", DTB) 1429