tlb.cc revision 4103
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 423569Sgblack@eecs.umich.edu#include "sim/builder.hh" 434103Ssaidi@eecs.umich.edu#include "sim/system.hh" 443569Sgblack@eecs.umich.edu 453804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 463804Ssaidi@eecs.umich.edu * */ 474088Sbinkertn@umich.edunamespace SparcISA { 483569Sgblack@eecs.umich.edu 493804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 503881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 513881Ssaidi@eecs.umich.edu cacheValid(false) 523804Ssaidi@eecs.umich.edu{ 533804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 543804Ssaidi@eecs.umich.edu if (size > 64) 553804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 563569Sgblack@eecs.umich.edu 573804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 583918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 593881Ssaidi@eecs.umich.edu 603881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 613881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 623804Ssaidi@eecs.umich.edu} 633569Sgblack@eecs.umich.edu 643804Ssaidi@eecs.umich.eduvoid 653804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 663804Ssaidi@eecs.umich.edu{ 673804Ssaidi@eecs.umich.edu MapIter i; 683881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 693804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 703804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 713804Ssaidi@eecs.umich.edu t->used = false; 723804Ssaidi@eecs.umich.edu usedEntries--; 733804Ssaidi@eecs.umich.edu } 743804Ssaidi@eecs.umich.edu } 753804Ssaidi@eecs.umich.edu} 763569Sgblack@eecs.umich.edu 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.eduvoid 793804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 803826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 813804Ssaidi@eecs.umich.edu{ 823569Sgblack@eecs.umich.edu 833569Sgblack@eecs.umich.edu 843804Ssaidi@eecs.umich.edu MapIter i; 853826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 863907Ssaidi@eecs.umich.edu// TlbRange tr; 873826Ssaidi@eecs.umich.edu int x; 883811Ssaidi@eecs.umich.edu 893836Ssaidi@eecs.umich.edu cacheValid = false; 903915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 913907Ssaidi@eecs.umich.edu /* tr.va = va; 923881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 933881Ssaidi@eecs.umich.edu tr.contextId = context_id; 943881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 953881Ssaidi@eecs.umich.edu tr.real = real; 963907Ssaidi@eecs.umich.edu*/ 973881Ssaidi@eecs.umich.edu 983881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 993881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1003881Ssaidi@eecs.umich.edu 1013881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1023907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1033907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1043907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1053907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1063907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1073907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1083907Ssaidi@eecs.umich.edu { 1093907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1103907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1113907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1123907Ssaidi@eecs.umich.edu 1133907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1143907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1153907Ssaidi@eecs.umich.edu tlb[x].used = false; 1163907Ssaidi@eecs.umich.edu usedEntries--; 1173907Ssaidi@eecs.umich.edu } 1183907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1193907Ssaidi@eecs.umich.edu } 1203907Ssaidi@eecs.umich.edu } 1213907Ssaidi@eecs.umich.edu } 1223907Ssaidi@eecs.umich.edu 1233907Ssaidi@eecs.umich.edu 1243907Ssaidi@eecs.umich.edu/* 1253881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1263881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1273881Ssaidi@eecs.umich.edu i->second->valid = false; 1283881Ssaidi@eecs.umich.edu if (i->second->used) { 1293881Ssaidi@eecs.umich.edu i->second->used = false; 1303881Ssaidi@eecs.umich.edu usedEntries--; 1313881Ssaidi@eecs.umich.edu } 1323881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1333881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1343881Ssaidi@eecs.umich.edu i->second); 1353881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1363881Ssaidi@eecs.umich.edu } 1373907Ssaidi@eecs.umich.edu*/ 1383811Ssaidi@eecs.umich.edu 1393826Ssaidi@eecs.umich.edu if (entry != -1) { 1403826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1413826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1423826Ssaidi@eecs.umich.edu } else { 1433881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1443881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1453881Ssaidi@eecs.umich.edu } else { 1463881Ssaidi@eecs.umich.edu x = lastReplaced; 1473881Ssaidi@eecs.umich.edu do { 1483881Ssaidi@eecs.umich.edu ++x; 1493881Ssaidi@eecs.umich.edu if (x == size) 1503881Ssaidi@eecs.umich.edu x = 0; 1513881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1523881Ssaidi@eecs.umich.edu goto insertAllLocked; 1533881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1543881Ssaidi@eecs.umich.edu lastReplaced = x; 1553881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1563881Ssaidi@eecs.umich.edu } 1573881Ssaidi@eecs.umich.edu /* 1583826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1593826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1603826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1613826Ssaidi@eecs.umich.edu break; 1623826Ssaidi@eecs.umich.edu } 1633881Ssaidi@eecs.umich.edu }*/ 1643569Sgblack@eecs.umich.edu } 1653569Sgblack@eecs.umich.edu 1663881Ssaidi@eecs.umich.eduinsertAllLocked: 1673804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1683881Ssaidi@eecs.umich.edu if (!new_entry) { 1693826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1703881Ssaidi@eecs.umich.edu } 1713881Ssaidi@eecs.umich.edu 1723881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1733907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1743907Ssaidi@eecs.umich.edu usedEntries--; 1753929Ssaidi@eecs.umich.edu if (new_entry->valid) 1763929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1773907Ssaidi@eecs.umich.edu 1783907Ssaidi@eecs.umich.edu 1793804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1803804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1813881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1823804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1833804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1843804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1853804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1863804Ssaidi@eecs.umich.edu new_entry->used = true;; 1873804Ssaidi@eecs.umich.edu new_entry->valid = true; 1883804Ssaidi@eecs.umich.edu usedEntries++; 1893569Sgblack@eecs.umich.edu 1903569Sgblack@eecs.umich.edu 1913569Sgblack@eecs.umich.edu 1923863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1933863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1943804Ssaidi@eecs.umich.edu 1953804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1963804Ssaidi@eecs.umich.edu // one we just inserted 1973804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1983804Ssaidi@eecs.umich.edu clearUsedBits(); 1993804Ssaidi@eecs.umich.edu new_entry->used = true; 2003804Ssaidi@eecs.umich.edu usedEntries++; 2013804Ssaidi@eecs.umich.edu } 2023804Ssaidi@eecs.umich.edu 2033569Sgblack@eecs.umich.edu} 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.edu 2063804Ssaidi@eecs.umich.eduTlbEntry* 2074070Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id, bool 2084070Ssaidi@eecs.umich.edu update_used) 2093804Ssaidi@eecs.umich.edu{ 2103804Ssaidi@eecs.umich.edu MapIter i; 2113804Ssaidi@eecs.umich.edu TlbRange tr; 2123804Ssaidi@eecs.umich.edu TlbEntry *t; 2133804Ssaidi@eecs.umich.edu 2143811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2153811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2163804Ssaidi@eecs.umich.edu // Assemble full address structure 2173804Ssaidi@eecs.umich.edu tr.va = va; 2183863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2193804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2203804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2213804Ssaidi@eecs.umich.edu tr.real = real; 2223804Ssaidi@eecs.umich.edu 2233804Ssaidi@eecs.umich.edu // Try to find the entry 2243804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2253804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2263811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2273804Ssaidi@eecs.umich.edu return NULL; 2283804Ssaidi@eecs.umich.edu } 2293804Ssaidi@eecs.umich.edu 2303804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2313804Ssaidi@eecs.umich.edu t = i->second; 2323826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2333826Ssaidi@eecs.umich.edu t->pte.size()); 2344070Ssaidi@eecs.umich.edu 2354070Ssaidi@eecs.umich.edu // Update the used bits only if this is a real access (not a fake one from 2364070Ssaidi@eecs.umich.edu // virttophys() 2374070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2383804Ssaidi@eecs.umich.edu t->used = true; 2393804Ssaidi@eecs.umich.edu usedEntries++; 2403804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2413804Ssaidi@eecs.umich.edu clearUsedBits(); 2423804Ssaidi@eecs.umich.edu t->used = true; 2433804Ssaidi@eecs.umich.edu usedEntries++; 2443804Ssaidi@eecs.umich.edu } 2453804Ssaidi@eecs.umich.edu } 2463804Ssaidi@eecs.umich.edu 2473804Ssaidi@eecs.umich.edu return t; 2483804Ssaidi@eecs.umich.edu} 2493804Ssaidi@eecs.umich.edu 2503826Ssaidi@eecs.umich.eduvoid 2513826Ssaidi@eecs.umich.eduTLB::dumpAll() 2523826Ssaidi@eecs.umich.edu{ 2533863Ssaidi@eecs.umich.edu MapIter i; 2543826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2553826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2563826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2573826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2583826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2593826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2603826Ssaidi@eecs.umich.edu } 2613826Ssaidi@eecs.umich.edu } 2623826Ssaidi@eecs.umich.edu} 2633804Ssaidi@eecs.umich.edu 2643804Ssaidi@eecs.umich.eduvoid 2653804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2663804Ssaidi@eecs.umich.edu{ 2673804Ssaidi@eecs.umich.edu TlbRange tr; 2683804Ssaidi@eecs.umich.edu MapIter i; 2693804Ssaidi@eecs.umich.edu 2703863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2713863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2723863Ssaidi@eecs.umich.edu 2733836Ssaidi@eecs.umich.edu cacheValid = false; 2743836Ssaidi@eecs.umich.edu 2753804Ssaidi@eecs.umich.edu // Assemble full address structure 2763804Ssaidi@eecs.umich.edu tr.va = va; 2773863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2783804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2793804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2803804Ssaidi@eecs.umich.edu tr.real = real; 2813804Ssaidi@eecs.umich.edu 2823804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2833804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2843804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2853863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2863804Ssaidi@eecs.umich.edu i->second->valid = false; 2873804Ssaidi@eecs.umich.edu if (i->second->used) { 2883804Ssaidi@eecs.umich.edu i->second->used = false; 2893804Ssaidi@eecs.umich.edu usedEntries--; 2903804Ssaidi@eecs.umich.edu } 2913881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2923804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2933804Ssaidi@eecs.umich.edu } 2943804Ssaidi@eecs.umich.edu} 2953804Ssaidi@eecs.umich.edu 2963804Ssaidi@eecs.umich.eduvoid 2973804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2983804Ssaidi@eecs.umich.edu{ 2993804Ssaidi@eecs.umich.edu int x; 3003863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3013863Ssaidi@eecs.umich.edu partition_id, context_id); 3023836Ssaidi@eecs.umich.edu cacheValid = false; 3033804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3043804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3053804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3063881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3073881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3083881Ssaidi@eecs.umich.edu } 3093804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3103804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3113804Ssaidi@eecs.umich.edu tlb[x].used = false; 3123804Ssaidi@eecs.umich.edu usedEntries--; 3133804Ssaidi@eecs.umich.edu } 3143804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3153804Ssaidi@eecs.umich.edu } 3163804Ssaidi@eecs.umich.edu } 3173804Ssaidi@eecs.umich.edu} 3183804Ssaidi@eecs.umich.edu 3193804Ssaidi@eecs.umich.eduvoid 3203804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3213804Ssaidi@eecs.umich.edu{ 3223804Ssaidi@eecs.umich.edu int x; 3233863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3243836Ssaidi@eecs.umich.edu cacheValid = false; 3253804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3263804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3273881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3283881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3293881Ssaidi@eecs.umich.edu } 3303804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3313804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3323804Ssaidi@eecs.umich.edu tlb[x].used = false; 3333804Ssaidi@eecs.umich.edu usedEntries--; 3343804Ssaidi@eecs.umich.edu } 3353804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3363804Ssaidi@eecs.umich.edu } 3373804Ssaidi@eecs.umich.edu } 3383804Ssaidi@eecs.umich.edu} 3393804Ssaidi@eecs.umich.edu 3403804Ssaidi@eecs.umich.eduvoid 3413804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3423804Ssaidi@eecs.umich.edu{ 3433804Ssaidi@eecs.umich.edu int x; 3443836Ssaidi@eecs.umich.edu cacheValid = false; 3453836Ssaidi@eecs.umich.edu 3463881Ssaidi@eecs.umich.edu freeList.clear(); 3473907Ssaidi@eecs.umich.edu lookupTable.clear(); 3483804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3493881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3503881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3513804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3523907Ssaidi@eecs.umich.edu tlb[x].used = false; 3533804Ssaidi@eecs.umich.edu } 3543804Ssaidi@eecs.umich.edu usedEntries = 0; 3553804Ssaidi@eecs.umich.edu} 3563804Ssaidi@eecs.umich.edu 3573804Ssaidi@eecs.umich.eduuint64_t 3583804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3593881Ssaidi@eecs.umich.edu if (entry >= size) 3603881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3613881Ssaidi@eecs.umich.edu 3623804Ssaidi@eecs.umich.edu assert(entry < size); 3633881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3643881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3653881Ssaidi@eecs.umich.edu else 3663881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3673804Ssaidi@eecs.umich.edu} 3683804Ssaidi@eecs.umich.edu 3693804Ssaidi@eecs.umich.eduuint64_t 3703804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3713804Ssaidi@eecs.umich.edu assert(entry < size); 3723804Ssaidi@eecs.umich.edu uint64_t tag; 3733881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3743881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3753804Ssaidi@eecs.umich.edu 3763881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3773881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3783881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3793804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3803804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3813804Ssaidi@eecs.umich.edu return tag; 3823804Ssaidi@eecs.umich.edu} 3833804Ssaidi@eecs.umich.edu 3843804Ssaidi@eecs.umich.edubool 3853804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3863804Ssaidi@eecs.umich.edu{ 3873804Ssaidi@eecs.umich.edu if (am) 3883804Ssaidi@eecs.umich.edu return true; 3893804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3903804Ssaidi@eecs.umich.edu return false; 3913804Ssaidi@eecs.umich.edu return true; 3923804Ssaidi@eecs.umich.edu} 3933804Ssaidi@eecs.umich.edu 3943804Ssaidi@eecs.umich.eduvoid 3953804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3963804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3973804Ssaidi@eecs.umich.edu{ 3983804Ssaidi@eecs.umich.edu uint64_t sfsr; 3993804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 4003804Ssaidi@eecs.umich.edu 4013804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4023804Ssaidi@eecs.umich.edu sfsr = 0x3; 4033804Ssaidi@eecs.umich.edu else 4043804Ssaidi@eecs.umich.edu sfsr = 1; 4053804Ssaidi@eecs.umich.edu 4063804Ssaidi@eecs.umich.edu if (write) 4073804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4083804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4093804Ssaidi@eecs.umich.edu if (se) 4103804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4113804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4123804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4133826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 4143804Ssaidi@eecs.umich.edu} 4153804Ssaidi@eecs.umich.edu 4163826Ssaidi@eecs.umich.eduvoid 4173826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 4183826Ssaidi@eecs.umich.edu{ 4193916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4203916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4213916Ssaidi@eecs.umich.edu 4223826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 4233826Ssaidi@eecs.umich.edu} 4243804Ssaidi@eecs.umich.edu 4253804Ssaidi@eecs.umich.eduvoid 4263804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 4273804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4283804Ssaidi@eecs.umich.edu{ 4293811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4303811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4313804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 4323804Ssaidi@eecs.umich.edu} 4333804Ssaidi@eecs.umich.edu 4343804Ssaidi@eecs.umich.eduvoid 4353826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4363826Ssaidi@eecs.umich.edu{ 4373826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 4383826Ssaidi@eecs.umich.edu} 4393826Ssaidi@eecs.umich.edu 4403826Ssaidi@eecs.umich.eduvoid 4413804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 4423804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4433804Ssaidi@eecs.umich.edu{ 4443811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4453811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4463804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 4473826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 4483804Ssaidi@eecs.umich.edu} 4493804Ssaidi@eecs.umich.edu 4503836Ssaidi@eecs.umich.eduvoid 4513826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4523826Ssaidi@eecs.umich.edu{ 4533826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 4543826Ssaidi@eecs.umich.edu} 4553826Ssaidi@eecs.umich.edu 4563826Ssaidi@eecs.umich.edu 4573804Ssaidi@eecs.umich.edu 4583804Ssaidi@eecs.umich.eduFault 4593804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4603804Ssaidi@eecs.umich.edu{ 4613833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4623833Ssaidi@eecs.umich.edu 4633836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4643836Ssaidi@eecs.umich.edu TlbEntry *e; 4653836Ssaidi@eecs.umich.edu 4663836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4673836Ssaidi@eecs.umich.edu 4683836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4693836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4703836Ssaidi@eecs.umich.edu 4713836Ssaidi@eecs.umich.edu // Be fast if we can! 4723836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4733836Ssaidi@eecs.umich.edu if (cacheEntry) { 4743836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4753836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4763836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4773836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4783836Ssaidi@eecs.umich.edu return NoFault; 4793836Ssaidi@eecs.umich.edu } 4803836Ssaidi@eecs.umich.edu } else { 4813836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4823836Ssaidi@eecs.umich.edu return NoFault; 4833836Ssaidi@eecs.umich.edu } 4843836Ssaidi@eecs.umich.edu } 4853836Ssaidi@eecs.umich.edu 4863833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4873833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4883833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4893833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4903833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4913833Ssaidi@eecs.umich.edu 4923833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4933833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4943833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4953804Ssaidi@eecs.umich.edu int context; 4963804Ssaidi@eecs.umich.edu ContextType ct; 4973804Ssaidi@eecs.umich.edu int asi; 4983804Ssaidi@eecs.umich.edu bool real = false; 4993804Ssaidi@eecs.umich.edu 5003833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 5013833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 5023811Ssaidi@eecs.umich.edu 5033804Ssaidi@eecs.umich.edu if (tl > 0) { 5043804Ssaidi@eecs.umich.edu asi = ASI_N; 5053804Ssaidi@eecs.umich.edu ct = Nucleus; 5063804Ssaidi@eecs.umich.edu context = 0; 5073804Ssaidi@eecs.umich.edu } else { 5083804Ssaidi@eecs.umich.edu asi = ASI_P; 5093804Ssaidi@eecs.umich.edu ct = Primary; 5103833Ssaidi@eecs.umich.edu context = pri_context; 5113804Ssaidi@eecs.umich.edu } 5123804Ssaidi@eecs.umich.edu 5133833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5143836Ssaidi@eecs.umich.edu cacheValid = true; 5153836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5163836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5173836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5183804Ssaidi@eecs.umich.edu return NoFault; 5193804Ssaidi@eecs.umich.edu } 5203804Ssaidi@eecs.umich.edu 5213836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5223836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5233804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 5243804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5253804Ssaidi@eecs.umich.edu } 5263804Ssaidi@eecs.umich.edu 5273804Ssaidi@eecs.umich.edu if (addr_mask) 5283804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5293804Ssaidi@eecs.umich.edu 5303804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5313804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 5323804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5333804Ssaidi@eecs.umich.edu } 5343804Ssaidi@eecs.umich.edu 5353833Ssaidi@eecs.umich.edu if (!lsu_im) { 5363836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5373804Ssaidi@eecs.umich.edu real = true; 5383804Ssaidi@eecs.umich.edu context = 0; 5393804Ssaidi@eecs.umich.edu } else { 5403804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5413804Ssaidi@eecs.umich.edu } 5423804Ssaidi@eecs.umich.edu 5433804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5443916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5453804Ssaidi@eecs.umich.edu if (real) 5463804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5473804Ssaidi@eecs.umich.edu else 5483804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5493804Ssaidi@eecs.umich.edu } 5503804Ssaidi@eecs.umich.edu 5513804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5523804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5533928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5543804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 5553804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5563804Ssaidi@eecs.umich.edu } 5573804Ssaidi@eecs.umich.edu 5583836Ssaidi@eecs.umich.edu // cache translation date for next translation 5593836Ssaidi@eecs.umich.edu cacheValid = true; 5603836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5613836Ssaidi@eecs.umich.edu cacheEntry = e; 5623836Ssaidi@eecs.umich.edu 5633826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5643836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5653836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5663804Ssaidi@eecs.umich.edu return NoFault; 5673804Ssaidi@eecs.umich.edu} 5683804Ssaidi@eecs.umich.edu 5693804Ssaidi@eecs.umich.edu 5703804Ssaidi@eecs.umich.edu 5713804Ssaidi@eecs.umich.eduFault 5723804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5733804Ssaidi@eecs.umich.edu{ 5743804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5753833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 5763836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5773836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5783836Ssaidi@eecs.umich.edu ASI asi; 5793836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5803836Ssaidi@eecs.umich.edu bool implicit = false; 5813836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5823833Ssaidi@eecs.umich.edu 5833836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5843836Ssaidi@eecs.umich.edu vaddr, size, asi); 5853836Ssaidi@eecs.umich.edu 5863929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5873929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5883929Ssaidi@eecs.umich.edu freeList.size()); 5893836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5903836Ssaidi@eecs.umich.edu implicit = true; 5913836Ssaidi@eecs.umich.edu 5923836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 5933836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5943836Ssaidi@eecs.umich.edu return NoFault; 5953836Ssaidi@eecs.umich.edu } 5963836Ssaidi@eecs.umich.edu 5973836Ssaidi@eecs.umich.edu // Be fast if we can! 5983836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5994090Ssaidi@eecs.umich.edu 6004090Ssaidi@eecs.umich.edu 6014090Ssaidi@eecs.umich.edu 6024090Ssaidi@eecs.umich.edu if (cacheEntry[0]) { 6034090Ssaidi@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 6044090Ssaidi@eecs.umich.edu Addr ce_va = ce->range.va; 6054090Ssaidi@eecs.umich.edu if (cacheAsi[0] == asi && 6064090Ssaidi@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6074090Ssaidi@eecs.umich.edu (!write || ce->pte.writable())) { 6084090Ssaidi@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6094090Ssaidi@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6104090Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6114090Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6124090Ssaidi@eecs.umich.edu return NoFault; 6134090Ssaidi@eecs.umich.edu } // if matched 6144090Ssaidi@eecs.umich.edu } // if cache entry valid 6154090Ssaidi@eecs.umich.edu if (cacheEntry[1]) { 6164090Ssaidi@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 6174090Ssaidi@eecs.umich.edu Addr ce_va = ce->range.va; 6184090Ssaidi@eecs.umich.edu if (cacheAsi[1] == asi && 6194090Ssaidi@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6204090Ssaidi@eecs.umich.edu (!write || ce->pte.writable())) { 6214090Ssaidi@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6224090Ssaidi@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6234090Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6244090Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6254090Ssaidi@eecs.umich.edu return NoFault; 6264090Ssaidi@eecs.umich.edu } // if matched 6274090Ssaidi@eecs.umich.edu } // if cache entry valid 6284090Ssaidi@eecs.umich.edu } 6293836Ssaidi@eecs.umich.edu 6303833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6313833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6323833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6333833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6343833Ssaidi@eecs.umich.edu 6353833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6363833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6373833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6383916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6393833Ssaidi@eecs.umich.edu 6403804Ssaidi@eecs.umich.edu bool real = false; 6413832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6423832Ssaidi@eecs.umich.edu int context = 0; 6433804Ssaidi@eecs.umich.edu 6443804Ssaidi@eecs.umich.edu TlbEntry *e; 6453804Ssaidi@eecs.umich.edu 6463833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6473833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6483804Ssaidi@eecs.umich.edu 6493804Ssaidi@eecs.umich.edu if (implicit) { 6503804Ssaidi@eecs.umich.edu if (tl > 0) { 6513804Ssaidi@eecs.umich.edu asi = ASI_N; 6523804Ssaidi@eecs.umich.edu ct = Nucleus; 6533804Ssaidi@eecs.umich.edu context = 0; 6543804Ssaidi@eecs.umich.edu } else { 6553804Ssaidi@eecs.umich.edu asi = ASI_P; 6563804Ssaidi@eecs.umich.edu ct = Primary; 6573833Ssaidi@eecs.umich.edu context = pri_context; 6583804Ssaidi@eecs.umich.edu } 6593910Ssaidi@eecs.umich.edu } else { 6603804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6613910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6623804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6633804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6643804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6653804Ssaidi@eecs.umich.edu } 6663910Ssaidi@eecs.umich.edu 6673910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6683804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6693804Ssaidi@eecs.umich.edu return new DataAccessException; 6703804Ssaidi@eecs.umich.edu } 6713804Ssaidi@eecs.umich.edu 6723910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6733910Ssaidi@eecs.umich.edu context = pri_context; 6743910Ssaidi@eecs.umich.edu ct = Primary; 6753910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6763910Ssaidi@eecs.umich.edu context = sec_context; 6773910Ssaidi@eecs.umich.edu ct = Secondary; 6783910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6793910Ssaidi@eecs.umich.edu ct = Nucleus; 6803910Ssaidi@eecs.umich.edu context = 0; 6813910Ssaidi@eecs.umich.edu } else { // ???? 6823910Ssaidi@eecs.umich.edu ct = Primary; 6833910Ssaidi@eecs.umich.edu context = pri_context; 6843910Ssaidi@eecs.umich.edu } 6853902Ssaidi@eecs.umich.edu } 6863804Ssaidi@eecs.umich.edu 6873926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6883804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6893804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6903804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 6913804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 6923856Ssaidi@eecs.umich.edu 6933804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6943804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6954103Ssaidi@eecs.umich.edu 6963824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6974103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6983804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6993804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 7003804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 7013804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 7023824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 7033824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 7043825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 7053825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 7063823Ssaidi@eecs.umich.edu 7073926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 7084010Ssaidi@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi)) 7093823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 7103804Ssaidi@eecs.umich.edu } 7113804Ssaidi@eecs.umich.edu 7123826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 7133826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 7143826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 7153826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7163826Ssaidi@eecs.umich.edu } 7173826Ssaidi@eecs.umich.edu 7183826Ssaidi@eecs.umich.edu if (addr_mask) 7193826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7203826Ssaidi@eecs.umich.edu 7213826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7223826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 7233826Ssaidi@eecs.umich.edu return new DataAccessException; 7243826Ssaidi@eecs.umich.edu } 7253826Ssaidi@eecs.umich.edu 7263826Ssaidi@eecs.umich.edu 7273910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7283804Ssaidi@eecs.umich.edu real = true; 7293804Ssaidi@eecs.umich.edu context = 0; 7303804Ssaidi@eecs.umich.edu }; 7313804Ssaidi@eecs.umich.edu 7323804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7333836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7343804Ssaidi@eecs.umich.edu return NoFault; 7353804Ssaidi@eecs.umich.edu } 7363804Ssaidi@eecs.umich.edu 7373836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7383804Ssaidi@eecs.umich.edu 7393804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7403916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7413811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7423804Ssaidi@eecs.umich.edu if (real) 7433804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7443804Ssaidi@eecs.umich.edu else 7453804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7463804Ssaidi@eecs.umich.edu 7473804Ssaidi@eecs.umich.edu } 7483804Ssaidi@eecs.umich.edu 7493928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7503928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7513928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7523928Ssaidi@eecs.umich.edu return new DataAccessException; 7533928Ssaidi@eecs.umich.edu } 7543804Ssaidi@eecs.umich.edu 7553804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7563928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7573804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7583804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7593804Ssaidi@eecs.umich.edu } 7603804Ssaidi@eecs.umich.edu 7613804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7623928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7633804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7643804Ssaidi@eecs.umich.edu return new DataAccessException; 7653804Ssaidi@eecs.umich.edu } 7663804Ssaidi@eecs.umich.edu 7673928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7683928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7693928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7703928Ssaidi@eecs.umich.edu return new DataAccessException; 7713928Ssaidi@eecs.umich.edu } 7723928Ssaidi@eecs.umich.edu 7733928Ssaidi@eecs.umich.edu 7744090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7753804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7763804Ssaidi@eecs.umich.edu 7773836Ssaidi@eecs.umich.edu // cache translation date for next translation 7783836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7793881Ssaidi@eecs.umich.edu if (!cacheValid) { 7803881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7813881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7823881Ssaidi@eecs.umich.edu } 7833881Ssaidi@eecs.umich.edu 7843836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7853836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7863836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7873836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7883836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7893836Ssaidi@eecs.umich.edu if (implicit) 7903836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7913836Ssaidi@eecs.umich.edu } 7923881Ssaidi@eecs.umich.edu cacheValid = true; 7933826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 7943836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 7953836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7963804Ssaidi@eecs.umich.edu return NoFault; 7974103Ssaidi@eecs.umich.edu 7983806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7994103Ssaidi@eecs.umich.eduhandleIntRegAccess: 8004103Ssaidi@eecs.umich.edu if (!hpriv) { 8014103Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8024103Ssaidi@eecs.umich.edu if (priv) 8034103Ssaidi@eecs.umich.edu return new DataAccessException; 8044103Ssaidi@eecs.umich.edu else 8054103Ssaidi@eecs.umich.edu return new PrivilegedAction; 8064103Ssaidi@eecs.umich.edu } 8074103Ssaidi@eecs.umich.edu 8084103Ssaidi@eecs.umich.edu if (asi == ASI_SWVR_UDB_INTR_W && !write || 8094103Ssaidi@eecs.umich.edu asi == ASI_SWVR_UDB_INTR_R && write) { 8104103Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8114103Ssaidi@eecs.umich.edu return new DataAccessException; 8124103Ssaidi@eecs.umich.edu } 8134103Ssaidi@eecs.umich.edu 8144103Ssaidi@eecs.umich.edu goto regAccessOk; 8154103Ssaidi@eecs.umich.edu 8163804Ssaidi@eecs.umich.edu 8173806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8183806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8193806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8203806Ssaidi@eecs.umich.edu return new DataAccessException; 8213806Ssaidi@eecs.umich.edu } 8223824Ssaidi@eecs.umich.edu goto regAccessOk; 8233824Ssaidi@eecs.umich.edu 8243824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8253824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8263824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8273824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8283824Ssaidi@eecs.umich.edu } 8293881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 8303824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8313824Ssaidi@eecs.umich.edu return new DataAccessException; 8323824Ssaidi@eecs.umich.edu } 8333824Ssaidi@eecs.umich.edu goto regAccessOk; 8343824Ssaidi@eecs.umich.edu 8353825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8363825Ssaidi@eecs.umich.edu if (!hpriv) { 8374070Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8384070Ssaidi@eecs.umich.edu if (priv) 8393825Ssaidi@eecs.umich.edu return new DataAccessException; 8404070Ssaidi@eecs.umich.edu else 8413825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8423825Ssaidi@eecs.umich.edu } 8433825Ssaidi@eecs.umich.edu goto regAccessOk; 8443825Ssaidi@eecs.umich.edu 8453825Ssaidi@eecs.umich.edu 8463824Ssaidi@eecs.umich.eduregAccessOk: 8473804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8483811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8493806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8503806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8513806Ssaidi@eecs.umich.edu return NoFault; 8523804Ssaidi@eecs.umich.edu}; 8533804Ssaidi@eecs.umich.edu 8543806Ssaidi@eecs.umich.eduTick 8553806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8563806Ssaidi@eecs.umich.edu{ 8573823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8583823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8594070Ssaidi@eecs.umich.edu uint64_t temp; 8603823Ssaidi@eecs.umich.edu 8613823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8623823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8633823Ssaidi@eecs.umich.edu 8643823Ssaidi@eecs.umich.edu switch (asi) { 8653823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8663823Ssaidi@eecs.umich.edu assert(va == 0); 8673823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 8683823Ssaidi@eecs.umich.edu break; 8693823Ssaidi@eecs.umich.edu case ASI_MMU: 8703823Ssaidi@eecs.umich.edu switch (va) { 8713823Ssaidi@eecs.umich.edu case 0x8: 8723823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 8733823Ssaidi@eecs.umich.edu break; 8743823Ssaidi@eecs.umich.edu case 0x10: 8753823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 8763823Ssaidi@eecs.umich.edu break; 8773823Ssaidi@eecs.umich.edu default: 8783823Ssaidi@eecs.umich.edu goto doMmuReadError; 8793823Ssaidi@eecs.umich.edu } 8803823Ssaidi@eecs.umich.edu break; 8813824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8823824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 8833824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8843824Ssaidi@eecs.umich.edu break; 8853823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8863823Ssaidi@eecs.umich.edu assert(va == 0); 8873823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 8883823Ssaidi@eecs.umich.edu break; 8893823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8903823Ssaidi@eecs.umich.edu assert(va == 0); 8913823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 8923823Ssaidi@eecs.umich.edu break; 8933823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8943823Ssaidi@eecs.umich.edu assert(va == 0); 8953823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 8963823Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8983823Ssaidi@eecs.umich.edu assert(va == 0); 8993823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 9003823Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 9033823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9073823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 9113823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 9153823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 9193823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 9233823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 9273823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 9313823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 9323823Ssaidi@eecs.umich.edu break; 9333826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9343912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9353826Ssaidi@eecs.umich.edu break; 9363823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9373823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9383823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9393823Ssaidi@eecs.umich.edu break; 9403826Ssaidi@eecs.umich.edu case ASI_IMMU: 9413826Ssaidi@eecs.umich.edu switch (va) { 9423833Ssaidi@eecs.umich.edu case 0x0: 9433833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9443833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9453833Ssaidi@eecs.umich.edu break; 9463906Ssaidi@eecs.umich.edu case 0x18: 9473906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 9483906Ssaidi@eecs.umich.edu break; 9493826Ssaidi@eecs.umich.edu case 0x30: 9503826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 9513826Ssaidi@eecs.umich.edu break; 9523826Ssaidi@eecs.umich.edu default: 9533826Ssaidi@eecs.umich.edu goto doMmuReadError; 9543826Ssaidi@eecs.umich.edu } 9553826Ssaidi@eecs.umich.edu break; 9563823Ssaidi@eecs.umich.edu case ASI_DMMU: 9573823Ssaidi@eecs.umich.edu switch (va) { 9583833Ssaidi@eecs.umich.edu case 0x0: 9593833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9603833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9613833Ssaidi@eecs.umich.edu break; 9623906Ssaidi@eecs.umich.edu case 0x18: 9633906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 9643906Ssaidi@eecs.umich.edu break; 9653906Ssaidi@eecs.umich.edu case 0x20: 9663906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 9673906Ssaidi@eecs.umich.edu break; 9683826Ssaidi@eecs.umich.edu case 0x30: 9693826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 9703826Ssaidi@eecs.umich.edu break; 9713823Ssaidi@eecs.umich.edu case 0x80: 9723823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 9733823Ssaidi@eecs.umich.edu break; 9743823Ssaidi@eecs.umich.edu default: 9753823Ssaidi@eecs.umich.edu goto doMmuReadError; 9763823Ssaidi@eecs.umich.edu } 9773823Ssaidi@eecs.umich.edu break; 9783833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9794070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9804070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), 9814070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), 9824070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 9834070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), 9844070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); 9853833Ssaidi@eecs.umich.edu break; 9863833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9874070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9884070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), 9894070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), 9904070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 9914070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), 9924070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); 9933833Ssaidi@eecs.umich.edu break; 9943899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9954070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9964070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), 9974070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), 9984070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 9994070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), 10004070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); 10013899Ssaidi@eecs.umich.edu break; 10023899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10034070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10044070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), 10054070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), 10064070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 10074070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), 10084070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); 10093899Ssaidi@eecs.umich.edu break; 10104103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10114103Ssaidi@eecs.umich.edu pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10124103Ssaidi@eecs.umich.edu break; 10134103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10144103Ssaidi@eecs.umich.edu temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10154103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); 10164103Ssaidi@eecs.umich.edu pkt->set(temp); 10174103Ssaidi@eecs.umich.edu break; 10183823Ssaidi@eecs.umich.edu default: 10193823Ssaidi@eecs.umich.edudoMmuReadError: 10203823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10213823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10223823Ssaidi@eecs.umich.edu } 10233823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 10243823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 10253806Ssaidi@eecs.umich.edu} 10263806Ssaidi@eecs.umich.edu 10273806Ssaidi@eecs.umich.eduTick 10283806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10293806Ssaidi@eecs.umich.edu{ 10303823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10313823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10323823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10333823Ssaidi@eecs.umich.edu 10343826Ssaidi@eecs.umich.edu Addr ta_insert; 10353826Ssaidi@eecs.umich.edu Addr va_insert; 10363826Ssaidi@eecs.umich.edu Addr ct_insert; 10373826Ssaidi@eecs.umich.edu int part_insert; 10383826Ssaidi@eecs.umich.edu int entry_insert = -1; 10393826Ssaidi@eecs.umich.edu bool real_insert; 10403863Ssaidi@eecs.umich.edu bool ignore; 10413863Ssaidi@eecs.umich.edu int part_id; 10423863Ssaidi@eecs.umich.edu int ctx_id; 10433826Ssaidi@eecs.umich.edu PageTableEntry pte; 10443826Ssaidi@eecs.umich.edu 10453825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10463823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10473823Ssaidi@eecs.umich.edu 10483823Ssaidi@eecs.umich.edu switch (asi) { 10493823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10503823Ssaidi@eecs.umich.edu assert(va == 0); 10513823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 10523823Ssaidi@eecs.umich.edu break; 10533823Ssaidi@eecs.umich.edu case ASI_MMU: 10543823Ssaidi@eecs.umich.edu switch (va) { 10553823Ssaidi@eecs.umich.edu case 0x8: 10563823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 10573823Ssaidi@eecs.umich.edu break; 10583823Ssaidi@eecs.umich.edu case 0x10: 10593823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 10603823Ssaidi@eecs.umich.edu break; 10613823Ssaidi@eecs.umich.edu default: 10623823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10633823Ssaidi@eecs.umich.edu } 10643823Ssaidi@eecs.umich.edu break; 10653824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10663825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10673824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 10683824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10693824Ssaidi@eecs.umich.edu break; 10703823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10713823Ssaidi@eecs.umich.edu assert(va == 0); 10723823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 10733823Ssaidi@eecs.umich.edu break; 10743823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10753823Ssaidi@eecs.umich.edu assert(va == 0); 10763823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 10773823Ssaidi@eecs.umich.edu break; 10783823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10793823Ssaidi@eecs.umich.edu assert(va == 0); 10803823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 10813823Ssaidi@eecs.umich.edu break; 10823823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10833823Ssaidi@eecs.umich.edu assert(va == 0); 10843823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 10853823Ssaidi@eecs.umich.edu break; 10863823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10873823Ssaidi@eecs.umich.edu assert(va == 0); 10883823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 10893823Ssaidi@eecs.umich.edu break; 10903823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10913823Ssaidi@eecs.umich.edu assert(va == 0); 10923823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 10933823Ssaidi@eecs.umich.edu break; 10943823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 10953823Ssaidi@eecs.umich.edu assert(va == 0); 10963823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 10973823Ssaidi@eecs.umich.edu break; 10983823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 10993823Ssaidi@eecs.umich.edu assert(va == 0); 11003823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 11013823Ssaidi@eecs.umich.edu break; 11023823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11033823Ssaidi@eecs.umich.edu assert(va == 0); 11043823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 11053823Ssaidi@eecs.umich.edu break; 11063823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11073823Ssaidi@eecs.umich.edu assert(va == 0); 11083823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 11093823Ssaidi@eecs.umich.edu break; 11103823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11113823Ssaidi@eecs.umich.edu assert(va == 0); 11123823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 11133823Ssaidi@eecs.umich.edu break; 11143823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11153823Ssaidi@eecs.umich.edu assert(va == 0); 11163823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 11173823Ssaidi@eecs.umich.edu break; 11183825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11193825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11203825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11213825Ssaidi@eecs.umich.edu break; 11223823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11233823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11243823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11253823Ssaidi@eecs.umich.edu break; 11263826Ssaidi@eecs.umich.edu case ASI_IMMU: 11273826Ssaidi@eecs.umich.edu switch (va) { 11283906Ssaidi@eecs.umich.edu case 0x18: 11293906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 11303906Ssaidi@eecs.umich.edu break; 11313826Ssaidi@eecs.umich.edu case 0x30: 11323916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11333826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 11343826Ssaidi@eecs.umich.edu break; 11353826Ssaidi@eecs.umich.edu default: 11363826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11373826Ssaidi@eecs.umich.edu } 11383826Ssaidi@eecs.umich.edu break; 11393826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11403826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11413826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11423826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11433826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 11443826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11453826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11463826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11473826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11483826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11493826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11503826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11513826Ssaidi@eecs.umich.edu pte, entry_insert); 11523826Ssaidi@eecs.umich.edu break; 11533826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11543826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11553826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11563826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11573826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 11583826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11593826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11603826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11613826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11623826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11633826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11643826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11653826Ssaidi@eecs.umich.edu break; 11663863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11673863Ssaidi@eecs.umich.edu ignore = false; 11683863Ssaidi@eecs.umich.edu ctx_id = -1; 11693863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11703863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11713863Ssaidi@eecs.umich.edu case 0: 11723863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 11733863Ssaidi@eecs.umich.edu break; 11743863Ssaidi@eecs.umich.edu case 1: 11753863Ssaidi@eecs.umich.edu ignore = true; 11763863Ssaidi@eecs.umich.edu break; 11773863Ssaidi@eecs.umich.edu case 3: 11783863Ssaidi@eecs.umich.edu ctx_id = 0; 11793863Ssaidi@eecs.umich.edu break; 11803863Ssaidi@eecs.umich.edu default: 11813863Ssaidi@eecs.umich.edu ignore = true; 11823863Ssaidi@eecs.umich.edu } 11833863Ssaidi@eecs.umich.edu 11843863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11853863Ssaidi@eecs.umich.edu case 0: // demap page 11863863Ssaidi@eecs.umich.edu if (!ignore) 11873863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11883863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11893863Ssaidi@eecs.umich.edu break; 11903863Ssaidi@eecs.umich.edu case 1: //demap context 11913863Ssaidi@eecs.umich.edu if (!ignore) 11923863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11933863Ssaidi@eecs.umich.edu break; 11943863Ssaidi@eecs.umich.edu case 2: 11953863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 11963863Ssaidi@eecs.umich.edu break; 11973863Ssaidi@eecs.umich.edu default: 11983863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 11993863Ssaidi@eecs.umich.edu } 12003863Ssaidi@eecs.umich.edu break; 12013823Ssaidi@eecs.umich.edu case ASI_DMMU: 12023823Ssaidi@eecs.umich.edu switch (va) { 12033906Ssaidi@eecs.umich.edu case 0x18: 12043906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 12053906Ssaidi@eecs.umich.edu break; 12063826Ssaidi@eecs.umich.edu case 0x30: 12073916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12083826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 12093826Ssaidi@eecs.umich.edu break; 12103823Ssaidi@eecs.umich.edu case 0x80: 12113823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 12123823Ssaidi@eecs.umich.edu break; 12133823Ssaidi@eecs.umich.edu default: 12143823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12153823Ssaidi@eecs.umich.edu } 12163823Ssaidi@eecs.umich.edu break; 12173863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12183863Ssaidi@eecs.umich.edu ignore = false; 12193863Ssaidi@eecs.umich.edu ctx_id = -1; 12203863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 12213863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12223863Ssaidi@eecs.umich.edu case 0: 12233863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 12243863Ssaidi@eecs.umich.edu break; 12253863Ssaidi@eecs.umich.edu case 1: 12263863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 12273863Ssaidi@eecs.umich.edu break; 12283863Ssaidi@eecs.umich.edu case 3: 12293863Ssaidi@eecs.umich.edu ctx_id = 0; 12303863Ssaidi@eecs.umich.edu break; 12313863Ssaidi@eecs.umich.edu default: 12323863Ssaidi@eecs.umich.edu ignore = true; 12333863Ssaidi@eecs.umich.edu } 12343863Ssaidi@eecs.umich.edu 12353863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12363863Ssaidi@eecs.umich.edu case 0: // demap page 12373863Ssaidi@eecs.umich.edu if (!ignore) 12383863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12393863Ssaidi@eecs.umich.edu break; 12403863Ssaidi@eecs.umich.edu case 1: //demap context 12413863Ssaidi@eecs.umich.edu if (!ignore) 12423863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12433863Ssaidi@eecs.umich.edu break; 12443863Ssaidi@eecs.umich.edu case 2: 12453863Ssaidi@eecs.umich.edu demapAll(part_id); 12463863Ssaidi@eecs.umich.edu break; 12473863Ssaidi@eecs.umich.edu default: 12483863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12493863Ssaidi@eecs.umich.edu } 12503863Ssaidi@eecs.umich.edu break; 12514103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12524103Ssaidi@eecs.umich.edu int msb; 12534103Ssaidi@eecs.umich.edu // clear all the interrupts that aren't set in the write 12544103Ssaidi@eecs.umich.edu while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) { 12554103Ssaidi@eecs.umich.edu msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data); 12564103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); 12574103Ssaidi@eecs.umich.edu } 12584103Ssaidi@eecs.umich.edu break; 12594103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12604103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12614103Ssaidi@eecs.umich.edu post_interrupt(bits(data,5,0),0); 12624103Ssaidi@eecs.umich.edu break; 12634103Ssaidi@eecs.umich.edu default: 12643823Ssaidi@eecs.umich.edudoMmuWriteError: 12653823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12663823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12673823Ssaidi@eecs.umich.edu } 12683823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 12693823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 12703806Ssaidi@eecs.umich.edu} 12713806Ssaidi@eecs.umich.edu 12723804Ssaidi@eecs.umich.eduvoid 12734070Ssaidi@eecs.umich.eduDTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12744070Ssaidi@eecs.umich.edu{ 12754070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12764070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12774070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), 12784070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 12794070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), 12804070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 12814070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 12824070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), 12834070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 12844070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), 12854070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 12864070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 12874070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), 12884070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 12894070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), 12904070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 12914070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 12924070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), 12934070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 12944070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), 12954070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 12964070Ssaidi@eecs.umich.edu} 12974070Ssaidi@eecs.umich.edu 12984070Ssaidi@eecs.umich.edu 12994070Ssaidi@eecs.umich.edu 13004070Ssaidi@eecs.umich.edu 13014070Ssaidi@eecs.umich.edu 13024070Ssaidi@eecs.umich.eduuint64_t 13034070Ssaidi@eecs.umich.eduDTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13044070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13054070Ssaidi@eecs.umich.edu{ 13064070Ssaidi@eecs.umich.edu uint64_t tsb; 13074070Ssaidi@eecs.umich.edu uint64_t config; 13084070Ssaidi@eecs.umich.edu 13094070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13104070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13114070Ssaidi@eecs.umich.edu config = c0_config; 13124070Ssaidi@eecs.umich.edu } else { 13134070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13144070Ssaidi@eecs.umich.edu config = cX_config; 13154070Ssaidi@eecs.umich.edu } 13164070Ssaidi@eecs.umich.edu 13174070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13184070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13194070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13204070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13214070Ssaidi@eecs.umich.edu 13224070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13234070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13244070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13254070Ssaidi@eecs.umich.edu 13264070Ssaidi@eecs.umich.edu return ptr; 13274070Ssaidi@eecs.umich.edu} 13284070Ssaidi@eecs.umich.edu 13294070Ssaidi@eecs.umich.edu 13304070Ssaidi@eecs.umich.eduvoid 13313804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13323804Ssaidi@eecs.umich.edu{ 13334000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13344000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13354000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13364000Ssaidi@eecs.umich.edu 13374000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13384000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13394000Ssaidi@eecs.umich.edu int cntr = 0; 13404000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13414000Ssaidi@eecs.umich.edu i = freeList.begin(); 13424000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13434000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13444000Ssaidi@eecs.umich.edu i++; 13454000Ssaidi@eecs.umich.edu } 13464000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13474000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13484000Ssaidi@eecs.umich.edu 13494000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13504000Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13514000Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13524000Ssaidi@eecs.umich.edu } 13533804Ssaidi@eecs.umich.edu} 13543804Ssaidi@eecs.umich.edu 13553804Ssaidi@eecs.umich.eduvoid 13563804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13573804Ssaidi@eecs.umich.edu{ 13584000Ssaidi@eecs.umich.edu int oldSize; 13594000Ssaidi@eecs.umich.edu 13604000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13614000Ssaidi@eecs.umich.edu if (oldSize != size) 13624000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13634000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13644000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13654000Ssaidi@eecs.umich.edu 13664000Ssaidi@eecs.umich.edu int cntr; 13674000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13684000Ssaidi@eecs.umich.edu 13694000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13704000Ssaidi@eecs.umich.edu freeList.clear(); 13714000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13724000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13734000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 13744000Ssaidi@eecs.umich.edu 13754000Ssaidi@eecs.umich.edu lookupTable.clear(); 13764000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13774000Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 13784000Ssaidi@eecs.umich.edu if (tlb[x].valid) 13794000Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 13804000Ssaidi@eecs.umich.edu 13814000Ssaidi@eecs.umich.edu } 13823804Ssaidi@eecs.umich.edu} 13833804Ssaidi@eecs.umich.edu 13844088Sbinkertn@umich.edu/* end namespace SparcISA */ } 13854088Sbinkertn@umich.edu 13864088Sbinkertn@umich.eduusing namespace SparcISA; 13873804Ssaidi@eecs.umich.edu 13883804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 13893804Ssaidi@eecs.umich.edu 13903804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 13913804Ssaidi@eecs.umich.edu 13923804Ssaidi@eecs.umich.edu Param<int> size; 13933804Ssaidi@eecs.umich.edu 13943804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 13953804Ssaidi@eecs.umich.edu 13963804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 13973804Ssaidi@eecs.umich.edu 13983804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 13993804Ssaidi@eecs.umich.edu 14003804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 14013804Ssaidi@eecs.umich.edu 14023804Ssaidi@eecs.umich.edu 14033804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 14043804Ssaidi@eecs.umich.edu{ 14053804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 14063804Ssaidi@eecs.umich.edu} 14073804Ssaidi@eecs.umich.edu 14083804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 14093804Ssaidi@eecs.umich.edu 14103804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 14113804Ssaidi@eecs.umich.edu 14123804Ssaidi@eecs.umich.edu Param<int> size; 14133804Ssaidi@eecs.umich.edu 14143804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 14153804Ssaidi@eecs.umich.edu 14163804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 14173804Ssaidi@eecs.umich.edu 14183804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 14193804Ssaidi@eecs.umich.edu 14203804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 14213804Ssaidi@eecs.umich.edu 14223804Ssaidi@eecs.umich.edu 14233804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 14243804Ssaidi@eecs.umich.edu{ 14253804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 14263804Ssaidi@eecs.umich.edu} 14273804Ssaidi@eecs.umich.edu 14283804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 1429