tlb.cc revision 4088
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 423569Sgblack@eecs.umich.edu#include "sim/builder.hh" 433569Sgblack@eecs.umich.edu 443804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 453804Ssaidi@eecs.umich.edu * */ 464088Sbinkertn@umich.edunamespace SparcISA { 473569Sgblack@eecs.umich.edu 483804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 493881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 503881Ssaidi@eecs.umich.edu cacheValid(false) 513804Ssaidi@eecs.umich.edu{ 523804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 533804Ssaidi@eecs.umich.edu if (size > 64) 543804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 553569Sgblack@eecs.umich.edu 563804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 573918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 583881Ssaidi@eecs.umich.edu 593881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 603881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 613804Ssaidi@eecs.umich.edu} 623569Sgblack@eecs.umich.edu 633804Ssaidi@eecs.umich.eduvoid 643804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 653804Ssaidi@eecs.umich.edu{ 663804Ssaidi@eecs.umich.edu MapIter i; 673881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 683804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 693804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 703804Ssaidi@eecs.umich.edu t->used = false; 713804Ssaidi@eecs.umich.edu usedEntries--; 723804Ssaidi@eecs.umich.edu } 733804Ssaidi@eecs.umich.edu } 743804Ssaidi@eecs.umich.edu} 753569Sgblack@eecs.umich.edu 763569Sgblack@eecs.umich.edu 773804Ssaidi@eecs.umich.eduvoid 783804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 793826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 803804Ssaidi@eecs.umich.edu{ 813569Sgblack@eecs.umich.edu 823569Sgblack@eecs.umich.edu 833804Ssaidi@eecs.umich.edu MapIter i; 843826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 853907Ssaidi@eecs.umich.edu// TlbRange tr; 863826Ssaidi@eecs.umich.edu int x; 873811Ssaidi@eecs.umich.edu 883836Ssaidi@eecs.umich.edu cacheValid = false; 893915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 903907Ssaidi@eecs.umich.edu /* tr.va = va; 913881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 923881Ssaidi@eecs.umich.edu tr.contextId = context_id; 933881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 943881Ssaidi@eecs.umich.edu tr.real = real; 953907Ssaidi@eecs.umich.edu*/ 963881Ssaidi@eecs.umich.edu 973881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 983881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 993881Ssaidi@eecs.umich.edu 1003881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1013907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1023907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1033907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1043907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1053907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1063907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1073907Ssaidi@eecs.umich.edu { 1083907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1093907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1103907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1113907Ssaidi@eecs.umich.edu 1123907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1133907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1143907Ssaidi@eecs.umich.edu tlb[x].used = false; 1153907Ssaidi@eecs.umich.edu usedEntries--; 1163907Ssaidi@eecs.umich.edu } 1173907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1183907Ssaidi@eecs.umich.edu } 1193907Ssaidi@eecs.umich.edu } 1203907Ssaidi@eecs.umich.edu } 1213907Ssaidi@eecs.umich.edu 1223907Ssaidi@eecs.umich.edu 1233907Ssaidi@eecs.umich.edu/* 1243881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1253881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1263881Ssaidi@eecs.umich.edu i->second->valid = false; 1273881Ssaidi@eecs.umich.edu if (i->second->used) { 1283881Ssaidi@eecs.umich.edu i->second->used = false; 1293881Ssaidi@eecs.umich.edu usedEntries--; 1303881Ssaidi@eecs.umich.edu } 1313881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1323881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1333881Ssaidi@eecs.umich.edu i->second); 1343881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1353881Ssaidi@eecs.umich.edu } 1363907Ssaidi@eecs.umich.edu*/ 1373811Ssaidi@eecs.umich.edu 1383826Ssaidi@eecs.umich.edu if (entry != -1) { 1393826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1403826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1413826Ssaidi@eecs.umich.edu } else { 1423881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1433881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1443881Ssaidi@eecs.umich.edu } else { 1453881Ssaidi@eecs.umich.edu x = lastReplaced; 1463881Ssaidi@eecs.umich.edu do { 1473881Ssaidi@eecs.umich.edu ++x; 1483881Ssaidi@eecs.umich.edu if (x == size) 1493881Ssaidi@eecs.umich.edu x = 0; 1503881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1513881Ssaidi@eecs.umich.edu goto insertAllLocked; 1523881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1533881Ssaidi@eecs.umich.edu lastReplaced = x; 1543881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1553881Ssaidi@eecs.umich.edu } 1563881Ssaidi@eecs.umich.edu /* 1573826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1583826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1593826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1603826Ssaidi@eecs.umich.edu break; 1613826Ssaidi@eecs.umich.edu } 1623881Ssaidi@eecs.umich.edu }*/ 1633569Sgblack@eecs.umich.edu } 1643569Sgblack@eecs.umich.edu 1653881Ssaidi@eecs.umich.eduinsertAllLocked: 1663804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1673881Ssaidi@eecs.umich.edu if (!new_entry) { 1683826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1693881Ssaidi@eecs.umich.edu } 1703881Ssaidi@eecs.umich.edu 1713881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1723907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1733907Ssaidi@eecs.umich.edu usedEntries--; 1743929Ssaidi@eecs.umich.edu if (new_entry->valid) 1753929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1763907Ssaidi@eecs.umich.edu 1773907Ssaidi@eecs.umich.edu 1783804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1793804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1803881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1813804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1823804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1833804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1843804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1853804Ssaidi@eecs.umich.edu new_entry->used = true;; 1863804Ssaidi@eecs.umich.edu new_entry->valid = true; 1873804Ssaidi@eecs.umich.edu usedEntries++; 1883569Sgblack@eecs.umich.edu 1893569Sgblack@eecs.umich.edu 1903569Sgblack@eecs.umich.edu 1913863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1923863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1933804Ssaidi@eecs.umich.edu 1943804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1953804Ssaidi@eecs.umich.edu // one we just inserted 1963804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1973804Ssaidi@eecs.umich.edu clearUsedBits(); 1983804Ssaidi@eecs.umich.edu new_entry->used = true; 1993804Ssaidi@eecs.umich.edu usedEntries++; 2003804Ssaidi@eecs.umich.edu } 2013804Ssaidi@eecs.umich.edu 2023569Sgblack@eecs.umich.edu} 2033804Ssaidi@eecs.umich.edu 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.eduTlbEntry* 2064070Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id, bool 2074070Ssaidi@eecs.umich.edu update_used) 2083804Ssaidi@eecs.umich.edu{ 2093804Ssaidi@eecs.umich.edu MapIter i; 2103804Ssaidi@eecs.umich.edu TlbRange tr; 2113804Ssaidi@eecs.umich.edu TlbEntry *t; 2123804Ssaidi@eecs.umich.edu 2133811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2143811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2153804Ssaidi@eecs.umich.edu // Assemble full address structure 2163804Ssaidi@eecs.umich.edu tr.va = va; 2173863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2183804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2193804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2203804Ssaidi@eecs.umich.edu tr.real = real; 2213804Ssaidi@eecs.umich.edu 2223804Ssaidi@eecs.umich.edu // Try to find the entry 2233804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2243804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2253811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2263804Ssaidi@eecs.umich.edu return NULL; 2273804Ssaidi@eecs.umich.edu } 2283804Ssaidi@eecs.umich.edu 2293804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2303804Ssaidi@eecs.umich.edu t = i->second; 2313826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2323826Ssaidi@eecs.umich.edu t->pte.size()); 2334070Ssaidi@eecs.umich.edu 2344070Ssaidi@eecs.umich.edu // Update the used bits only if this is a real access (not a fake one from 2354070Ssaidi@eecs.umich.edu // virttophys() 2364070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2373804Ssaidi@eecs.umich.edu t->used = true; 2383804Ssaidi@eecs.umich.edu usedEntries++; 2393804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2403804Ssaidi@eecs.umich.edu clearUsedBits(); 2413804Ssaidi@eecs.umich.edu t->used = true; 2423804Ssaidi@eecs.umich.edu usedEntries++; 2433804Ssaidi@eecs.umich.edu } 2443804Ssaidi@eecs.umich.edu } 2453804Ssaidi@eecs.umich.edu 2463804Ssaidi@eecs.umich.edu return t; 2473804Ssaidi@eecs.umich.edu} 2483804Ssaidi@eecs.umich.edu 2493826Ssaidi@eecs.umich.eduvoid 2503826Ssaidi@eecs.umich.eduTLB::dumpAll() 2513826Ssaidi@eecs.umich.edu{ 2523863Ssaidi@eecs.umich.edu MapIter i; 2533826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2543826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2553826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2563826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2573826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2583826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2593826Ssaidi@eecs.umich.edu } 2603826Ssaidi@eecs.umich.edu } 2613826Ssaidi@eecs.umich.edu} 2623804Ssaidi@eecs.umich.edu 2633804Ssaidi@eecs.umich.eduvoid 2643804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2653804Ssaidi@eecs.umich.edu{ 2663804Ssaidi@eecs.umich.edu TlbRange tr; 2673804Ssaidi@eecs.umich.edu MapIter i; 2683804Ssaidi@eecs.umich.edu 2693863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2703863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2713863Ssaidi@eecs.umich.edu 2723836Ssaidi@eecs.umich.edu cacheValid = false; 2733836Ssaidi@eecs.umich.edu 2743804Ssaidi@eecs.umich.edu // Assemble full address structure 2753804Ssaidi@eecs.umich.edu tr.va = va; 2763863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2773804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2783804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2793804Ssaidi@eecs.umich.edu tr.real = real; 2803804Ssaidi@eecs.umich.edu 2813804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2823804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2833804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2843863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2853804Ssaidi@eecs.umich.edu i->second->valid = false; 2863804Ssaidi@eecs.umich.edu if (i->second->used) { 2873804Ssaidi@eecs.umich.edu i->second->used = false; 2883804Ssaidi@eecs.umich.edu usedEntries--; 2893804Ssaidi@eecs.umich.edu } 2903881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2913804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2923804Ssaidi@eecs.umich.edu } 2933804Ssaidi@eecs.umich.edu} 2943804Ssaidi@eecs.umich.edu 2953804Ssaidi@eecs.umich.eduvoid 2963804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2973804Ssaidi@eecs.umich.edu{ 2983804Ssaidi@eecs.umich.edu int x; 2993863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3003863Ssaidi@eecs.umich.edu partition_id, context_id); 3013836Ssaidi@eecs.umich.edu cacheValid = false; 3023804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3033804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3043804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3053881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3063881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3073881Ssaidi@eecs.umich.edu } 3083804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3093804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3103804Ssaidi@eecs.umich.edu tlb[x].used = false; 3113804Ssaidi@eecs.umich.edu usedEntries--; 3123804Ssaidi@eecs.umich.edu } 3133804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3143804Ssaidi@eecs.umich.edu } 3153804Ssaidi@eecs.umich.edu } 3163804Ssaidi@eecs.umich.edu} 3173804Ssaidi@eecs.umich.edu 3183804Ssaidi@eecs.umich.eduvoid 3193804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3203804Ssaidi@eecs.umich.edu{ 3213804Ssaidi@eecs.umich.edu int x; 3223863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3233836Ssaidi@eecs.umich.edu cacheValid = false; 3243804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3253804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3263881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3273881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3283881Ssaidi@eecs.umich.edu } 3293804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3303804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3313804Ssaidi@eecs.umich.edu tlb[x].used = false; 3323804Ssaidi@eecs.umich.edu usedEntries--; 3333804Ssaidi@eecs.umich.edu } 3343804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3353804Ssaidi@eecs.umich.edu } 3363804Ssaidi@eecs.umich.edu } 3373804Ssaidi@eecs.umich.edu} 3383804Ssaidi@eecs.umich.edu 3393804Ssaidi@eecs.umich.eduvoid 3403804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3413804Ssaidi@eecs.umich.edu{ 3423804Ssaidi@eecs.umich.edu int x; 3433836Ssaidi@eecs.umich.edu cacheValid = false; 3443836Ssaidi@eecs.umich.edu 3453881Ssaidi@eecs.umich.edu freeList.clear(); 3463907Ssaidi@eecs.umich.edu lookupTable.clear(); 3473804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3483881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3493881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3503804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3513907Ssaidi@eecs.umich.edu tlb[x].used = false; 3523804Ssaidi@eecs.umich.edu } 3533804Ssaidi@eecs.umich.edu usedEntries = 0; 3543804Ssaidi@eecs.umich.edu} 3553804Ssaidi@eecs.umich.edu 3563804Ssaidi@eecs.umich.eduuint64_t 3573804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3583881Ssaidi@eecs.umich.edu if (entry >= size) 3593881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3603881Ssaidi@eecs.umich.edu 3613804Ssaidi@eecs.umich.edu assert(entry < size); 3623881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3633881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3643881Ssaidi@eecs.umich.edu else 3653881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3663804Ssaidi@eecs.umich.edu} 3673804Ssaidi@eecs.umich.edu 3683804Ssaidi@eecs.umich.eduuint64_t 3693804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3703804Ssaidi@eecs.umich.edu assert(entry < size); 3713804Ssaidi@eecs.umich.edu uint64_t tag; 3723881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3733881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3743804Ssaidi@eecs.umich.edu 3753881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3763881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3773881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3783804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3793804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3803804Ssaidi@eecs.umich.edu return tag; 3813804Ssaidi@eecs.umich.edu} 3823804Ssaidi@eecs.umich.edu 3833804Ssaidi@eecs.umich.edubool 3843804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3853804Ssaidi@eecs.umich.edu{ 3863804Ssaidi@eecs.umich.edu if (am) 3873804Ssaidi@eecs.umich.edu return true; 3883804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3893804Ssaidi@eecs.umich.edu return false; 3903804Ssaidi@eecs.umich.edu return true; 3913804Ssaidi@eecs.umich.edu} 3923804Ssaidi@eecs.umich.edu 3933804Ssaidi@eecs.umich.eduvoid 3943804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3953804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3963804Ssaidi@eecs.umich.edu{ 3973804Ssaidi@eecs.umich.edu uint64_t sfsr; 3983804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 3993804Ssaidi@eecs.umich.edu 4003804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4013804Ssaidi@eecs.umich.edu sfsr = 0x3; 4023804Ssaidi@eecs.umich.edu else 4033804Ssaidi@eecs.umich.edu sfsr = 1; 4043804Ssaidi@eecs.umich.edu 4053804Ssaidi@eecs.umich.edu if (write) 4063804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4073804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4083804Ssaidi@eecs.umich.edu if (se) 4093804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4103804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4113804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4123826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 4133804Ssaidi@eecs.umich.edu} 4143804Ssaidi@eecs.umich.edu 4153826Ssaidi@eecs.umich.eduvoid 4163826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 4173826Ssaidi@eecs.umich.edu{ 4183916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4193916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4203916Ssaidi@eecs.umich.edu 4213826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 4223826Ssaidi@eecs.umich.edu} 4233804Ssaidi@eecs.umich.edu 4243804Ssaidi@eecs.umich.eduvoid 4253804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 4263804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4273804Ssaidi@eecs.umich.edu{ 4283811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4293811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4303804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 4313804Ssaidi@eecs.umich.edu} 4323804Ssaidi@eecs.umich.edu 4333804Ssaidi@eecs.umich.eduvoid 4343826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4353826Ssaidi@eecs.umich.edu{ 4363826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 4373826Ssaidi@eecs.umich.edu} 4383826Ssaidi@eecs.umich.edu 4393826Ssaidi@eecs.umich.eduvoid 4403804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 4413804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4423804Ssaidi@eecs.umich.edu{ 4433811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4443811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4453804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 4463826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 4473804Ssaidi@eecs.umich.edu} 4483804Ssaidi@eecs.umich.edu 4493836Ssaidi@eecs.umich.eduvoid 4503826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4513826Ssaidi@eecs.umich.edu{ 4523826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 4533826Ssaidi@eecs.umich.edu} 4543826Ssaidi@eecs.umich.edu 4553826Ssaidi@eecs.umich.edu 4563804Ssaidi@eecs.umich.edu 4573804Ssaidi@eecs.umich.eduFault 4583804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4593804Ssaidi@eecs.umich.edu{ 4603833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4613833Ssaidi@eecs.umich.edu 4623836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4633836Ssaidi@eecs.umich.edu TlbEntry *e; 4643836Ssaidi@eecs.umich.edu 4653836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4663836Ssaidi@eecs.umich.edu 4673836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4683836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4693836Ssaidi@eecs.umich.edu 4703836Ssaidi@eecs.umich.edu // Be fast if we can! 4713836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4723836Ssaidi@eecs.umich.edu if (cacheEntry) { 4733836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4743836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4753836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4763836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4773836Ssaidi@eecs.umich.edu return NoFault; 4783836Ssaidi@eecs.umich.edu } 4793836Ssaidi@eecs.umich.edu } else { 4803836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4813836Ssaidi@eecs.umich.edu return NoFault; 4823836Ssaidi@eecs.umich.edu } 4833836Ssaidi@eecs.umich.edu } 4843836Ssaidi@eecs.umich.edu 4853833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4863833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4873833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4883833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4893833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4903833Ssaidi@eecs.umich.edu 4913833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4923833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4933833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4943804Ssaidi@eecs.umich.edu int context; 4953804Ssaidi@eecs.umich.edu ContextType ct; 4963804Ssaidi@eecs.umich.edu int asi; 4973804Ssaidi@eecs.umich.edu bool real = false; 4983804Ssaidi@eecs.umich.edu 4993833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 5003833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 5013811Ssaidi@eecs.umich.edu 5023804Ssaidi@eecs.umich.edu if (tl > 0) { 5033804Ssaidi@eecs.umich.edu asi = ASI_N; 5043804Ssaidi@eecs.umich.edu ct = Nucleus; 5053804Ssaidi@eecs.umich.edu context = 0; 5063804Ssaidi@eecs.umich.edu } else { 5073804Ssaidi@eecs.umich.edu asi = ASI_P; 5083804Ssaidi@eecs.umich.edu ct = Primary; 5093833Ssaidi@eecs.umich.edu context = pri_context; 5103804Ssaidi@eecs.umich.edu } 5113804Ssaidi@eecs.umich.edu 5123833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5133836Ssaidi@eecs.umich.edu cacheValid = true; 5143836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5153836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5163836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5173804Ssaidi@eecs.umich.edu return NoFault; 5183804Ssaidi@eecs.umich.edu } 5193804Ssaidi@eecs.umich.edu 5203836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5213836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5223804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 5233804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5243804Ssaidi@eecs.umich.edu } 5253804Ssaidi@eecs.umich.edu 5263804Ssaidi@eecs.umich.edu if (addr_mask) 5273804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5283804Ssaidi@eecs.umich.edu 5293804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5303804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 5313804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5323804Ssaidi@eecs.umich.edu } 5333804Ssaidi@eecs.umich.edu 5343833Ssaidi@eecs.umich.edu if (!lsu_im) { 5353836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5363804Ssaidi@eecs.umich.edu real = true; 5373804Ssaidi@eecs.umich.edu context = 0; 5383804Ssaidi@eecs.umich.edu } else { 5393804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5403804Ssaidi@eecs.umich.edu } 5413804Ssaidi@eecs.umich.edu 5423804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5433916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5443804Ssaidi@eecs.umich.edu if (real) 5453804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5463804Ssaidi@eecs.umich.edu else 5473804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5483804Ssaidi@eecs.umich.edu } 5493804Ssaidi@eecs.umich.edu 5503804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5513804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5523928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5533804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 5543804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5553804Ssaidi@eecs.umich.edu } 5563804Ssaidi@eecs.umich.edu 5573836Ssaidi@eecs.umich.edu // cache translation date for next translation 5583836Ssaidi@eecs.umich.edu cacheValid = true; 5593836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5603836Ssaidi@eecs.umich.edu cacheEntry = e; 5613836Ssaidi@eecs.umich.edu 5623826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5633836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5643836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5653804Ssaidi@eecs.umich.edu return NoFault; 5663804Ssaidi@eecs.umich.edu} 5673804Ssaidi@eecs.umich.edu 5683804Ssaidi@eecs.umich.edu 5693804Ssaidi@eecs.umich.edu 5703804Ssaidi@eecs.umich.eduFault 5713804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5723804Ssaidi@eecs.umich.edu{ 5733804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5743833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 5753836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5763836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5773836Ssaidi@eecs.umich.edu ASI asi; 5783836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5793836Ssaidi@eecs.umich.edu bool implicit = false; 5803836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5813833Ssaidi@eecs.umich.edu 5823836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5833836Ssaidi@eecs.umich.edu vaddr, size, asi); 5843836Ssaidi@eecs.umich.edu 5853929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5863929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5873929Ssaidi@eecs.umich.edu freeList.size()); 5883836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5893836Ssaidi@eecs.umich.edu implicit = true; 5903836Ssaidi@eecs.umich.edu 5913836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 5923836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5933836Ssaidi@eecs.umich.edu return NoFault; 5943836Ssaidi@eecs.umich.edu } 5953836Ssaidi@eecs.umich.edu 5963836Ssaidi@eecs.umich.edu // Be fast if we can! 5973836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5983836Ssaidi@eecs.umich.edu if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 5993928Ssaidi@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr && 6003928Ssaidi@eecs.umich.edu (!write || cacheEntry[0]->pte.writable())) { 6013836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 6023836Ssaidi@eecs.umich.edu vaddr & cacheEntry[0]->pte.size()-1 ); 6033836Ssaidi@eecs.umich.edu return NoFault; 6043836Ssaidi@eecs.umich.edu } 6053836Ssaidi@eecs.umich.edu if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 6063928Ssaidi@eecs.umich.edu cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr && 6073928Ssaidi@eecs.umich.edu (!write || cacheEntry[1]->pte.writable())) { 6083836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 6093836Ssaidi@eecs.umich.edu vaddr & cacheEntry[1]->pte.size()-1 ); 6103836Ssaidi@eecs.umich.edu return NoFault; 6113836Ssaidi@eecs.umich.edu } 6123836Ssaidi@eecs.umich.edu } 6133836Ssaidi@eecs.umich.edu 6143833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6153833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6163833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6173833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6183833Ssaidi@eecs.umich.edu 6193833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6203833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6213833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6223916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6233833Ssaidi@eecs.umich.edu 6243804Ssaidi@eecs.umich.edu bool real = false; 6253832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6263832Ssaidi@eecs.umich.edu int context = 0; 6273804Ssaidi@eecs.umich.edu 6283804Ssaidi@eecs.umich.edu TlbEntry *e; 6293804Ssaidi@eecs.umich.edu 6303833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6313833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6323804Ssaidi@eecs.umich.edu 6333804Ssaidi@eecs.umich.edu if (implicit) { 6343804Ssaidi@eecs.umich.edu if (tl > 0) { 6353804Ssaidi@eecs.umich.edu asi = ASI_N; 6363804Ssaidi@eecs.umich.edu ct = Nucleus; 6373804Ssaidi@eecs.umich.edu context = 0; 6383804Ssaidi@eecs.umich.edu } else { 6393804Ssaidi@eecs.umich.edu asi = ASI_P; 6403804Ssaidi@eecs.umich.edu ct = Primary; 6413833Ssaidi@eecs.umich.edu context = pri_context; 6423804Ssaidi@eecs.umich.edu } 6433910Ssaidi@eecs.umich.edu } else { 6443804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6453910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6463804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6473804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6483804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6493804Ssaidi@eecs.umich.edu } 6503910Ssaidi@eecs.umich.edu 6513910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6523804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6533804Ssaidi@eecs.umich.edu return new DataAccessException; 6543804Ssaidi@eecs.umich.edu } 6553804Ssaidi@eecs.umich.edu 6563910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6573910Ssaidi@eecs.umich.edu context = pri_context; 6583910Ssaidi@eecs.umich.edu ct = Primary; 6593910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6603910Ssaidi@eecs.umich.edu context = sec_context; 6613910Ssaidi@eecs.umich.edu ct = Secondary; 6623910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6633910Ssaidi@eecs.umich.edu ct = Nucleus; 6643910Ssaidi@eecs.umich.edu context = 0; 6653910Ssaidi@eecs.umich.edu } else { // ???? 6663910Ssaidi@eecs.umich.edu ct = Primary; 6673910Ssaidi@eecs.umich.edu context = pri_context; 6683910Ssaidi@eecs.umich.edu } 6693902Ssaidi@eecs.umich.edu } 6703804Ssaidi@eecs.umich.edu 6713926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6723804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6733804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6743804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 6753804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 6763856Ssaidi@eecs.umich.edu 6773804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6783804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6793824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6803824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 6813823Ssaidi@eecs.umich.edu 6823804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6833804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6843804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6853804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6863824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6873824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6883825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 6893825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6903823Ssaidi@eecs.umich.edu 6913926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 6924010Ssaidi@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi)) 6933823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6943804Ssaidi@eecs.umich.edu } 6953804Ssaidi@eecs.umich.edu 6963826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6973826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 6983826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 6993826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7003826Ssaidi@eecs.umich.edu } 7013826Ssaidi@eecs.umich.edu 7023826Ssaidi@eecs.umich.edu if (addr_mask) 7033826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7043826Ssaidi@eecs.umich.edu 7053826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7063826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 7073826Ssaidi@eecs.umich.edu return new DataAccessException; 7083826Ssaidi@eecs.umich.edu } 7093826Ssaidi@eecs.umich.edu 7103826Ssaidi@eecs.umich.edu 7113910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7123804Ssaidi@eecs.umich.edu real = true; 7133804Ssaidi@eecs.umich.edu context = 0; 7143804Ssaidi@eecs.umich.edu }; 7153804Ssaidi@eecs.umich.edu 7163804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7173836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7183804Ssaidi@eecs.umich.edu return NoFault; 7193804Ssaidi@eecs.umich.edu } 7203804Ssaidi@eecs.umich.edu 7213836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7223804Ssaidi@eecs.umich.edu 7233804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7243916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7253811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7263804Ssaidi@eecs.umich.edu if (real) 7273804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7283804Ssaidi@eecs.umich.edu else 7293804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7303804Ssaidi@eecs.umich.edu 7313804Ssaidi@eecs.umich.edu } 7323804Ssaidi@eecs.umich.edu 7333928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7343928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7353928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7363928Ssaidi@eecs.umich.edu return new DataAccessException; 7373928Ssaidi@eecs.umich.edu } 7383804Ssaidi@eecs.umich.edu 7393804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7403928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7413804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7423804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7433804Ssaidi@eecs.umich.edu } 7443804Ssaidi@eecs.umich.edu 7453804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7463928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7473804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7483804Ssaidi@eecs.umich.edu return new DataAccessException; 7493804Ssaidi@eecs.umich.edu } 7503804Ssaidi@eecs.umich.edu 7513928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7523928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7533928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7543928Ssaidi@eecs.umich.edu return new DataAccessException; 7553928Ssaidi@eecs.umich.edu } 7563928Ssaidi@eecs.umich.edu 7573928Ssaidi@eecs.umich.edu 7583804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 7593804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7603804Ssaidi@eecs.umich.edu 7613836Ssaidi@eecs.umich.edu // cache translation date for next translation 7623836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7633881Ssaidi@eecs.umich.edu if (!cacheValid) { 7643881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7653881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7663881Ssaidi@eecs.umich.edu } 7673881Ssaidi@eecs.umich.edu 7683836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7693836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7703836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7713836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7723836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7733836Ssaidi@eecs.umich.edu if (implicit) 7743836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7753836Ssaidi@eecs.umich.edu } 7763881Ssaidi@eecs.umich.edu cacheValid = true; 7773826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 7783836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 7793836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7803804Ssaidi@eecs.umich.edu return NoFault; 7813806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7823804Ssaidi@eecs.umich.edu 7833806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7843806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7853806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7863806Ssaidi@eecs.umich.edu return new DataAccessException; 7873806Ssaidi@eecs.umich.edu } 7883824Ssaidi@eecs.umich.edu goto regAccessOk; 7893824Ssaidi@eecs.umich.edu 7903824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7913824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7923824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7933824Ssaidi@eecs.umich.edu return new PrivilegedAction; 7943824Ssaidi@eecs.umich.edu } 7953881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 7963824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7973824Ssaidi@eecs.umich.edu return new DataAccessException; 7983824Ssaidi@eecs.umich.edu } 7993824Ssaidi@eecs.umich.edu goto regAccessOk; 8003824Ssaidi@eecs.umich.edu 8013825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8023825Ssaidi@eecs.umich.edu if (!hpriv) { 8034070Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8044070Ssaidi@eecs.umich.edu if (priv) 8053825Ssaidi@eecs.umich.edu return new DataAccessException; 8064070Ssaidi@eecs.umich.edu else 8073825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8083825Ssaidi@eecs.umich.edu } 8093825Ssaidi@eecs.umich.edu goto regAccessOk; 8103825Ssaidi@eecs.umich.edu 8113825Ssaidi@eecs.umich.edu 8123824Ssaidi@eecs.umich.eduregAccessOk: 8133804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8143811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8153806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8163806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8173806Ssaidi@eecs.umich.edu return NoFault; 8183804Ssaidi@eecs.umich.edu}; 8193804Ssaidi@eecs.umich.edu 8203806Ssaidi@eecs.umich.eduTick 8213806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8223806Ssaidi@eecs.umich.edu{ 8233823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8243823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8254070Ssaidi@eecs.umich.edu uint64_t temp; 8263823Ssaidi@eecs.umich.edu 8273823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8283823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8293823Ssaidi@eecs.umich.edu 8303823Ssaidi@eecs.umich.edu switch (asi) { 8313823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8323823Ssaidi@eecs.umich.edu assert(va == 0); 8333823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 8343823Ssaidi@eecs.umich.edu break; 8353823Ssaidi@eecs.umich.edu case ASI_MMU: 8363823Ssaidi@eecs.umich.edu switch (va) { 8373823Ssaidi@eecs.umich.edu case 0x8: 8383823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 8393823Ssaidi@eecs.umich.edu break; 8403823Ssaidi@eecs.umich.edu case 0x10: 8413823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 8423823Ssaidi@eecs.umich.edu break; 8433823Ssaidi@eecs.umich.edu default: 8443823Ssaidi@eecs.umich.edu goto doMmuReadError; 8453823Ssaidi@eecs.umich.edu } 8463823Ssaidi@eecs.umich.edu break; 8473824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8483824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 8493824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8503824Ssaidi@eecs.umich.edu break; 8513823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8523823Ssaidi@eecs.umich.edu assert(va == 0); 8533823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 8543823Ssaidi@eecs.umich.edu break; 8553823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8563823Ssaidi@eecs.umich.edu assert(va == 0); 8573823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 8583823Ssaidi@eecs.umich.edu break; 8593823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8603823Ssaidi@eecs.umich.edu assert(va == 0); 8613823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 8623823Ssaidi@eecs.umich.edu break; 8633823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8643823Ssaidi@eecs.umich.edu assert(va == 0); 8653823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 8663823Ssaidi@eecs.umich.edu break; 8673823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8683823Ssaidi@eecs.umich.edu assert(va == 0); 8693823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 8703823Ssaidi@eecs.umich.edu break; 8713823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8723823Ssaidi@eecs.umich.edu assert(va == 0); 8733823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 8743823Ssaidi@eecs.umich.edu break; 8753823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 8763823Ssaidi@eecs.umich.edu assert(va == 0); 8773823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 8783823Ssaidi@eecs.umich.edu break; 8793823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 8803823Ssaidi@eecs.umich.edu assert(va == 0); 8813823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 8823823Ssaidi@eecs.umich.edu break; 8833823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 8843823Ssaidi@eecs.umich.edu assert(va == 0); 8853823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 8863823Ssaidi@eecs.umich.edu break; 8873823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 8883823Ssaidi@eecs.umich.edu assert(va == 0); 8893823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 8903823Ssaidi@eecs.umich.edu break; 8913823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 8923823Ssaidi@eecs.umich.edu assert(va == 0); 8933823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 8943823Ssaidi@eecs.umich.edu break; 8953823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8963823Ssaidi@eecs.umich.edu assert(va == 0); 8973823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 8983823Ssaidi@eecs.umich.edu break; 8993826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9003912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9013826Ssaidi@eecs.umich.edu break; 9023823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9033823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9043823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9053823Ssaidi@eecs.umich.edu break; 9063826Ssaidi@eecs.umich.edu case ASI_IMMU: 9073826Ssaidi@eecs.umich.edu switch (va) { 9083833Ssaidi@eecs.umich.edu case 0x0: 9093833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9103833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9113833Ssaidi@eecs.umich.edu break; 9123906Ssaidi@eecs.umich.edu case 0x18: 9133906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 9143906Ssaidi@eecs.umich.edu break; 9153826Ssaidi@eecs.umich.edu case 0x30: 9163826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 9173826Ssaidi@eecs.umich.edu break; 9183826Ssaidi@eecs.umich.edu default: 9193826Ssaidi@eecs.umich.edu goto doMmuReadError; 9203826Ssaidi@eecs.umich.edu } 9213826Ssaidi@eecs.umich.edu break; 9223823Ssaidi@eecs.umich.edu case ASI_DMMU: 9233823Ssaidi@eecs.umich.edu switch (va) { 9243833Ssaidi@eecs.umich.edu case 0x0: 9253833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9263833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9273833Ssaidi@eecs.umich.edu break; 9283906Ssaidi@eecs.umich.edu case 0x18: 9293906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 9303906Ssaidi@eecs.umich.edu break; 9313906Ssaidi@eecs.umich.edu case 0x20: 9323906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 9333906Ssaidi@eecs.umich.edu break; 9343826Ssaidi@eecs.umich.edu case 0x30: 9353826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 9363826Ssaidi@eecs.umich.edu break; 9373823Ssaidi@eecs.umich.edu case 0x80: 9383823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 9393823Ssaidi@eecs.umich.edu break; 9403823Ssaidi@eecs.umich.edu default: 9413823Ssaidi@eecs.umich.edu goto doMmuReadError; 9423823Ssaidi@eecs.umich.edu } 9433823Ssaidi@eecs.umich.edu break; 9443833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9454070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9464070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), 9474070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), 9484070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 9494070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), 9504070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); 9513833Ssaidi@eecs.umich.edu break; 9523833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9534070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9544070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), 9554070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), 9564070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 9574070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), 9584070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); 9593833Ssaidi@eecs.umich.edu break; 9603899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9614070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9624070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), 9634070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), 9644070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 9654070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), 9664070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); 9673899Ssaidi@eecs.umich.edu break; 9683899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 9694070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9704070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), 9714070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), 9724070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 9734070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), 9744070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); 9753899Ssaidi@eecs.umich.edu break; 9763833Ssaidi@eecs.umich.edu 9773823Ssaidi@eecs.umich.edu default: 9783823Ssaidi@eecs.umich.edudoMmuReadError: 9793823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 9803823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 9813823Ssaidi@eecs.umich.edu } 9823823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 9833823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 9843806Ssaidi@eecs.umich.edu} 9853806Ssaidi@eecs.umich.edu 9863806Ssaidi@eecs.umich.eduTick 9873806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 9883806Ssaidi@eecs.umich.edu{ 9893823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 9903823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 9913823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 9923823Ssaidi@eecs.umich.edu 9933826Ssaidi@eecs.umich.edu Addr ta_insert; 9943826Ssaidi@eecs.umich.edu Addr va_insert; 9953826Ssaidi@eecs.umich.edu Addr ct_insert; 9963826Ssaidi@eecs.umich.edu int part_insert; 9973826Ssaidi@eecs.umich.edu int entry_insert = -1; 9983826Ssaidi@eecs.umich.edu bool real_insert; 9993863Ssaidi@eecs.umich.edu bool ignore; 10003863Ssaidi@eecs.umich.edu int part_id; 10013863Ssaidi@eecs.umich.edu int ctx_id; 10023826Ssaidi@eecs.umich.edu PageTableEntry pte; 10033826Ssaidi@eecs.umich.edu 10043825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10053823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10063823Ssaidi@eecs.umich.edu 10073823Ssaidi@eecs.umich.edu switch (asi) { 10083823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10093823Ssaidi@eecs.umich.edu assert(va == 0); 10103823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 10113823Ssaidi@eecs.umich.edu break; 10123823Ssaidi@eecs.umich.edu case ASI_MMU: 10133823Ssaidi@eecs.umich.edu switch (va) { 10143823Ssaidi@eecs.umich.edu case 0x8: 10153823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 10163823Ssaidi@eecs.umich.edu break; 10173823Ssaidi@eecs.umich.edu case 0x10: 10183823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 10193823Ssaidi@eecs.umich.edu break; 10203823Ssaidi@eecs.umich.edu default: 10213823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10223823Ssaidi@eecs.umich.edu } 10233823Ssaidi@eecs.umich.edu break; 10243824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10253825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10263824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 10273824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10283824Ssaidi@eecs.umich.edu break; 10293823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10303823Ssaidi@eecs.umich.edu assert(va == 0); 10313823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 10323823Ssaidi@eecs.umich.edu break; 10333823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10343823Ssaidi@eecs.umich.edu assert(va == 0); 10353823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 10363823Ssaidi@eecs.umich.edu break; 10373823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10383823Ssaidi@eecs.umich.edu assert(va == 0); 10393823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 10403823Ssaidi@eecs.umich.edu break; 10413823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10423823Ssaidi@eecs.umich.edu assert(va == 0); 10433823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 10443823Ssaidi@eecs.umich.edu break; 10453823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10463823Ssaidi@eecs.umich.edu assert(va == 0); 10473823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 10483823Ssaidi@eecs.umich.edu break; 10493823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10503823Ssaidi@eecs.umich.edu assert(va == 0); 10513823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 10523823Ssaidi@eecs.umich.edu break; 10533823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 10543823Ssaidi@eecs.umich.edu assert(va == 0); 10553823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 10563823Ssaidi@eecs.umich.edu break; 10573823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 10583823Ssaidi@eecs.umich.edu assert(va == 0); 10593823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 10603823Ssaidi@eecs.umich.edu break; 10613823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 10623823Ssaidi@eecs.umich.edu assert(va == 0); 10633823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 10643823Ssaidi@eecs.umich.edu break; 10653823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 10663823Ssaidi@eecs.umich.edu assert(va == 0); 10673823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 10683823Ssaidi@eecs.umich.edu break; 10693823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 10703823Ssaidi@eecs.umich.edu assert(va == 0); 10713823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 10723823Ssaidi@eecs.umich.edu break; 10733823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 10743823Ssaidi@eecs.umich.edu assert(va == 0); 10753823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 10763823Ssaidi@eecs.umich.edu break; 10773825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 10783825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 10793825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 10803825Ssaidi@eecs.umich.edu break; 10813823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 10823823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 10833823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 10843823Ssaidi@eecs.umich.edu break; 10853826Ssaidi@eecs.umich.edu case ASI_IMMU: 10863826Ssaidi@eecs.umich.edu switch (va) { 10873906Ssaidi@eecs.umich.edu case 0x18: 10883906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 10893906Ssaidi@eecs.umich.edu break; 10903826Ssaidi@eecs.umich.edu case 0x30: 10913916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 10923826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 10933826Ssaidi@eecs.umich.edu break; 10943826Ssaidi@eecs.umich.edu default: 10953826Ssaidi@eecs.umich.edu goto doMmuWriteError; 10963826Ssaidi@eecs.umich.edu } 10973826Ssaidi@eecs.umich.edu break; 10983826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 10993826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11003826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11013826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11023826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 11033826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11043826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11053826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11063826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11073826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11083826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11093826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11103826Ssaidi@eecs.umich.edu pte, entry_insert); 11113826Ssaidi@eecs.umich.edu break; 11123826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11133826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11143826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11153826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11163826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 11173826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11183826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11193826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11203826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11213826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11223826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11233826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11243826Ssaidi@eecs.umich.edu break; 11253863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11263863Ssaidi@eecs.umich.edu ignore = false; 11273863Ssaidi@eecs.umich.edu ctx_id = -1; 11283863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11293863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11303863Ssaidi@eecs.umich.edu case 0: 11313863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 11323863Ssaidi@eecs.umich.edu break; 11333863Ssaidi@eecs.umich.edu case 1: 11343863Ssaidi@eecs.umich.edu ignore = true; 11353863Ssaidi@eecs.umich.edu break; 11363863Ssaidi@eecs.umich.edu case 3: 11373863Ssaidi@eecs.umich.edu ctx_id = 0; 11383863Ssaidi@eecs.umich.edu break; 11393863Ssaidi@eecs.umich.edu default: 11403863Ssaidi@eecs.umich.edu ignore = true; 11413863Ssaidi@eecs.umich.edu } 11423863Ssaidi@eecs.umich.edu 11433863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11443863Ssaidi@eecs.umich.edu case 0: // demap page 11453863Ssaidi@eecs.umich.edu if (!ignore) 11463863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11473863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11483863Ssaidi@eecs.umich.edu break; 11493863Ssaidi@eecs.umich.edu case 1: //demap context 11503863Ssaidi@eecs.umich.edu if (!ignore) 11513863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11523863Ssaidi@eecs.umich.edu break; 11533863Ssaidi@eecs.umich.edu case 2: 11543863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 11553863Ssaidi@eecs.umich.edu break; 11563863Ssaidi@eecs.umich.edu default: 11573863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 11583863Ssaidi@eecs.umich.edu } 11593863Ssaidi@eecs.umich.edu break; 11603823Ssaidi@eecs.umich.edu case ASI_DMMU: 11613823Ssaidi@eecs.umich.edu switch (va) { 11623906Ssaidi@eecs.umich.edu case 0x18: 11633906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 11643906Ssaidi@eecs.umich.edu break; 11653826Ssaidi@eecs.umich.edu case 0x30: 11663916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11673826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 11683826Ssaidi@eecs.umich.edu break; 11693823Ssaidi@eecs.umich.edu case 0x80: 11703823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 11713823Ssaidi@eecs.umich.edu break; 11723823Ssaidi@eecs.umich.edu default: 11733823Ssaidi@eecs.umich.edu goto doMmuWriteError; 11743823Ssaidi@eecs.umich.edu } 11753823Ssaidi@eecs.umich.edu break; 11763863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 11773863Ssaidi@eecs.umich.edu ignore = false; 11783863Ssaidi@eecs.umich.edu ctx_id = -1; 11793863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11803863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11813863Ssaidi@eecs.umich.edu case 0: 11823863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 11833863Ssaidi@eecs.umich.edu break; 11843863Ssaidi@eecs.umich.edu case 1: 11853863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 11863863Ssaidi@eecs.umich.edu break; 11873863Ssaidi@eecs.umich.edu case 3: 11883863Ssaidi@eecs.umich.edu ctx_id = 0; 11893863Ssaidi@eecs.umich.edu break; 11903863Ssaidi@eecs.umich.edu default: 11913863Ssaidi@eecs.umich.edu ignore = true; 11923863Ssaidi@eecs.umich.edu } 11933863Ssaidi@eecs.umich.edu 11943863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11953863Ssaidi@eecs.umich.edu case 0: // demap page 11963863Ssaidi@eecs.umich.edu if (!ignore) 11973863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 11983863Ssaidi@eecs.umich.edu break; 11993863Ssaidi@eecs.umich.edu case 1: //demap context 12003863Ssaidi@eecs.umich.edu if (!ignore) 12013863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12023863Ssaidi@eecs.umich.edu break; 12033863Ssaidi@eecs.umich.edu case 2: 12043863Ssaidi@eecs.umich.edu demapAll(part_id); 12053863Ssaidi@eecs.umich.edu break; 12063863Ssaidi@eecs.umich.edu default: 12073863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12083863Ssaidi@eecs.umich.edu } 12093863Ssaidi@eecs.umich.edu break; 12103823Ssaidi@eecs.umich.edu default: 12113823Ssaidi@eecs.umich.edudoMmuWriteError: 12123823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12133823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12143823Ssaidi@eecs.umich.edu } 12153823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 12163823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 12173806Ssaidi@eecs.umich.edu} 12183806Ssaidi@eecs.umich.edu 12193804Ssaidi@eecs.umich.eduvoid 12204070Ssaidi@eecs.umich.eduDTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12214070Ssaidi@eecs.umich.edu{ 12224070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12234070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12244070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), 12254070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 12264070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), 12274070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 12284070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 12294070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), 12304070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), 12314070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), 12324070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 12334070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 12344070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), 12354070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 12364070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), 12374070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 12384070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 12394070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), 12404070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), 12414070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), 12424070Ssaidi@eecs.umich.edu tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 12434070Ssaidi@eecs.umich.edu} 12444070Ssaidi@eecs.umich.edu 12454070Ssaidi@eecs.umich.edu 12464070Ssaidi@eecs.umich.edu 12474070Ssaidi@eecs.umich.edu 12484070Ssaidi@eecs.umich.edu 12494070Ssaidi@eecs.umich.eduuint64_t 12504070Ssaidi@eecs.umich.eduDTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 12514070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 12524070Ssaidi@eecs.umich.edu{ 12534070Ssaidi@eecs.umich.edu uint64_t tsb; 12544070Ssaidi@eecs.umich.edu uint64_t config; 12554070Ssaidi@eecs.umich.edu 12564070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 12574070Ssaidi@eecs.umich.edu tsb = c0_tsb; 12584070Ssaidi@eecs.umich.edu config = c0_config; 12594070Ssaidi@eecs.umich.edu } else { 12604070Ssaidi@eecs.umich.edu tsb = cX_tsb; 12614070Ssaidi@eecs.umich.edu config = cX_config; 12624070Ssaidi@eecs.umich.edu } 12634070Ssaidi@eecs.umich.edu 12644070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 12654070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 12664070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 12674070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 12684070Ssaidi@eecs.umich.edu 12694070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 12704070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 12714070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 12724070Ssaidi@eecs.umich.edu 12734070Ssaidi@eecs.umich.edu return ptr; 12744070Ssaidi@eecs.umich.edu} 12754070Ssaidi@eecs.umich.edu 12764070Ssaidi@eecs.umich.edu 12774070Ssaidi@eecs.umich.eduvoid 12783804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 12793804Ssaidi@eecs.umich.edu{ 12804000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 12814000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 12824000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 12834000Ssaidi@eecs.umich.edu 12844000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 12854000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 12864000Ssaidi@eecs.umich.edu int cntr = 0; 12874000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 12884000Ssaidi@eecs.umich.edu i = freeList.begin(); 12894000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 12904000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 12914000Ssaidi@eecs.umich.edu i++; 12924000Ssaidi@eecs.umich.edu } 12934000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 12944000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 12954000Ssaidi@eecs.umich.edu 12964000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 12974000Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 12984000Ssaidi@eecs.umich.edu tlb[x].serialize(os); 12994000Ssaidi@eecs.umich.edu } 13003804Ssaidi@eecs.umich.edu} 13013804Ssaidi@eecs.umich.edu 13023804Ssaidi@eecs.umich.eduvoid 13033804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13043804Ssaidi@eecs.umich.edu{ 13054000Ssaidi@eecs.umich.edu int oldSize; 13064000Ssaidi@eecs.umich.edu 13074000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13084000Ssaidi@eecs.umich.edu if (oldSize != size) 13094000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13104000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13114000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13124000Ssaidi@eecs.umich.edu 13134000Ssaidi@eecs.umich.edu int cntr; 13144000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13154000Ssaidi@eecs.umich.edu 13164000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13174000Ssaidi@eecs.umich.edu freeList.clear(); 13184000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13194000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13204000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 13214000Ssaidi@eecs.umich.edu 13224000Ssaidi@eecs.umich.edu lookupTable.clear(); 13234000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13244000Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 13254000Ssaidi@eecs.umich.edu if (tlb[x].valid) 13264000Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 13274000Ssaidi@eecs.umich.edu 13284000Ssaidi@eecs.umich.edu } 13293804Ssaidi@eecs.umich.edu} 13303804Ssaidi@eecs.umich.edu 13314088Sbinkertn@umich.edu/* end namespace SparcISA */ } 13324088Sbinkertn@umich.edu 13334088Sbinkertn@umich.eduusing namespace SparcISA; 13343804Ssaidi@eecs.umich.edu 13353804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 13363804Ssaidi@eecs.umich.edu 13373804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 13383804Ssaidi@eecs.umich.edu 13393804Ssaidi@eecs.umich.edu Param<int> size; 13403804Ssaidi@eecs.umich.edu 13413804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 13423804Ssaidi@eecs.umich.edu 13433804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 13443804Ssaidi@eecs.umich.edu 13453804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 13463804Ssaidi@eecs.umich.edu 13473804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 13483804Ssaidi@eecs.umich.edu 13493804Ssaidi@eecs.umich.edu 13503804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 13513804Ssaidi@eecs.umich.edu{ 13523804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 13533804Ssaidi@eecs.umich.edu} 13543804Ssaidi@eecs.umich.edu 13553804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 13563804Ssaidi@eecs.umich.edu 13573804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 13583804Ssaidi@eecs.umich.edu 13593804Ssaidi@eecs.umich.edu Param<int> size; 13603804Ssaidi@eecs.umich.edu 13613804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 13623804Ssaidi@eecs.umich.edu 13633804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 13643804Ssaidi@eecs.umich.edu 13653804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 13663804Ssaidi@eecs.umich.edu 13673804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 13683804Ssaidi@eecs.umich.edu 13693804Ssaidi@eecs.umich.edu 13703804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 13713804Ssaidi@eecs.umich.edu{ 13723804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 13733804Ssaidi@eecs.umich.edu} 13743804Ssaidi@eecs.umich.edu 13753804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 1376