tlb.cc revision 3863
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 353811Ssaidi@eecs.umich.edu#include "base/trace.hh" 363811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 373823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 383823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 393823Ssaidi@eecs.umich.edu#include "mem/request.hh" 403569Sgblack@eecs.umich.edu#include "sim/builder.hh" 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 433804Ssaidi@eecs.umich.edu * */ 443569Sgblack@eecs.umich.edunamespace SparcISA 453569Sgblack@eecs.umich.edu{ 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 483836Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), cacheValid(false) 493804Ssaidi@eecs.umich.edu{ 503804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 513804Ssaidi@eecs.umich.edu if (size > 64) 523804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 533569Sgblack@eecs.umich.edu 543804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 553804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 563804Ssaidi@eecs.umich.edu} 573569Sgblack@eecs.umich.edu 583804Ssaidi@eecs.umich.eduvoid 593804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 603804Ssaidi@eecs.umich.edu{ 613804Ssaidi@eecs.umich.edu MapIter i; 623804Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end();) { 633804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 643804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 653804Ssaidi@eecs.umich.edu t->used = false; 663804Ssaidi@eecs.umich.edu usedEntries--; 673804Ssaidi@eecs.umich.edu } 683804Ssaidi@eecs.umich.edu } 693804Ssaidi@eecs.umich.edu} 703569Sgblack@eecs.umich.edu 713569Sgblack@eecs.umich.edu 723804Ssaidi@eecs.umich.eduvoid 733804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 743826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 753804Ssaidi@eecs.umich.edu{ 763569Sgblack@eecs.umich.edu 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.edu MapIter i; 793826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 803826Ssaidi@eecs.umich.edu int x; 813811Ssaidi@eecs.umich.edu 823836Ssaidi@eecs.umich.edu cacheValid = false; 833836Ssaidi@eecs.umich.edu 843826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", 853826Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real); 863811Ssaidi@eecs.umich.edu 873826Ssaidi@eecs.umich.edu if (entry != -1) { 883826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 893826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 903826Ssaidi@eecs.umich.edu } else { 913826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 923826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 933826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 943826Ssaidi@eecs.umich.edu break; 953826Ssaidi@eecs.umich.edu } 963804Ssaidi@eecs.umich.edu } 973569Sgblack@eecs.umich.edu } 983569Sgblack@eecs.umich.edu 993804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1003826Ssaidi@eecs.umich.edu if (!new_entry) 1013826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1023569Sgblack@eecs.umich.edu 1033804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1043804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1053804Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size(); 1063804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1073804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1083804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1093804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1103804Ssaidi@eecs.umich.edu new_entry->used = true;; 1113804Ssaidi@eecs.umich.edu new_entry->valid = true; 1123804Ssaidi@eecs.umich.edu usedEntries++; 1133569Sgblack@eecs.umich.edu 1143569Sgblack@eecs.umich.edu 1153804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1163804Ssaidi@eecs.umich.edu i = lookupTable.find(new_entry->range); 1173804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1183804Ssaidi@eecs.umich.edu i->second->valid = false; 1193804Ssaidi@eecs.umich.edu if (i->second->used) { 1203804Ssaidi@eecs.umich.edu i->second->used = false; 1213804Ssaidi@eecs.umich.edu usedEntries--; 1223804Ssaidi@eecs.umich.edu } 1233811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); 1243804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1253569Sgblack@eecs.umich.edu } 1263569Sgblack@eecs.umich.edu 1273863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1283863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1293804Ssaidi@eecs.umich.edu 1303804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1313804Ssaidi@eecs.umich.edu // one we just inserted 1323804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1333804Ssaidi@eecs.umich.edu clearUsedBits(); 1343804Ssaidi@eecs.umich.edu new_entry->used = true; 1353804Ssaidi@eecs.umich.edu usedEntries++; 1363804Ssaidi@eecs.umich.edu } 1373804Ssaidi@eecs.umich.edu 1383569Sgblack@eecs.umich.edu} 1393804Ssaidi@eecs.umich.edu 1403804Ssaidi@eecs.umich.edu 1413804Ssaidi@eecs.umich.eduTlbEntry* 1423804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 1433804Ssaidi@eecs.umich.edu{ 1443804Ssaidi@eecs.umich.edu MapIter i; 1453804Ssaidi@eecs.umich.edu TlbRange tr; 1463804Ssaidi@eecs.umich.edu TlbEntry *t; 1473804Ssaidi@eecs.umich.edu 1483811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 1493811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 1503804Ssaidi@eecs.umich.edu // Assemble full address structure 1513804Ssaidi@eecs.umich.edu tr.va = va; 1523863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 1533804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1543804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1553804Ssaidi@eecs.umich.edu tr.real = real; 1563804Ssaidi@eecs.umich.edu 1573804Ssaidi@eecs.umich.edu // Try to find the entry 1583804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1593804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 1603811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 1613804Ssaidi@eecs.umich.edu return NULL; 1623804Ssaidi@eecs.umich.edu } 1633804Ssaidi@eecs.umich.edu 1643804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 1653804Ssaidi@eecs.umich.edu t = i->second; 1663826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 1673826Ssaidi@eecs.umich.edu t->pte.size()); 1683804Ssaidi@eecs.umich.edu if (!t->used) { 1693804Ssaidi@eecs.umich.edu t->used = true; 1703804Ssaidi@eecs.umich.edu usedEntries++; 1713804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1723804Ssaidi@eecs.umich.edu clearUsedBits(); 1733804Ssaidi@eecs.umich.edu t->used = true; 1743804Ssaidi@eecs.umich.edu usedEntries++; 1753804Ssaidi@eecs.umich.edu } 1763804Ssaidi@eecs.umich.edu } 1773804Ssaidi@eecs.umich.edu 1783804Ssaidi@eecs.umich.edu return t; 1793804Ssaidi@eecs.umich.edu} 1803804Ssaidi@eecs.umich.edu 1813826Ssaidi@eecs.umich.eduvoid 1823826Ssaidi@eecs.umich.eduTLB::dumpAll() 1833826Ssaidi@eecs.umich.edu{ 1843863Ssaidi@eecs.umich.edu MapIter i; 1853826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 1863826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1873826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 1883826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 1893826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 1903826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 1913826Ssaidi@eecs.umich.edu } 1923826Ssaidi@eecs.umich.edu } 1933826Ssaidi@eecs.umich.edu} 1943804Ssaidi@eecs.umich.edu 1953804Ssaidi@eecs.umich.eduvoid 1963804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 1973804Ssaidi@eecs.umich.edu{ 1983804Ssaidi@eecs.umich.edu TlbRange tr; 1993804Ssaidi@eecs.umich.edu MapIter i; 2003804Ssaidi@eecs.umich.edu 2013863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2023863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2033863Ssaidi@eecs.umich.edu 2043836Ssaidi@eecs.umich.edu cacheValid = false; 2053836Ssaidi@eecs.umich.edu 2063804Ssaidi@eecs.umich.edu // Assemble full address structure 2073804Ssaidi@eecs.umich.edu tr.va = va; 2083863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2093804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2103804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2113804Ssaidi@eecs.umich.edu tr.real = real; 2123804Ssaidi@eecs.umich.edu 2133804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2143804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2153804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2163863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2173804Ssaidi@eecs.umich.edu i->second->valid = false; 2183804Ssaidi@eecs.umich.edu if (i->second->used) { 2193804Ssaidi@eecs.umich.edu i->second->used = false; 2203804Ssaidi@eecs.umich.edu usedEntries--; 2213804Ssaidi@eecs.umich.edu } 2223804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2233804Ssaidi@eecs.umich.edu } 2243804Ssaidi@eecs.umich.edu} 2253804Ssaidi@eecs.umich.edu 2263804Ssaidi@eecs.umich.eduvoid 2273804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2283804Ssaidi@eecs.umich.edu{ 2293804Ssaidi@eecs.umich.edu int x; 2303863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2313863Ssaidi@eecs.umich.edu partition_id, context_id); 2323836Ssaidi@eecs.umich.edu cacheValid = false; 2333804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2343804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2353804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2363804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2373804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2383804Ssaidi@eecs.umich.edu tlb[x].used = false; 2393804Ssaidi@eecs.umich.edu usedEntries--; 2403804Ssaidi@eecs.umich.edu } 2413804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2423804Ssaidi@eecs.umich.edu } 2433804Ssaidi@eecs.umich.edu } 2443804Ssaidi@eecs.umich.edu} 2453804Ssaidi@eecs.umich.edu 2463804Ssaidi@eecs.umich.eduvoid 2473804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 2483804Ssaidi@eecs.umich.edu{ 2493804Ssaidi@eecs.umich.edu int x; 2503863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 2513836Ssaidi@eecs.umich.edu cacheValid = false; 2523804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2533804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 2543804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2553804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2563804Ssaidi@eecs.umich.edu tlb[x].used = false; 2573804Ssaidi@eecs.umich.edu usedEntries--; 2583804Ssaidi@eecs.umich.edu } 2593804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2603804Ssaidi@eecs.umich.edu } 2613804Ssaidi@eecs.umich.edu } 2623804Ssaidi@eecs.umich.edu} 2633804Ssaidi@eecs.umich.edu 2643804Ssaidi@eecs.umich.eduvoid 2653804Ssaidi@eecs.umich.eduTLB::invalidateAll() 2663804Ssaidi@eecs.umich.edu{ 2673804Ssaidi@eecs.umich.edu int x; 2683836Ssaidi@eecs.umich.edu cacheValid = false; 2693836Ssaidi@eecs.umich.edu 2703804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2713804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2723804Ssaidi@eecs.umich.edu } 2733804Ssaidi@eecs.umich.edu usedEntries = 0; 2743804Ssaidi@eecs.umich.edu} 2753804Ssaidi@eecs.umich.edu 2763804Ssaidi@eecs.umich.eduuint64_t 2773804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 2783804Ssaidi@eecs.umich.edu assert(entry < size); 2793804Ssaidi@eecs.umich.edu return tlb[entry].pte(); 2803804Ssaidi@eecs.umich.edu} 2813804Ssaidi@eecs.umich.edu 2823804Ssaidi@eecs.umich.eduuint64_t 2833804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 2843804Ssaidi@eecs.umich.edu assert(entry < size); 2853804Ssaidi@eecs.umich.edu uint64_t tag; 2863804Ssaidi@eecs.umich.edu 2873804Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId | tlb[entry].range.va | 2883804Ssaidi@eecs.umich.edu (uint64_t)tlb[entry].range.partitionId << 61; 2893804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 2903804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 2913804Ssaidi@eecs.umich.edu return tag; 2923804Ssaidi@eecs.umich.edu} 2933804Ssaidi@eecs.umich.edu 2943804Ssaidi@eecs.umich.edubool 2953804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 2963804Ssaidi@eecs.umich.edu{ 2973804Ssaidi@eecs.umich.edu if (am) 2983804Ssaidi@eecs.umich.edu return true; 2993804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3003804Ssaidi@eecs.umich.edu return false; 3013804Ssaidi@eecs.umich.edu return true; 3023804Ssaidi@eecs.umich.edu} 3033804Ssaidi@eecs.umich.edu 3043804Ssaidi@eecs.umich.eduvoid 3053804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3063804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3073804Ssaidi@eecs.umich.edu{ 3083804Ssaidi@eecs.umich.edu uint64_t sfsr; 3093804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 3103804Ssaidi@eecs.umich.edu 3113804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3123804Ssaidi@eecs.umich.edu sfsr = 0x3; 3133804Ssaidi@eecs.umich.edu else 3143804Ssaidi@eecs.umich.edu sfsr = 1; 3153804Ssaidi@eecs.umich.edu 3163804Ssaidi@eecs.umich.edu if (write) 3173804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3183804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3193804Ssaidi@eecs.umich.edu if (se) 3203804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3213804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3223804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3233826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 3243804Ssaidi@eecs.umich.edu} 3253804Ssaidi@eecs.umich.edu 3263826Ssaidi@eecs.umich.eduvoid 3273826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 3283826Ssaidi@eecs.umich.edu{ 3293826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 3303826Ssaidi@eecs.umich.edu} 3313804Ssaidi@eecs.umich.edu 3323804Ssaidi@eecs.umich.eduvoid 3333804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 3343804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3353804Ssaidi@eecs.umich.edu{ 3363811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 3373811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 3383804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 3393804Ssaidi@eecs.umich.edu} 3403804Ssaidi@eecs.umich.edu 3413804Ssaidi@eecs.umich.eduvoid 3423826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3433826Ssaidi@eecs.umich.edu{ 3443826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 3453826Ssaidi@eecs.umich.edu} 3463826Ssaidi@eecs.umich.edu 3473826Ssaidi@eecs.umich.eduvoid 3483804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 3493804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3503804Ssaidi@eecs.umich.edu{ 3513811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 3523811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 3533804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 3543826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 3553804Ssaidi@eecs.umich.edu} 3563804Ssaidi@eecs.umich.edu 3573836Ssaidi@eecs.umich.eduvoid 3583826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3593826Ssaidi@eecs.umich.edu{ 3603826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 3613826Ssaidi@eecs.umich.edu} 3623826Ssaidi@eecs.umich.edu 3633826Ssaidi@eecs.umich.edu 3643804Ssaidi@eecs.umich.edu 3653804Ssaidi@eecs.umich.eduFault 3663804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3673804Ssaidi@eecs.umich.edu{ 3683833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 3693833Ssaidi@eecs.umich.edu 3703836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 3713836Ssaidi@eecs.umich.edu TlbEntry *e; 3723836Ssaidi@eecs.umich.edu 3733836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 3743836Ssaidi@eecs.umich.edu 3753836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 3763836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 3773836Ssaidi@eecs.umich.edu 3783836Ssaidi@eecs.umich.edu // Be fast if we can! 3793836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 3803836Ssaidi@eecs.umich.edu if (cacheEntry) { 3813836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 3823836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 3833836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 3843836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 3853836Ssaidi@eecs.umich.edu return NoFault; 3863836Ssaidi@eecs.umich.edu } 3873836Ssaidi@eecs.umich.edu } else { 3883836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 3893836Ssaidi@eecs.umich.edu return NoFault; 3903836Ssaidi@eecs.umich.edu } 3913836Ssaidi@eecs.umich.edu } 3923836Ssaidi@eecs.umich.edu 3933833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 3943833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 3953833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 3963833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 3973833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 3983833Ssaidi@eecs.umich.edu 3993833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4003833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4013833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4023804Ssaidi@eecs.umich.edu int context; 4033804Ssaidi@eecs.umich.edu ContextType ct; 4043804Ssaidi@eecs.umich.edu int asi; 4053804Ssaidi@eecs.umich.edu bool real = false; 4063804Ssaidi@eecs.umich.edu 4073833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4083833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4093811Ssaidi@eecs.umich.edu 4103804Ssaidi@eecs.umich.edu if (tl > 0) { 4113804Ssaidi@eecs.umich.edu asi = ASI_N; 4123804Ssaidi@eecs.umich.edu ct = Nucleus; 4133804Ssaidi@eecs.umich.edu context = 0; 4143804Ssaidi@eecs.umich.edu } else { 4153804Ssaidi@eecs.umich.edu asi = ASI_P; 4163804Ssaidi@eecs.umich.edu ct = Primary; 4173833Ssaidi@eecs.umich.edu context = pri_context; 4183804Ssaidi@eecs.umich.edu } 4193804Ssaidi@eecs.umich.edu 4203833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4213836Ssaidi@eecs.umich.edu cacheValid = true; 4223836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4233836Ssaidi@eecs.umich.edu cacheEntry = NULL; 4243836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4253804Ssaidi@eecs.umich.edu return NoFault; 4263804Ssaidi@eecs.umich.edu } 4273804Ssaidi@eecs.umich.edu 4283836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4293836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4303804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 4313804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4323804Ssaidi@eecs.umich.edu } 4333804Ssaidi@eecs.umich.edu 4343804Ssaidi@eecs.umich.edu if (addr_mask) 4353804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4363804Ssaidi@eecs.umich.edu 4373804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4383804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 4393804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4403804Ssaidi@eecs.umich.edu } 4413804Ssaidi@eecs.umich.edu 4423833Ssaidi@eecs.umich.edu if (!lsu_im) { 4433836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4443804Ssaidi@eecs.umich.edu real = true; 4453804Ssaidi@eecs.umich.edu context = 0; 4463804Ssaidi@eecs.umich.edu } else { 4473804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4483804Ssaidi@eecs.umich.edu } 4493804Ssaidi@eecs.umich.edu 4503804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 4513804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 4523804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 4533804Ssaidi@eecs.umich.edu if (real) 4543804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 4553804Ssaidi@eecs.umich.edu else 4563804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 4573804Ssaidi@eecs.umich.edu } 4583804Ssaidi@eecs.umich.edu 4593804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 4603804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 4613804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 4623804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4633804Ssaidi@eecs.umich.edu } 4643804Ssaidi@eecs.umich.edu 4653836Ssaidi@eecs.umich.edu // cache translation date for next translation 4663836Ssaidi@eecs.umich.edu cacheValid = true; 4673836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4683836Ssaidi@eecs.umich.edu cacheEntry = e; 4693836Ssaidi@eecs.umich.edu 4703826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 4713836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 4723836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 4733804Ssaidi@eecs.umich.edu return NoFault; 4743804Ssaidi@eecs.umich.edu} 4753804Ssaidi@eecs.umich.edu 4763804Ssaidi@eecs.umich.edu 4773804Ssaidi@eecs.umich.edu 4783804Ssaidi@eecs.umich.eduFault 4793804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 4803804Ssaidi@eecs.umich.edu{ 4813804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 4823833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4833836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4843836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 4853836Ssaidi@eecs.umich.edu ASI asi; 4863836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 4873836Ssaidi@eecs.umich.edu bool implicit = false; 4883836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4893833Ssaidi@eecs.umich.edu 4903836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 4913836Ssaidi@eecs.umich.edu vaddr, size, asi); 4923836Ssaidi@eecs.umich.edu 4933836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 4943836Ssaidi@eecs.umich.edu implicit = true; 4953836Ssaidi@eecs.umich.edu 4963836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 4973836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4983836Ssaidi@eecs.umich.edu return NoFault; 4993836Ssaidi@eecs.umich.edu } 5003836Ssaidi@eecs.umich.edu 5013836Ssaidi@eecs.umich.edu // Be fast if we can! 5023836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5033836Ssaidi@eecs.umich.edu if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 5043836Ssaidi@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 5053836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 5063836Ssaidi@eecs.umich.edu vaddr & cacheEntry[0]->pte.size()-1 ); 5073836Ssaidi@eecs.umich.edu return NoFault; 5083836Ssaidi@eecs.umich.edu } 5093836Ssaidi@eecs.umich.edu if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 5103836Ssaidi@eecs.umich.edu cacheEntry[1]->range.va + cacheEntry[1]->range.size >= vaddr) { 5113836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 5123836Ssaidi@eecs.umich.edu vaddr & cacheEntry[1]->pte.size()-1 ); 5133836Ssaidi@eecs.umich.edu return NoFault; 5143836Ssaidi@eecs.umich.edu } 5153836Ssaidi@eecs.umich.edu } 5163836Ssaidi@eecs.umich.edu 5173833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 5183833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 5193833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 5203833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 5213833Ssaidi@eecs.umich.edu 5223833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 5233833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 5243833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 5253833Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,47,32); 5263833Ssaidi@eecs.umich.edu 5273804Ssaidi@eecs.umich.edu bool real = false; 5283832Ssaidi@eecs.umich.edu ContextType ct = Primary; 5293832Ssaidi@eecs.umich.edu int context = 0; 5303804Ssaidi@eecs.umich.edu 5313804Ssaidi@eecs.umich.edu TlbEntry *e; 5323804Ssaidi@eecs.umich.edu 5333833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 5343833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 5353804Ssaidi@eecs.umich.edu 5363804Ssaidi@eecs.umich.edu if (implicit) { 5373804Ssaidi@eecs.umich.edu if (tl > 0) { 5383804Ssaidi@eecs.umich.edu asi = ASI_N; 5393804Ssaidi@eecs.umich.edu ct = Nucleus; 5403804Ssaidi@eecs.umich.edu context = 0; 5413804Ssaidi@eecs.umich.edu } else { 5423804Ssaidi@eecs.umich.edu asi = ASI_P; 5433804Ssaidi@eecs.umich.edu ct = Primary; 5443833Ssaidi@eecs.umich.edu context = pri_context; 5453804Ssaidi@eecs.umich.edu } 5463804Ssaidi@eecs.umich.edu } else if (!hpriv && !red) { 5473823Ssaidi@eecs.umich.edu if (tl > 0 || AsiIsNucleus(asi)) { 5483804Ssaidi@eecs.umich.edu ct = Nucleus; 5493804Ssaidi@eecs.umich.edu context = 0; 5503804Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 5513804Ssaidi@eecs.umich.edu ct = Secondary; 5523833Ssaidi@eecs.umich.edu context = sec_context; 5533804Ssaidi@eecs.umich.edu } else { 5543833Ssaidi@eecs.umich.edu context = pri_context; 5553804Ssaidi@eecs.umich.edu ct = Primary; //??? 5563804Ssaidi@eecs.umich.edu } 5573804Ssaidi@eecs.umich.edu 5583804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 5593804Ssaidi@eecs.umich.edu if (!priv && !AsiIsUnPriv(asi)) { 5603804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 5613804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 5623804Ssaidi@eecs.umich.edu return new PrivilegedAction; 5633804Ssaidi@eecs.umich.edu } 5643804Ssaidi@eecs.umich.edu if (priv && AsiIsHPriv(asi)) { 5653804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 5663804Ssaidi@eecs.umich.edu return new DataAccessException; 5673804Ssaidi@eecs.umich.edu } 5683804Ssaidi@eecs.umich.edu 5693826Ssaidi@eecs.umich.edu } else if (hpriv) { 5703826Ssaidi@eecs.umich.edu if (asi == ASI_P) { 5713826Ssaidi@eecs.umich.edu ct = Primary; 5723833Ssaidi@eecs.umich.edu context = pri_context; 5733826Ssaidi@eecs.umich.edu goto continueDtbFlow; 5743826Ssaidi@eecs.umich.edu } 5753804Ssaidi@eecs.umich.edu } 5763804Ssaidi@eecs.umich.edu 5773804Ssaidi@eecs.umich.edu if (!implicit) { 5783804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 5793804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 5803804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 5813804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 5823804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 5833804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 5843832Ssaidi@eecs.umich.edu if (write && asi == ASI_LDTX_P) 5853832Ssaidi@eecs.umich.edu // block init store (like write hint64) 5863832Ssaidi@eecs.umich.edu goto continueDtbFlow; 5873856Ssaidi@eecs.umich.edu if (!write && asi == ASI_QUAD_LDD) 5883856Ssaidi@eecs.umich.edu goto continueDtbFlow; 5893856Ssaidi@eecs.umich.edu 5903804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 5913804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 5923804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 5933804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 5943824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 5953824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 5963823Ssaidi@eecs.umich.edu 5973804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 5983804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 5993804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6003804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6013824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6023824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6033825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 6043825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6053823Ssaidi@eecs.umich.edu 6063823Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 6073823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6083804Ssaidi@eecs.umich.edu } 6093804Ssaidi@eecs.umich.edu 6103826Ssaidi@eecs.umich.educontinueDtbFlow: 6113826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6123826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 6133826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 6143826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6153826Ssaidi@eecs.umich.edu } 6163826Ssaidi@eecs.umich.edu 6173826Ssaidi@eecs.umich.edu if (addr_mask) 6183826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6193826Ssaidi@eecs.umich.edu 6203826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 6213826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 6223826Ssaidi@eecs.umich.edu return new DataAccessException; 6233826Ssaidi@eecs.umich.edu } 6243826Ssaidi@eecs.umich.edu 6253826Ssaidi@eecs.umich.edu 6263833Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) { 6273804Ssaidi@eecs.umich.edu real = true; 6283804Ssaidi@eecs.umich.edu context = 0; 6293804Ssaidi@eecs.umich.edu }; 6303804Ssaidi@eecs.umich.edu 6313804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 6323836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 6333804Ssaidi@eecs.umich.edu return NoFault; 6343804Ssaidi@eecs.umich.edu } 6353804Ssaidi@eecs.umich.edu 6363836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 6373804Ssaidi@eecs.umich.edu 6383804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 6393804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 6403804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 6413811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 6423804Ssaidi@eecs.umich.edu if (real) 6433804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 6443804Ssaidi@eecs.umich.edu else 6453804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 6463804Ssaidi@eecs.umich.edu 6473804Ssaidi@eecs.umich.edu } 6483804Ssaidi@eecs.umich.edu 6493804Ssaidi@eecs.umich.edu 6503804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 6513804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 6523804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 6533804Ssaidi@eecs.umich.edu } 6543804Ssaidi@eecs.umich.edu 6553804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 6563804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 6573804Ssaidi@eecs.umich.edu return new DataAccessException; 6583804Ssaidi@eecs.umich.edu } 6593804Ssaidi@eecs.umich.edu 6603804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 6613804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6623804Ssaidi@eecs.umich.edu 6633804Ssaidi@eecs.umich.edu 6643804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 6653804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 6663804Ssaidi@eecs.umich.edu return new DataAccessException; 6673804Ssaidi@eecs.umich.edu } 6683804Ssaidi@eecs.umich.edu 6693836Ssaidi@eecs.umich.edu // cache translation date for next translation 6703836Ssaidi@eecs.umich.edu cacheValid = true; 6713836Ssaidi@eecs.umich.edu cacheState = tlbdata; 6723836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 6733836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 6743836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 6753836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 6763836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 6773836Ssaidi@eecs.umich.edu if (implicit) 6783836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 6793836Ssaidi@eecs.umich.edu } 6803836Ssaidi@eecs.umich.edu 6813826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 6823836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 6833836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6843804Ssaidi@eecs.umich.edu return NoFault; 6853806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 6863804Ssaidi@eecs.umich.edu 6873806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 6883806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 6893806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6903806Ssaidi@eecs.umich.edu return new DataAccessException; 6913806Ssaidi@eecs.umich.edu } 6923824Ssaidi@eecs.umich.edu goto regAccessOk; 6933824Ssaidi@eecs.umich.edu 6943824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 6953824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 6963824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6973824Ssaidi@eecs.umich.edu return new PrivilegedAction; 6983824Ssaidi@eecs.umich.edu } 6993824Ssaidi@eecs.umich.edu if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 7003824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7013824Ssaidi@eecs.umich.edu return new DataAccessException; 7023824Ssaidi@eecs.umich.edu } 7033824Ssaidi@eecs.umich.edu goto regAccessOk; 7043824Ssaidi@eecs.umich.edu 7053825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 7063825Ssaidi@eecs.umich.edu if (!hpriv) { 7073825Ssaidi@eecs.umich.edu if (priv) { 7083825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7093825Ssaidi@eecs.umich.edu return new DataAccessException; 7103825Ssaidi@eecs.umich.edu } else { 7113825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7123825Ssaidi@eecs.umich.edu return new PrivilegedAction; 7133825Ssaidi@eecs.umich.edu } 7143825Ssaidi@eecs.umich.edu } 7153825Ssaidi@eecs.umich.edu goto regAccessOk; 7163825Ssaidi@eecs.umich.edu 7173825Ssaidi@eecs.umich.edu 7183824Ssaidi@eecs.umich.eduregAccessOk: 7193804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 7203811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 7213806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 7223806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 7233806Ssaidi@eecs.umich.edu return NoFault; 7243804Ssaidi@eecs.umich.edu}; 7253804Ssaidi@eecs.umich.edu 7263806Ssaidi@eecs.umich.eduTick 7273806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 7283806Ssaidi@eecs.umich.edu{ 7293823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 7303823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 7313833Ssaidi@eecs.umich.edu uint64_t temp, data; 7323833Ssaidi@eecs.umich.edu uint64_t tsbtemp, cnftemp; 7333823Ssaidi@eecs.umich.edu 7343823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 7353823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 7363823Ssaidi@eecs.umich.edu 7373823Ssaidi@eecs.umich.edu switch (asi) { 7383823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 7393823Ssaidi@eecs.umich.edu assert(va == 0); 7403823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 7413823Ssaidi@eecs.umich.edu break; 7423823Ssaidi@eecs.umich.edu case ASI_MMU: 7433823Ssaidi@eecs.umich.edu switch (va) { 7443823Ssaidi@eecs.umich.edu case 0x8: 7453823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 7463823Ssaidi@eecs.umich.edu break; 7473823Ssaidi@eecs.umich.edu case 0x10: 7483823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 7493823Ssaidi@eecs.umich.edu break; 7503823Ssaidi@eecs.umich.edu default: 7513823Ssaidi@eecs.umich.edu goto doMmuReadError; 7523823Ssaidi@eecs.umich.edu } 7533823Ssaidi@eecs.umich.edu break; 7543824Ssaidi@eecs.umich.edu case ASI_QUEUE: 7553824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 7563824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 7573824Ssaidi@eecs.umich.edu break; 7583823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 7593823Ssaidi@eecs.umich.edu assert(va == 0); 7603823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 7613823Ssaidi@eecs.umich.edu break; 7623823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 7633823Ssaidi@eecs.umich.edu assert(va == 0); 7643823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 7653823Ssaidi@eecs.umich.edu break; 7663823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 7673823Ssaidi@eecs.umich.edu assert(va == 0); 7683823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 7693823Ssaidi@eecs.umich.edu break; 7703823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 7713823Ssaidi@eecs.umich.edu assert(va == 0); 7723823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 7733823Ssaidi@eecs.umich.edu break; 7743823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 7753823Ssaidi@eecs.umich.edu assert(va == 0); 7763823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 7773823Ssaidi@eecs.umich.edu break; 7783823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 7793823Ssaidi@eecs.umich.edu assert(va == 0); 7803823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 7813823Ssaidi@eecs.umich.edu break; 7823823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 7833823Ssaidi@eecs.umich.edu assert(va == 0); 7843823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 7853823Ssaidi@eecs.umich.edu break; 7863823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 7873823Ssaidi@eecs.umich.edu assert(va == 0); 7883823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 7893823Ssaidi@eecs.umich.edu break; 7903823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 7913823Ssaidi@eecs.umich.edu assert(va == 0); 7923823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 7933823Ssaidi@eecs.umich.edu break; 7943823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 7953823Ssaidi@eecs.umich.edu assert(va == 0); 7963823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 7973823Ssaidi@eecs.umich.edu break; 7983823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 7993823Ssaidi@eecs.umich.edu assert(va == 0); 8003823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 8013823Ssaidi@eecs.umich.edu break; 8023823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8033823Ssaidi@eecs.umich.edu assert(va == 0); 8043823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 8053823Ssaidi@eecs.umich.edu break; 8063826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 8073826Ssaidi@eecs.umich.edu warn("returning 0 for SPARC ERROR regsiter read\n"); 8083826Ssaidi@eecs.umich.edu pkt->set(0); 8093826Ssaidi@eecs.umich.edu break; 8103823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 8113823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 8123823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 8133823Ssaidi@eecs.umich.edu break; 8143826Ssaidi@eecs.umich.edu case ASI_IMMU: 8153826Ssaidi@eecs.umich.edu switch (va) { 8163833Ssaidi@eecs.umich.edu case 0x0: 8173833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 8183833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 8193833Ssaidi@eecs.umich.edu break; 8203826Ssaidi@eecs.umich.edu case 0x30: 8213826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 8223826Ssaidi@eecs.umich.edu break; 8233826Ssaidi@eecs.umich.edu default: 8243826Ssaidi@eecs.umich.edu goto doMmuReadError; 8253826Ssaidi@eecs.umich.edu } 8263826Ssaidi@eecs.umich.edu break; 8273823Ssaidi@eecs.umich.edu case ASI_DMMU: 8283823Ssaidi@eecs.umich.edu switch (va) { 8293833Ssaidi@eecs.umich.edu case 0x0: 8303833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8313833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 8323833Ssaidi@eecs.umich.edu break; 8333826Ssaidi@eecs.umich.edu case 0x30: 8343826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 8353826Ssaidi@eecs.umich.edu break; 8363823Ssaidi@eecs.umich.edu case 0x80: 8373823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 8383823Ssaidi@eecs.umich.edu break; 8393823Ssaidi@eecs.umich.edu default: 8403823Ssaidi@eecs.umich.edu goto doMmuReadError; 8413823Ssaidi@eecs.umich.edu } 8423823Ssaidi@eecs.umich.edu break; 8433833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 8443833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8453833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 8463833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 8473833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 8483833Ssaidi@eecs.umich.edu } else { 8493833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 8503833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 8513833Ssaidi@eecs.umich.edu } 8523833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 8533833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 8543833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 8553833Ssaidi@eecs.umich.edu pkt->set(data); 8563833Ssaidi@eecs.umich.edu break; 8573833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 8583833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8593833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 8603833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 8613833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 8623833Ssaidi@eecs.umich.edu } else { 8633833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 8643833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 8653833Ssaidi@eecs.umich.edu } 8663833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 8673833Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 8683833Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 8693833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 8703833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 8713833Ssaidi@eecs.umich.edu pkt->set(data); 8723833Ssaidi@eecs.umich.edu break; 8733833Ssaidi@eecs.umich.edu 8743823Ssaidi@eecs.umich.edu default: 8753823Ssaidi@eecs.umich.edudoMmuReadError: 8763823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 8773823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 8783823Ssaidi@eecs.umich.edu } 8793823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 8803823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 8813806Ssaidi@eecs.umich.edu} 8823806Ssaidi@eecs.umich.edu 8833806Ssaidi@eecs.umich.eduTick 8843806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 8853806Ssaidi@eecs.umich.edu{ 8863823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 8873823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8883823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8893823Ssaidi@eecs.umich.edu 8903826Ssaidi@eecs.umich.edu Addr ta_insert; 8913826Ssaidi@eecs.umich.edu Addr va_insert; 8923826Ssaidi@eecs.umich.edu Addr ct_insert; 8933826Ssaidi@eecs.umich.edu int part_insert; 8943826Ssaidi@eecs.umich.edu int entry_insert = -1; 8953826Ssaidi@eecs.umich.edu bool real_insert; 8963863Ssaidi@eecs.umich.edu bool ignore; 8973863Ssaidi@eecs.umich.edu int part_id; 8983863Ssaidi@eecs.umich.edu int ctx_id; 8993826Ssaidi@eecs.umich.edu PageTableEntry pte; 9003826Ssaidi@eecs.umich.edu 9013825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 9023823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 9033823Ssaidi@eecs.umich.edu 9043823Ssaidi@eecs.umich.edu switch (asi) { 9053823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9073823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_MMU: 9103823Ssaidi@eecs.umich.edu switch (va) { 9113823Ssaidi@eecs.umich.edu case 0x8: 9123823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 9133823Ssaidi@eecs.umich.edu break; 9143823Ssaidi@eecs.umich.edu case 0x10: 9153823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu default: 9183823Ssaidi@eecs.umich.edu goto doMmuWriteError; 9193823Ssaidi@eecs.umich.edu } 9203823Ssaidi@eecs.umich.edu break; 9213824Ssaidi@eecs.umich.edu case ASI_QUEUE: 9223825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 9233824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 9243824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 9253824Ssaidi@eecs.umich.edu break; 9263823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 9273823Ssaidi@eecs.umich.edu assert(va == 0); 9283823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 9293823Ssaidi@eecs.umich.edu break; 9303823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 9313823Ssaidi@eecs.umich.edu assert(va == 0); 9323823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 9333823Ssaidi@eecs.umich.edu break; 9343823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9353823Ssaidi@eecs.umich.edu assert(va == 0); 9363823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 9373823Ssaidi@eecs.umich.edu break; 9383823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9393823Ssaidi@eecs.umich.edu assert(va == 0); 9403823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 9413823Ssaidi@eecs.umich.edu break; 9423823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9433823Ssaidi@eecs.umich.edu assert(va == 0); 9443823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 9453823Ssaidi@eecs.umich.edu break; 9463823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9473823Ssaidi@eecs.umich.edu assert(va == 0); 9483823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 9493823Ssaidi@eecs.umich.edu break; 9503823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9513823Ssaidi@eecs.umich.edu assert(va == 0); 9523823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 9533823Ssaidi@eecs.umich.edu break; 9543823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9553823Ssaidi@eecs.umich.edu assert(va == 0); 9563823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 9573823Ssaidi@eecs.umich.edu break; 9583823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9593823Ssaidi@eecs.umich.edu assert(va == 0); 9603823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 9613823Ssaidi@eecs.umich.edu break; 9623823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9633823Ssaidi@eecs.umich.edu assert(va == 0); 9643823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 9653823Ssaidi@eecs.umich.edu break; 9663823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9673823Ssaidi@eecs.umich.edu assert(va == 0); 9683823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 9693823Ssaidi@eecs.umich.edu break; 9703823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9713823Ssaidi@eecs.umich.edu assert(va == 0); 9723823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 9733823Ssaidi@eecs.umich.edu break; 9743825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 9753825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9763825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 9773825Ssaidi@eecs.umich.edu break; 9783823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9793823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9803823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 9813823Ssaidi@eecs.umich.edu break; 9823826Ssaidi@eecs.umich.edu case ASI_IMMU: 9833826Ssaidi@eecs.umich.edu switch (va) { 9843826Ssaidi@eecs.umich.edu case 0x30: 9853826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 9863826Ssaidi@eecs.umich.edu break; 9873826Ssaidi@eecs.umich.edu default: 9883826Ssaidi@eecs.umich.edu goto doMmuWriteError; 9893826Ssaidi@eecs.umich.edu } 9903826Ssaidi@eecs.umich.edu break; 9913826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 9923826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 9933826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 9943826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 9953826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9963826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 9973826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 9983826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 9993826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 10003826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 10013826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 10023826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 10033826Ssaidi@eecs.umich.edu pte, entry_insert); 10043826Ssaidi@eecs.umich.edu break; 10053826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 10063826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 10073826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 10083826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 10093826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 10103826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 10113826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 10123826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 10133826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 10143826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 10153826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 10163826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 10173826Ssaidi@eecs.umich.edu break; 10183863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 10193863Ssaidi@eecs.umich.edu ignore = false; 10203863Ssaidi@eecs.umich.edu ctx_id = -1; 10213863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 10223863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 10233863Ssaidi@eecs.umich.edu case 0: 10243863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 10253863Ssaidi@eecs.umich.edu break; 10263863Ssaidi@eecs.umich.edu case 1: 10273863Ssaidi@eecs.umich.edu ignore = true; 10283863Ssaidi@eecs.umich.edu break; 10293863Ssaidi@eecs.umich.edu case 3: 10303863Ssaidi@eecs.umich.edu ctx_id = 0; 10313863Ssaidi@eecs.umich.edu break; 10323863Ssaidi@eecs.umich.edu default: 10333863Ssaidi@eecs.umich.edu ignore = true; 10343863Ssaidi@eecs.umich.edu } 10353863Ssaidi@eecs.umich.edu 10363863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 10373863Ssaidi@eecs.umich.edu case 0: // demap page 10383863Ssaidi@eecs.umich.edu if (!ignore) 10393863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 10403863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 10413863Ssaidi@eecs.umich.edu break; 10423863Ssaidi@eecs.umich.edu case 1: //demap context 10433863Ssaidi@eecs.umich.edu if (!ignore) 10443863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 10453863Ssaidi@eecs.umich.edu break; 10463863Ssaidi@eecs.umich.edu case 2: 10473863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 10483863Ssaidi@eecs.umich.edu break; 10493863Ssaidi@eecs.umich.edu default: 10503863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 10513863Ssaidi@eecs.umich.edu } 10523863Ssaidi@eecs.umich.edu break; 10533823Ssaidi@eecs.umich.edu case ASI_DMMU: 10543823Ssaidi@eecs.umich.edu switch (va) { 10553826Ssaidi@eecs.umich.edu case 0x30: 10563826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 10573826Ssaidi@eecs.umich.edu break; 10583823Ssaidi@eecs.umich.edu case 0x80: 10593823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 10603823Ssaidi@eecs.umich.edu break; 10613823Ssaidi@eecs.umich.edu default: 10623823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10633823Ssaidi@eecs.umich.edu } 10643823Ssaidi@eecs.umich.edu break; 10653863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 10663863Ssaidi@eecs.umich.edu ignore = false; 10673863Ssaidi@eecs.umich.edu ctx_id = -1; 10683863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 10693863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 10703863Ssaidi@eecs.umich.edu case 0: 10713863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 10723863Ssaidi@eecs.umich.edu break; 10733863Ssaidi@eecs.umich.edu case 1: 10743863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 10753863Ssaidi@eecs.umich.edu break; 10763863Ssaidi@eecs.umich.edu case 3: 10773863Ssaidi@eecs.umich.edu ctx_id = 0; 10783863Ssaidi@eecs.umich.edu break; 10793863Ssaidi@eecs.umich.edu default: 10803863Ssaidi@eecs.umich.edu ignore = true; 10813863Ssaidi@eecs.umich.edu } 10823863Ssaidi@eecs.umich.edu 10833863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 10843863Ssaidi@eecs.umich.edu case 0: // demap page 10853863Ssaidi@eecs.umich.edu if (!ignore) 10863863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 10873863Ssaidi@eecs.umich.edu break; 10883863Ssaidi@eecs.umich.edu case 1: //demap context 10893863Ssaidi@eecs.umich.edu if (!ignore) 10903863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 10913863Ssaidi@eecs.umich.edu break; 10923863Ssaidi@eecs.umich.edu case 2: 10933863Ssaidi@eecs.umich.edu demapAll(part_id); 10943863Ssaidi@eecs.umich.edu break; 10953863Ssaidi@eecs.umich.edu default: 10963863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 10973863Ssaidi@eecs.umich.edu } 10983863Ssaidi@eecs.umich.edu break; 10993823Ssaidi@eecs.umich.edu default: 11003823Ssaidi@eecs.umich.edudoMmuWriteError: 11013823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 11023823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 11033823Ssaidi@eecs.umich.edu } 11043823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 11053823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 11063806Ssaidi@eecs.umich.edu} 11073806Ssaidi@eecs.umich.edu 11083804Ssaidi@eecs.umich.eduvoid 11093804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 11103804Ssaidi@eecs.umich.edu{ 11113804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 11123804Ssaidi@eecs.umich.edu} 11133804Ssaidi@eecs.umich.edu 11143804Ssaidi@eecs.umich.eduvoid 11153804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 11163804Ssaidi@eecs.umich.edu{ 11173804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 11183804Ssaidi@eecs.umich.edu} 11193804Ssaidi@eecs.umich.edu 11203804Ssaidi@eecs.umich.edu 11213804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 11223804Ssaidi@eecs.umich.edu 11233804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 11243804Ssaidi@eecs.umich.edu 11253804Ssaidi@eecs.umich.edu Param<int> size; 11263804Ssaidi@eecs.umich.edu 11273804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 11283804Ssaidi@eecs.umich.edu 11293804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 11303804Ssaidi@eecs.umich.edu 11313804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 11323804Ssaidi@eecs.umich.edu 11333804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 11343804Ssaidi@eecs.umich.edu 11353804Ssaidi@eecs.umich.edu 11363804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 11373804Ssaidi@eecs.umich.edu{ 11383804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 11393804Ssaidi@eecs.umich.edu} 11403804Ssaidi@eecs.umich.edu 11413804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 11423804Ssaidi@eecs.umich.edu 11433804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 11443804Ssaidi@eecs.umich.edu 11453804Ssaidi@eecs.umich.edu Param<int> size; 11463804Ssaidi@eecs.umich.edu 11473804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 11483804Ssaidi@eecs.umich.edu 11493804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 11503804Ssaidi@eecs.umich.edu 11513804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 11523804Ssaidi@eecs.umich.edu 11533804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 11543804Ssaidi@eecs.umich.edu 11553804Ssaidi@eecs.umich.edu 11563804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 11573804Ssaidi@eecs.umich.edu{ 11583804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 11593804Ssaidi@eecs.umich.edu} 11603804Ssaidi@eecs.umich.edu 11613804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 11623804Ssaidi@eecs.umich.edu} 1163