tlb.cc revision 3856
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 353811Ssaidi@eecs.umich.edu#include "base/trace.hh" 363811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 373823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 383823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 393823Ssaidi@eecs.umich.edu#include "mem/request.hh" 403569Sgblack@eecs.umich.edu#include "sim/builder.hh" 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 433804Ssaidi@eecs.umich.edu * */ 443569Sgblack@eecs.umich.edunamespace SparcISA 453569Sgblack@eecs.umich.edu{ 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 483836Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), cacheValid(false) 493804Ssaidi@eecs.umich.edu{ 503804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 513804Ssaidi@eecs.umich.edu if (size > 64) 523804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 533569Sgblack@eecs.umich.edu 543804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 553804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 563804Ssaidi@eecs.umich.edu} 573569Sgblack@eecs.umich.edu 583804Ssaidi@eecs.umich.eduvoid 593804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 603804Ssaidi@eecs.umich.edu{ 613804Ssaidi@eecs.umich.edu MapIter i; 623804Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end();) { 633804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 643804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 653804Ssaidi@eecs.umich.edu t->used = false; 663804Ssaidi@eecs.umich.edu usedEntries--; 673804Ssaidi@eecs.umich.edu } 683804Ssaidi@eecs.umich.edu } 693804Ssaidi@eecs.umich.edu} 703569Sgblack@eecs.umich.edu 713569Sgblack@eecs.umich.edu 723804Ssaidi@eecs.umich.eduvoid 733804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 743826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 753804Ssaidi@eecs.umich.edu{ 763569Sgblack@eecs.umich.edu 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.edu MapIter i; 793826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 803826Ssaidi@eecs.umich.edu int x; 813811Ssaidi@eecs.umich.edu 823836Ssaidi@eecs.umich.edu cacheValid = false; 833836Ssaidi@eecs.umich.edu 843826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", 853826Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real); 863811Ssaidi@eecs.umich.edu 873826Ssaidi@eecs.umich.edu if (entry != -1) { 883826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 893826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 903826Ssaidi@eecs.umich.edu } else { 913826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 923826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 933826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 943826Ssaidi@eecs.umich.edu break; 953826Ssaidi@eecs.umich.edu } 963804Ssaidi@eecs.umich.edu } 973569Sgblack@eecs.umich.edu } 983569Sgblack@eecs.umich.edu 993804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1003826Ssaidi@eecs.umich.edu if (!new_entry) 1013826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1023569Sgblack@eecs.umich.edu 1033804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1043804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1053804Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size(); 1063804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1073804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1083804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1093804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1103804Ssaidi@eecs.umich.edu new_entry->used = true;; 1113804Ssaidi@eecs.umich.edu new_entry->valid = true; 1123804Ssaidi@eecs.umich.edu usedEntries++; 1133569Sgblack@eecs.umich.edu 1143569Sgblack@eecs.umich.edu 1153804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1163804Ssaidi@eecs.umich.edu i = lookupTable.find(new_entry->range); 1173804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1183804Ssaidi@eecs.umich.edu i->second->valid = false; 1193804Ssaidi@eecs.umich.edu if (i->second->used) { 1203804Ssaidi@eecs.umich.edu i->second->used = false; 1213804Ssaidi@eecs.umich.edu usedEntries--; 1223804Ssaidi@eecs.umich.edu } 1233811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); 1243804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1253569Sgblack@eecs.umich.edu } 1263569Sgblack@eecs.umich.edu 1273804Ssaidi@eecs.umich.edu lookupTable.insert(new_entry->range, new_entry);; 1283804Ssaidi@eecs.umich.edu 1293804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1303804Ssaidi@eecs.umich.edu // one we just inserted 1313804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1323804Ssaidi@eecs.umich.edu clearUsedBits(); 1333804Ssaidi@eecs.umich.edu new_entry->used = true; 1343804Ssaidi@eecs.umich.edu usedEntries++; 1353804Ssaidi@eecs.umich.edu } 1363804Ssaidi@eecs.umich.edu 1373569Sgblack@eecs.umich.edu} 1383804Ssaidi@eecs.umich.edu 1393804Ssaidi@eecs.umich.edu 1403804Ssaidi@eecs.umich.eduTlbEntry* 1413804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 1423804Ssaidi@eecs.umich.edu{ 1433804Ssaidi@eecs.umich.edu MapIter i; 1443804Ssaidi@eecs.umich.edu TlbRange tr; 1453804Ssaidi@eecs.umich.edu TlbEntry *t; 1463804Ssaidi@eecs.umich.edu 1473811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 1483811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 1493804Ssaidi@eecs.umich.edu // Assemble full address structure 1503804Ssaidi@eecs.umich.edu tr.va = va; 1513804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 1523804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1533804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1543804Ssaidi@eecs.umich.edu tr.real = real; 1553804Ssaidi@eecs.umich.edu 1563804Ssaidi@eecs.umich.edu // Try to find the entry 1573804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1583804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 1593811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 1603804Ssaidi@eecs.umich.edu return NULL; 1613804Ssaidi@eecs.umich.edu } 1623804Ssaidi@eecs.umich.edu 1633804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 1643804Ssaidi@eecs.umich.edu t = i->second; 1653826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 1663826Ssaidi@eecs.umich.edu t->pte.size()); 1673804Ssaidi@eecs.umich.edu if (!t->used) { 1683804Ssaidi@eecs.umich.edu t->used = true; 1693804Ssaidi@eecs.umich.edu usedEntries++; 1703804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1713804Ssaidi@eecs.umich.edu clearUsedBits(); 1723804Ssaidi@eecs.umich.edu t->used = true; 1733804Ssaidi@eecs.umich.edu usedEntries++; 1743804Ssaidi@eecs.umich.edu } 1753804Ssaidi@eecs.umich.edu } 1763804Ssaidi@eecs.umich.edu 1773804Ssaidi@eecs.umich.edu return t; 1783804Ssaidi@eecs.umich.edu} 1793804Ssaidi@eecs.umich.edu 1803826Ssaidi@eecs.umich.eduvoid 1813826Ssaidi@eecs.umich.eduTLB::dumpAll() 1823826Ssaidi@eecs.umich.edu{ 1833826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 1843826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1853826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 1863826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 1873826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 1883826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 1893826Ssaidi@eecs.umich.edu } 1903826Ssaidi@eecs.umich.edu } 1913826Ssaidi@eecs.umich.edu} 1923804Ssaidi@eecs.umich.edu 1933804Ssaidi@eecs.umich.eduvoid 1943804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 1953804Ssaidi@eecs.umich.edu{ 1963804Ssaidi@eecs.umich.edu TlbRange tr; 1973804Ssaidi@eecs.umich.edu MapIter i; 1983804Ssaidi@eecs.umich.edu 1993836Ssaidi@eecs.umich.edu cacheValid = false; 2003836Ssaidi@eecs.umich.edu 2013804Ssaidi@eecs.umich.edu // Assemble full address structure 2023804Ssaidi@eecs.umich.edu tr.va = va; 2033804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 2043804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2053804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2063804Ssaidi@eecs.umich.edu tr.real = real; 2073804Ssaidi@eecs.umich.edu 2083804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2093804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2103804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2113804Ssaidi@eecs.umich.edu i->second->valid = false; 2123804Ssaidi@eecs.umich.edu if (i->second->used) { 2133804Ssaidi@eecs.umich.edu i->second->used = false; 2143804Ssaidi@eecs.umich.edu usedEntries--; 2153804Ssaidi@eecs.umich.edu } 2163804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2173804Ssaidi@eecs.umich.edu } 2183804Ssaidi@eecs.umich.edu} 2193804Ssaidi@eecs.umich.edu 2203804Ssaidi@eecs.umich.eduvoid 2213804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2223804Ssaidi@eecs.umich.edu{ 2233804Ssaidi@eecs.umich.edu int x; 2243836Ssaidi@eecs.umich.edu cacheValid = false; 2253804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2263804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2273804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2283804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2293804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2303804Ssaidi@eecs.umich.edu tlb[x].used = false; 2313804Ssaidi@eecs.umich.edu usedEntries--; 2323804Ssaidi@eecs.umich.edu } 2333804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2343804Ssaidi@eecs.umich.edu } 2353804Ssaidi@eecs.umich.edu } 2363804Ssaidi@eecs.umich.edu} 2373804Ssaidi@eecs.umich.edu 2383804Ssaidi@eecs.umich.eduvoid 2393804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 2403804Ssaidi@eecs.umich.edu{ 2413804Ssaidi@eecs.umich.edu int x; 2423836Ssaidi@eecs.umich.edu cacheValid = false; 2433804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2443804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 2453804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2463804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2473804Ssaidi@eecs.umich.edu tlb[x].used = false; 2483804Ssaidi@eecs.umich.edu usedEntries--; 2493804Ssaidi@eecs.umich.edu } 2503804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2513804Ssaidi@eecs.umich.edu } 2523804Ssaidi@eecs.umich.edu } 2533804Ssaidi@eecs.umich.edu} 2543804Ssaidi@eecs.umich.edu 2553804Ssaidi@eecs.umich.eduvoid 2563804Ssaidi@eecs.umich.eduTLB::invalidateAll() 2573804Ssaidi@eecs.umich.edu{ 2583804Ssaidi@eecs.umich.edu int x; 2593836Ssaidi@eecs.umich.edu cacheValid = false; 2603836Ssaidi@eecs.umich.edu 2613804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2623804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2633804Ssaidi@eecs.umich.edu } 2643804Ssaidi@eecs.umich.edu usedEntries = 0; 2653804Ssaidi@eecs.umich.edu} 2663804Ssaidi@eecs.umich.edu 2673804Ssaidi@eecs.umich.eduuint64_t 2683804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 2693804Ssaidi@eecs.umich.edu assert(entry < size); 2703804Ssaidi@eecs.umich.edu return tlb[entry].pte(); 2713804Ssaidi@eecs.umich.edu} 2723804Ssaidi@eecs.umich.edu 2733804Ssaidi@eecs.umich.eduuint64_t 2743804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 2753804Ssaidi@eecs.umich.edu assert(entry < size); 2763804Ssaidi@eecs.umich.edu uint64_t tag; 2773804Ssaidi@eecs.umich.edu 2783804Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId | tlb[entry].range.va | 2793804Ssaidi@eecs.umich.edu (uint64_t)tlb[entry].range.partitionId << 61; 2803804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 2813804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 2823804Ssaidi@eecs.umich.edu return tag; 2833804Ssaidi@eecs.umich.edu} 2843804Ssaidi@eecs.umich.edu 2853804Ssaidi@eecs.umich.edubool 2863804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 2873804Ssaidi@eecs.umich.edu{ 2883804Ssaidi@eecs.umich.edu if (am) 2893804Ssaidi@eecs.umich.edu return true; 2903804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 2913804Ssaidi@eecs.umich.edu return false; 2923804Ssaidi@eecs.umich.edu return true; 2933804Ssaidi@eecs.umich.edu} 2943804Ssaidi@eecs.umich.edu 2953804Ssaidi@eecs.umich.eduvoid 2963804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 2973804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2983804Ssaidi@eecs.umich.edu{ 2993804Ssaidi@eecs.umich.edu uint64_t sfsr; 3003804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 3013804Ssaidi@eecs.umich.edu 3023804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3033804Ssaidi@eecs.umich.edu sfsr = 0x3; 3043804Ssaidi@eecs.umich.edu else 3053804Ssaidi@eecs.umich.edu sfsr = 1; 3063804Ssaidi@eecs.umich.edu 3073804Ssaidi@eecs.umich.edu if (write) 3083804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3093804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3103804Ssaidi@eecs.umich.edu if (se) 3113804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3123804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3133804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3143826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 3153804Ssaidi@eecs.umich.edu} 3163804Ssaidi@eecs.umich.edu 3173826Ssaidi@eecs.umich.eduvoid 3183826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 3193826Ssaidi@eecs.umich.edu{ 3203826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 3213826Ssaidi@eecs.umich.edu} 3223804Ssaidi@eecs.umich.edu 3233804Ssaidi@eecs.umich.eduvoid 3243804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 3253804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3263804Ssaidi@eecs.umich.edu{ 3273811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 3283811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 3293804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 3303804Ssaidi@eecs.umich.edu} 3313804Ssaidi@eecs.umich.edu 3323804Ssaidi@eecs.umich.eduvoid 3333826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3343826Ssaidi@eecs.umich.edu{ 3353826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 3363826Ssaidi@eecs.umich.edu} 3373826Ssaidi@eecs.umich.edu 3383826Ssaidi@eecs.umich.eduvoid 3393804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 3403804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3413804Ssaidi@eecs.umich.edu{ 3423811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 3433811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 3443804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 3453826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 3463804Ssaidi@eecs.umich.edu} 3473804Ssaidi@eecs.umich.edu 3483836Ssaidi@eecs.umich.eduvoid 3493826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3503826Ssaidi@eecs.umich.edu{ 3513826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 3523826Ssaidi@eecs.umich.edu} 3533826Ssaidi@eecs.umich.edu 3543826Ssaidi@eecs.umich.edu 3553804Ssaidi@eecs.umich.edu 3563804Ssaidi@eecs.umich.eduFault 3573804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3583804Ssaidi@eecs.umich.edu{ 3593833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 3603833Ssaidi@eecs.umich.edu 3613836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 3623836Ssaidi@eecs.umich.edu TlbEntry *e; 3633836Ssaidi@eecs.umich.edu 3643836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 3653836Ssaidi@eecs.umich.edu 3663836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 3673836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 3683836Ssaidi@eecs.umich.edu 3693836Ssaidi@eecs.umich.edu // Be fast if we can! 3703836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 3713836Ssaidi@eecs.umich.edu if (cacheEntry) { 3723836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 3733836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 3743836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 3753836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 3763836Ssaidi@eecs.umich.edu return NoFault; 3773836Ssaidi@eecs.umich.edu } 3783836Ssaidi@eecs.umich.edu } else { 3793836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 3803836Ssaidi@eecs.umich.edu return NoFault; 3813836Ssaidi@eecs.umich.edu } 3823836Ssaidi@eecs.umich.edu } 3833836Ssaidi@eecs.umich.edu 3843833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 3853833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 3863833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 3873833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 3883833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 3893833Ssaidi@eecs.umich.edu 3903833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 3913833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 3923833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 3933804Ssaidi@eecs.umich.edu int context; 3943804Ssaidi@eecs.umich.edu ContextType ct; 3953804Ssaidi@eecs.umich.edu int asi; 3963804Ssaidi@eecs.umich.edu bool real = false; 3973804Ssaidi@eecs.umich.edu 3983833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 3993833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4003811Ssaidi@eecs.umich.edu 4013804Ssaidi@eecs.umich.edu if (tl > 0) { 4023804Ssaidi@eecs.umich.edu asi = ASI_N; 4033804Ssaidi@eecs.umich.edu ct = Nucleus; 4043804Ssaidi@eecs.umich.edu context = 0; 4053804Ssaidi@eecs.umich.edu } else { 4063804Ssaidi@eecs.umich.edu asi = ASI_P; 4073804Ssaidi@eecs.umich.edu ct = Primary; 4083833Ssaidi@eecs.umich.edu context = pri_context; 4093804Ssaidi@eecs.umich.edu } 4103804Ssaidi@eecs.umich.edu 4113833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4123836Ssaidi@eecs.umich.edu cacheValid = true; 4133836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4143836Ssaidi@eecs.umich.edu cacheEntry = NULL; 4153836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4163804Ssaidi@eecs.umich.edu return NoFault; 4173804Ssaidi@eecs.umich.edu } 4183804Ssaidi@eecs.umich.edu 4193836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4203836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4213804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 4223804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4233804Ssaidi@eecs.umich.edu } 4243804Ssaidi@eecs.umich.edu 4253804Ssaidi@eecs.umich.edu if (addr_mask) 4263804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4273804Ssaidi@eecs.umich.edu 4283804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4293804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 4303804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4313804Ssaidi@eecs.umich.edu } 4323804Ssaidi@eecs.umich.edu 4333833Ssaidi@eecs.umich.edu if (!lsu_im) { 4343836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4353804Ssaidi@eecs.umich.edu real = true; 4363804Ssaidi@eecs.umich.edu context = 0; 4373804Ssaidi@eecs.umich.edu } else { 4383804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4393804Ssaidi@eecs.umich.edu } 4403804Ssaidi@eecs.umich.edu 4413804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 4423804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 4433804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 4443804Ssaidi@eecs.umich.edu if (real) 4453804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 4463804Ssaidi@eecs.umich.edu else 4473804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 4483804Ssaidi@eecs.umich.edu } 4493804Ssaidi@eecs.umich.edu 4503804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 4513804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 4523804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 4533804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4543804Ssaidi@eecs.umich.edu } 4553804Ssaidi@eecs.umich.edu 4563836Ssaidi@eecs.umich.edu // cache translation date for next translation 4573836Ssaidi@eecs.umich.edu cacheValid = true; 4583836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4593836Ssaidi@eecs.umich.edu cacheEntry = e; 4603836Ssaidi@eecs.umich.edu 4613826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 4623836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 4633836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 4643804Ssaidi@eecs.umich.edu return NoFault; 4653804Ssaidi@eecs.umich.edu} 4663804Ssaidi@eecs.umich.edu 4673804Ssaidi@eecs.umich.edu 4683804Ssaidi@eecs.umich.edu 4693804Ssaidi@eecs.umich.eduFault 4703804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 4713804Ssaidi@eecs.umich.edu{ 4723804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 4733833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4743836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4753836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 4763836Ssaidi@eecs.umich.edu ASI asi; 4773836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 4783836Ssaidi@eecs.umich.edu bool implicit = false; 4793836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4803833Ssaidi@eecs.umich.edu 4813836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 4823836Ssaidi@eecs.umich.edu vaddr, size, asi); 4833836Ssaidi@eecs.umich.edu 4843836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 4853836Ssaidi@eecs.umich.edu implicit = true; 4863836Ssaidi@eecs.umich.edu 4873836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 4883836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4893836Ssaidi@eecs.umich.edu return NoFault; 4903836Ssaidi@eecs.umich.edu } 4913836Ssaidi@eecs.umich.edu 4923836Ssaidi@eecs.umich.edu // Be fast if we can! 4933836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4943836Ssaidi@eecs.umich.edu if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 4953836Ssaidi@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4963836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 4973836Ssaidi@eecs.umich.edu vaddr & cacheEntry[0]->pte.size()-1 ); 4983836Ssaidi@eecs.umich.edu return NoFault; 4993836Ssaidi@eecs.umich.edu } 5003836Ssaidi@eecs.umich.edu if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 5013836Ssaidi@eecs.umich.edu cacheEntry[1]->range.va + cacheEntry[1]->range.size >= vaddr) { 5023836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 5033836Ssaidi@eecs.umich.edu vaddr & cacheEntry[1]->pte.size()-1 ); 5043836Ssaidi@eecs.umich.edu return NoFault; 5053836Ssaidi@eecs.umich.edu } 5063836Ssaidi@eecs.umich.edu } 5073836Ssaidi@eecs.umich.edu 5083833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 5093833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 5103833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 5113833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 5123833Ssaidi@eecs.umich.edu 5133833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 5143833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 5153833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 5163833Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,47,32); 5173833Ssaidi@eecs.umich.edu 5183804Ssaidi@eecs.umich.edu bool real = false; 5193832Ssaidi@eecs.umich.edu ContextType ct = Primary; 5203832Ssaidi@eecs.umich.edu int context = 0; 5213804Ssaidi@eecs.umich.edu 5223804Ssaidi@eecs.umich.edu TlbEntry *e; 5233804Ssaidi@eecs.umich.edu 5243833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 5253833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 5263804Ssaidi@eecs.umich.edu 5273804Ssaidi@eecs.umich.edu if (implicit) { 5283804Ssaidi@eecs.umich.edu if (tl > 0) { 5293804Ssaidi@eecs.umich.edu asi = ASI_N; 5303804Ssaidi@eecs.umich.edu ct = Nucleus; 5313804Ssaidi@eecs.umich.edu context = 0; 5323804Ssaidi@eecs.umich.edu } else { 5333804Ssaidi@eecs.umich.edu asi = ASI_P; 5343804Ssaidi@eecs.umich.edu ct = Primary; 5353833Ssaidi@eecs.umich.edu context = pri_context; 5363804Ssaidi@eecs.umich.edu } 5373804Ssaidi@eecs.umich.edu } else if (!hpriv && !red) { 5383823Ssaidi@eecs.umich.edu if (tl > 0 || AsiIsNucleus(asi)) { 5393804Ssaidi@eecs.umich.edu ct = Nucleus; 5403804Ssaidi@eecs.umich.edu context = 0; 5413804Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 5423804Ssaidi@eecs.umich.edu ct = Secondary; 5433833Ssaidi@eecs.umich.edu context = sec_context; 5443804Ssaidi@eecs.umich.edu } else { 5453833Ssaidi@eecs.umich.edu context = pri_context; 5463804Ssaidi@eecs.umich.edu ct = Primary; //??? 5473804Ssaidi@eecs.umich.edu } 5483804Ssaidi@eecs.umich.edu 5493804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 5503804Ssaidi@eecs.umich.edu if (!priv && !AsiIsUnPriv(asi)) { 5513804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 5523804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 5533804Ssaidi@eecs.umich.edu return new PrivilegedAction; 5543804Ssaidi@eecs.umich.edu } 5553804Ssaidi@eecs.umich.edu if (priv && AsiIsHPriv(asi)) { 5563804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 5573804Ssaidi@eecs.umich.edu return new DataAccessException; 5583804Ssaidi@eecs.umich.edu } 5593804Ssaidi@eecs.umich.edu 5603826Ssaidi@eecs.umich.edu } else if (hpriv) { 5613826Ssaidi@eecs.umich.edu if (asi == ASI_P) { 5623826Ssaidi@eecs.umich.edu ct = Primary; 5633833Ssaidi@eecs.umich.edu context = pri_context; 5643826Ssaidi@eecs.umich.edu goto continueDtbFlow; 5653826Ssaidi@eecs.umich.edu } 5663804Ssaidi@eecs.umich.edu } 5673804Ssaidi@eecs.umich.edu 5683804Ssaidi@eecs.umich.edu if (!implicit) { 5693804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 5703804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 5713804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 5723804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 5733804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 5743804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 5753832Ssaidi@eecs.umich.edu if (write && asi == ASI_LDTX_P) 5763832Ssaidi@eecs.umich.edu // block init store (like write hint64) 5773832Ssaidi@eecs.umich.edu goto continueDtbFlow; 5783856Ssaidi@eecs.umich.edu if (!write && asi == ASI_QUAD_LDD) 5793856Ssaidi@eecs.umich.edu goto continueDtbFlow; 5803856Ssaidi@eecs.umich.edu 5813804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 5823804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 5833804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 5843804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 5853824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 5863824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 5873823Ssaidi@eecs.umich.edu 5883804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 5893804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 5903804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 5913804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 5923824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 5933824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 5943825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 5953825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 5963823Ssaidi@eecs.umich.edu 5973823Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 5983823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 5993804Ssaidi@eecs.umich.edu } 6003804Ssaidi@eecs.umich.edu 6013826Ssaidi@eecs.umich.educontinueDtbFlow: 6023826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6033826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 6043826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 6053826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6063826Ssaidi@eecs.umich.edu } 6073826Ssaidi@eecs.umich.edu 6083826Ssaidi@eecs.umich.edu if (addr_mask) 6093826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6103826Ssaidi@eecs.umich.edu 6113826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 6123826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 6133826Ssaidi@eecs.umich.edu return new DataAccessException; 6143826Ssaidi@eecs.umich.edu } 6153826Ssaidi@eecs.umich.edu 6163826Ssaidi@eecs.umich.edu 6173833Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) { 6183804Ssaidi@eecs.umich.edu real = true; 6193804Ssaidi@eecs.umich.edu context = 0; 6203804Ssaidi@eecs.umich.edu }; 6213804Ssaidi@eecs.umich.edu 6223804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 6233836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 6243804Ssaidi@eecs.umich.edu return NoFault; 6253804Ssaidi@eecs.umich.edu } 6263804Ssaidi@eecs.umich.edu 6273836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 6283804Ssaidi@eecs.umich.edu 6293804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 6303804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 6313804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 6323811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 6333804Ssaidi@eecs.umich.edu if (real) 6343804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 6353804Ssaidi@eecs.umich.edu else 6363804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 6373804Ssaidi@eecs.umich.edu 6383804Ssaidi@eecs.umich.edu } 6393804Ssaidi@eecs.umich.edu 6403804Ssaidi@eecs.umich.edu 6413804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 6423804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 6433804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 6443804Ssaidi@eecs.umich.edu } 6453804Ssaidi@eecs.umich.edu 6463804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 6473804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 6483804Ssaidi@eecs.umich.edu return new DataAccessException; 6493804Ssaidi@eecs.umich.edu } 6503804Ssaidi@eecs.umich.edu 6513804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 6523804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6533804Ssaidi@eecs.umich.edu 6543804Ssaidi@eecs.umich.edu 6553804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 6563804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 6573804Ssaidi@eecs.umich.edu return new DataAccessException; 6583804Ssaidi@eecs.umich.edu } 6593804Ssaidi@eecs.umich.edu 6603836Ssaidi@eecs.umich.edu // cache translation date for next translation 6613836Ssaidi@eecs.umich.edu cacheValid = true; 6623836Ssaidi@eecs.umich.edu cacheState = tlbdata; 6633836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 6643836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 6653836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 6663836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 6673836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 6683836Ssaidi@eecs.umich.edu if (implicit) 6693836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 6703836Ssaidi@eecs.umich.edu } 6713836Ssaidi@eecs.umich.edu 6723826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 6733836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 6743836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6753804Ssaidi@eecs.umich.edu return NoFault; 6763806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 6773804Ssaidi@eecs.umich.edu 6783806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 6793806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 6803806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6813806Ssaidi@eecs.umich.edu return new DataAccessException; 6823806Ssaidi@eecs.umich.edu } 6833824Ssaidi@eecs.umich.edu goto regAccessOk; 6843824Ssaidi@eecs.umich.edu 6853824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 6863824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 6873824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6883824Ssaidi@eecs.umich.edu return new PrivilegedAction; 6893824Ssaidi@eecs.umich.edu } 6903824Ssaidi@eecs.umich.edu if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 6913824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6923824Ssaidi@eecs.umich.edu return new DataAccessException; 6933824Ssaidi@eecs.umich.edu } 6943824Ssaidi@eecs.umich.edu goto regAccessOk; 6953824Ssaidi@eecs.umich.edu 6963825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 6973825Ssaidi@eecs.umich.edu if (!hpriv) { 6983825Ssaidi@eecs.umich.edu if (priv) { 6993825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7003825Ssaidi@eecs.umich.edu return new DataAccessException; 7013825Ssaidi@eecs.umich.edu } else { 7023825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7033825Ssaidi@eecs.umich.edu return new PrivilegedAction; 7043825Ssaidi@eecs.umich.edu } 7053825Ssaidi@eecs.umich.edu } 7063825Ssaidi@eecs.umich.edu goto regAccessOk; 7073825Ssaidi@eecs.umich.edu 7083825Ssaidi@eecs.umich.edu 7093824Ssaidi@eecs.umich.eduregAccessOk: 7103804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 7113811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 7123806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 7133806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 7143806Ssaidi@eecs.umich.edu return NoFault; 7153804Ssaidi@eecs.umich.edu}; 7163804Ssaidi@eecs.umich.edu 7173806Ssaidi@eecs.umich.eduTick 7183806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 7193806Ssaidi@eecs.umich.edu{ 7203823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 7213823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 7223833Ssaidi@eecs.umich.edu uint64_t temp, data; 7233833Ssaidi@eecs.umich.edu uint64_t tsbtemp, cnftemp; 7243823Ssaidi@eecs.umich.edu 7253823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 7263823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 7273823Ssaidi@eecs.umich.edu 7283823Ssaidi@eecs.umich.edu switch (asi) { 7293823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 7303823Ssaidi@eecs.umich.edu assert(va == 0); 7313823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 7323823Ssaidi@eecs.umich.edu break; 7333823Ssaidi@eecs.umich.edu case ASI_MMU: 7343823Ssaidi@eecs.umich.edu switch (va) { 7353823Ssaidi@eecs.umich.edu case 0x8: 7363823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 7373823Ssaidi@eecs.umich.edu break; 7383823Ssaidi@eecs.umich.edu case 0x10: 7393823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 7403823Ssaidi@eecs.umich.edu break; 7413823Ssaidi@eecs.umich.edu default: 7423823Ssaidi@eecs.umich.edu goto doMmuReadError; 7433823Ssaidi@eecs.umich.edu } 7443823Ssaidi@eecs.umich.edu break; 7453824Ssaidi@eecs.umich.edu case ASI_QUEUE: 7463824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 7473824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 7483824Ssaidi@eecs.umich.edu break; 7493823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 7503823Ssaidi@eecs.umich.edu assert(va == 0); 7513823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 7523823Ssaidi@eecs.umich.edu break; 7533823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 7543823Ssaidi@eecs.umich.edu assert(va == 0); 7553823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 7563823Ssaidi@eecs.umich.edu break; 7573823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 7583823Ssaidi@eecs.umich.edu assert(va == 0); 7593823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 7603823Ssaidi@eecs.umich.edu break; 7613823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 7623823Ssaidi@eecs.umich.edu assert(va == 0); 7633823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 7643823Ssaidi@eecs.umich.edu break; 7653823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 7663823Ssaidi@eecs.umich.edu assert(va == 0); 7673823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 7683823Ssaidi@eecs.umich.edu break; 7693823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 7703823Ssaidi@eecs.umich.edu assert(va == 0); 7713823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 7723823Ssaidi@eecs.umich.edu break; 7733823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 7743823Ssaidi@eecs.umich.edu assert(va == 0); 7753823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 7763823Ssaidi@eecs.umich.edu break; 7773823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 7783823Ssaidi@eecs.umich.edu assert(va == 0); 7793823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 7803823Ssaidi@eecs.umich.edu break; 7813823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 7823823Ssaidi@eecs.umich.edu assert(va == 0); 7833823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 7843823Ssaidi@eecs.umich.edu break; 7853823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 7863823Ssaidi@eecs.umich.edu assert(va == 0); 7873823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 7883823Ssaidi@eecs.umich.edu break; 7893823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 7903823Ssaidi@eecs.umich.edu assert(va == 0); 7913823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 7923823Ssaidi@eecs.umich.edu break; 7933823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 7943823Ssaidi@eecs.umich.edu assert(va == 0); 7953823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 7963823Ssaidi@eecs.umich.edu break; 7973826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 7983826Ssaidi@eecs.umich.edu warn("returning 0 for SPARC ERROR regsiter read\n"); 7993826Ssaidi@eecs.umich.edu pkt->set(0); 8003826Ssaidi@eecs.umich.edu break; 8013823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 8023823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 8033823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 8043823Ssaidi@eecs.umich.edu break; 8053826Ssaidi@eecs.umich.edu case ASI_IMMU: 8063826Ssaidi@eecs.umich.edu switch (va) { 8073833Ssaidi@eecs.umich.edu case 0x0: 8083833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 8093833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 8103833Ssaidi@eecs.umich.edu break; 8113826Ssaidi@eecs.umich.edu case 0x30: 8123826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 8133826Ssaidi@eecs.umich.edu break; 8143826Ssaidi@eecs.umich.edu default: 8153826Ssaidi@eecs.umich.edu goto doMmuReadError; 8163826Ssaidi@eecs.umich.edu } 8173826Ssaidi@eecs.umich.edu break; 8183823Ssaidi@eecs.umich.edu case ASI_DMMU: 8193823Ssaidi@eecs.umich.edu switch (va) { 8203833Ssaidi@eecs.umich.edu case 0x0: 8213833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8223833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 8233833Ssaidi@eecs.umich.edu break; 8243826Ssaidi@eecs.umich.edu case 0x30: 8253826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 8263826Ssaidi@eecs.umich.edu break; 8273823Ssaidi@eecs.umich.edu case 0x80: 8283823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 8293823Ssaidi@eecs.umich.edu break; 8303823Ssaidi@eecs.umich.edu default: 8313823Ssaidi@eecs.umich.edu goto doMmuReadError; 8323823Ssaidi@eecs.umich.edu } 8333823Ssaidi@eecs.umich.edu break; 8343833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 8353833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8363833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 8373833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 8383833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 8393833Ssaidi@eecs.umich.edu } else { 8403833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 8413833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 8423833Ssaidi@eecs.umich.edu } 8433833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 8443833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 8453833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 8463833Ssaidi@eecs.umich.edu pkt->set(data); 8473833Ssaidi@eecs.umich.edu break; 8483833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 8493833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8503833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 8513833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 8523833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 8533833Ssaidi@eecs.umich.edu } else { 8543833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 8553833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 8563833Ssaidi@eecs.umich.edu } 8573833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 8583833Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 8593833Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 8603833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 8613833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 8623833Ssaidi@eecs.umich.edu pkt->set(data); 8633833Ssaidi@eecs.umich.edu break; 8643833Ssaidi@eecs.umich.edu 8653823Ssaidi@eecs.umich.edu default: 8663823Ssaidi@eecs.umich.edudoMmuReadError: 8673823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 8683823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 8693823Ssaidi@eecs.umich.edu } 8703823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 8713823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 8723806Ssaidi@eecs.umich.edu} 8733806Ssaidi@eecs.umich.edu 8743806Ssaidi@eecs.umich.eduTick 8753806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 8763806Ssaidi@eecs.umich.edu{ 8773823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 8783823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8793823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8803823Ssaidi@eecs.umich.edu 8813826Ssaidi@eecs.umich.edu Addr ta_insert; 8823826Ssaidi@eecs.umich.edu Addr va_insert; 8833826Ssaidi@eecs.umich.edu Addr ct_insert; 8843826Ssaidi@eecs.umich.edu int part_insert; 8853826Ssaidi@eecs.umich.edu int entry_insert = -1; 8863826Ssaidi@eecs.umich.edu bool real_insert; 8873826Ssaidi@eecs.umich.edu PageTableEntry pte; 8883826Ssaidi@eecs.umich.edu 8893825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 8903823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 8913823Ssaidi@eecs.umich.edu 8923823Ssaidi@eecs.umich.edu switch (asi) { 8933823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8943823Ssaidi@eecs.umich.edu assert(va == 0); 8953823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 8963823Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_MMU: 8983823Ssaidi@eecs.umich.edu switch (va) { 8993823Ssaidi@eecs.umich.edu case 0x8: 9003823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 9013823Ssaidi@eecs.umich.edu break; 9023823Ssaidi@eecs.umich.edu case 0x10: 9033823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu default: 9063823Ssaidi@eecs.umich.edu goto doMmuWriteError; 9073823Ssaidi@eecs.umich.edu } 9083823Ssaidi@eecs.umich.edu break; 9093824Ssaidi@eecs.umich.edu case ASI_QUEUE: 9103825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 9113824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 9123824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 9133824Ssaidi@eecs.umich.edu break; 9143823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 9153823Ssaidi@eecs.umich.edu assert(va == 0); 9163823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 9173823Ssaidi@eecs.umich.edu break; 9183823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 9193823Ssaidi@eecs.umich.edu assert(va == 0); 9203823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 9213823Ssaidi@eecs.umich.edu break; 9223823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9233823Ssaidi@eecs.umich.edu assert(va == 0); 9243823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 9253823Ssaidi@eecs.umich.edu break; 9263823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9273823Ssaidi@eecs.umich.edu assert(va == 0); 9283823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 9293823Ssaidi@eecs.umich.edu break; 9303823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9313823Ssaidi@eecs.umich.edu assert(va == 0); 9323823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 9333823Ssaidi@eecs.umich.edu break; 9343823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9353823Ssaidi@eecs.umich.edu assert(va == 0); 9363823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 9373823Ssaidi@eecs.umich.edu break; 9383823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9393823Ssaidi@eecs.umich.edu assert(va == 0); 9403823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 9413823Ssaidi@eecs.umich.edu break; 9423823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9433823Ssaidi@eecs.umich.edu assert(va == 0); 9443823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 9453823Ssaidi@eecs.umich.edu break; 9463823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9473823Ssaidi@eecs.umich.edu assert(va == 0); 9483823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 9493823Ssaidi@eecs.umich.edu break; 9503823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9513823Ssaidi@eecs.umich.edu assert(va == 0); 9523823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 9533823Ssaidi@eecs.umich.edu break; 9543823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9553823Ssaidi@eecs.umich.edu assert(va == 0); 9563823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 9573823Ssaidi@eecs.umich.edu break; 9583823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9593823Ssaidi@eecs.umich.edu assert(va == 0); 9603823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 9613823Ssaidi@eecs.umich.edu break; 9623825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 9633825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9643825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 9653825Ssaidi@eecs.umich.edu break; 9663823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9673823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9683823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 9693823Ssaidi@eecs.umich.edu break; 9703826Ssaidi@eecs.umich.edu case ASI_IMMU: 9713826Ssaidi@eecs.umich.edu switch (va) { 9723826Ssaidi@eecs.umich.edu case 0x30: 9733826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 9743826Ssaidi@eecs.umich.edu break; 9753826Ssaidi@eecs.umich.edu default: 9763826Ssaidi@eecs.umich.edu goto doMmuWriteError; 9773826Ssaidi@eecs.umich.edu } 9783826Ssaidi@eecs.umich.edu break; 9793826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 9803826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 9813826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 9823826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 9833826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9843826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 9853826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 9863826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 9873826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 9883826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 9893826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 9903826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 9913826Ssaidi@eecs.umich.edu pte, entry_insert); 9923826Ssaidi@eecs.umich.edu break; 9933826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 9943826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 9953826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 9963826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 9973826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9983826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 9993826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 10003826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 10013826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 10023826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 10033826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 10043826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 10053826Ssaidi@eecs.umich.edu break; 10063823Ssaidi@eecs.umich.edu case ASI_DMMU: 10073823Ssaidi@eecs.umich.edu switch (va) { 10083826Ssaidi@eecs.umich.edu case 0x30: 10093826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 10103826Ssaidi@eecs.umich.edu break; 10113823Ssaidi@eecs.umich.edu case 0x80: 10123823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 10133823Ssaidi@eecs.umich.edu break; 10143823Ssaidi@eecs.umich.edu default: 10153823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10163823Ssaidi@eecs.umich.edu } 10173823Ssaidi@eecs.umich.edu break; 10183823Ssaidi@eecs.umich.edu default: 10193823Ssaidi@eecs.umich.edudoMmuWriteError: 10203823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 10213823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 10223823Ssaidi@eecs.umich.edu } 10233823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 10243823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 10253806Ssaidi@eecs.umich.edu} 10263806Ssaidi@eecs.umich.edu 10273804Ssaidi@eecs.umich.eduvoid 10283804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 10293804Ssaidi@eecs.umich.edu{ 10303804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 10313804Ssaidi@eecs.umich.edu} 10323804Ssaidi@eecs.umich.edu 10333804Ssaidi@eecs.umich.eduvoid 10343804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 10353804Ssaidi@eecs.umich.edu{ 10363804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 10373804Ssaidi@eecs.umich.edu} 10383804Ssaidi@eecs.umich.edu 10393804Ssaidi@eecs.umich.edu 10403804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 10413804Ssaidi@eecs.umich.edu 10423804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 10433804Ssaidi@eecs.umich.edu 10443804Ssaidi@eecs.umich.edu Param<int> size; 10453804Ssaidi@eecs.umich.edu 10463804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 10473804Ssaidi@eecs.umich.edu 10483804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 10493804Ssaidi@eecs.umich.edu 10503804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 10513804Ssaidi@eecs.umich.edu 10523804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 10533804Ssaidi@eecs.umich.edu 10543804Ssaidi@eecs.umich.edu 10553804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 10563804Ssaidi@eecs.umich.edu{ 10573804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 10583804Ssaidi@eecs.umich.edu} 10593804Ssaidi@eecs.umich.edu 10603804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 10613804Ssaidi@eecs.umich.edu 10623804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 10633804Ssaidi@eecs.umich.edu 10643804Ssaidi@eecs.umich.edu Param<int> size; 10653804Ssaidi@eecs.umich.edu 10663804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 10673804Ssaidi@eecs.umich.edu 10683804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 10693804Ssaidi@eecs.umich.edu 10703804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 10713804Ssaidi@eecs.umich.edu 10723804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 10733804Ssaidi@eecs.umich.edu 10743804Ssaidi@eecs.umich.edu 10753804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 10763804Ssaidi@eecs.umich.edu{ 10773804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 10783804Ssaidi@eecs.umich.edu} 10793804Ssaidi@eecs.umich.edu 10803804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 10813804Ssaidi@eecs.umich.edu} 1082