tlb.cc revision 3823
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343811Ssaidi@eecs.umich.edu#include "base/trace.hh" 353811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 363823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 373823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 383823Ssaidi@eecs.umich.edu#include "mem/request.hh" 393569Sgblack@eecs.umich.edu#include "sim/builder.hh" 403569Sgblack@eecs.umich.edu 413804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 423804Ssaidi@eecs.umich.edu * */ 433569Sgblack@eecs.umich.edunamespace SparcISA 443569Sgblack@eecs.umich.edu{ 453569Sgblack@eecs.umich.edu 463804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 473804Ssaidi@eecs.umich.edu : SimObject(name), size(s) 483804Ssaidi@eecs.umich.edu{ 493804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 503804Ssaidi@eecs.umich.edu if (size > 64) 513804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 523569Sgblack@eecs.umich.edu 533804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 543804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 553804Ssaidi@eecs.umich.edu} 563569Sgblack@eecs.umich.edu 573804Ssaidi@eecs.umich.eduvoid 583804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 593804Ssaidi@eecs.umich.edu{ 603804Ssaidi@eecs.umich.edu MapIter i; 613804Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end();) { 623804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 633804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 643804Ssaidi@eecs.umich.edu t->used = false; 653804Ssaidi@eecs.umich.edu usedEntries--; 663804Ssaidi@eecs.umich.edu } 673804Ssaidi@eecs.umich.edu } 683804Ssaidi@eecs.umich.edu} 693569Sgblack@eecs.umich.edu 703569Sgblack@eecs.umich.edu 713804Ssaidi@eecs.umich.eduvoid 723804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 733804Ssaidi@eecs.umich.edu const PageTableEntry& PTE) 743804Ssaidi@eecs.umich.edu{ 753569Sgblack@eecs.umich.edu 763569Sgblack@eecs.umich.edu 773804Ssaidi@eecs.umich.edu MapIter i; 783804Ssaidi@eecs.umich.edu TlbEntry *new_entry; 793811Ssaidi@eecs.umich.edu 803811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n", 813811Ssaidi@eecs.umich.edu va, partition_id, context_id, (int)real); 823811Ssaidi@eecs.umich.edu 833804Ssaidi@eecs.umich.edu int x = -1; 843804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 853804Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 863804Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 873804Ssaidi@eecs.umich.edu break; 883804Ssaidi@eecs.umich.edu } 893569Sgblack@eecs.umich.edu } 903569Sgblack@eecs.umich.edu 913804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 923804Ssaidi@eecs.umich.edu if (x == -1) 933804Ssaidi@eecs.umich.edu x = size - 1; 943569Sgblack@eecs.umich.edu 953804Ssaidi@eecs.umich.edu assert(PTE.valid()); 963804Ssaidi@eecs.umich.edu new_entry->range.va = va; 973804Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size(); 983804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 993804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1003804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1013804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1023804Ssaidi@eecs.umich.edu new_entry->used = true;; 1033804Ssaidi@eecs.umich.edu new_entry->valid = true; 1043804Ssaidi@eecs.umich.edu usedEntries++; 1053569Sgblack@eecs.umich.edu 1063569Sgblack@eecs.umich.edu 1073804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1083804Ssaidi@eecs.umich.edu i = lookupTable.find(new_entry->range); 1093804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1103804Ssaidi@eecs.umich.edu i->second->valid = false; 1113804Ssaidi@eecs.umich.edu if (i->second->used) { 1123804Ssaidi@eecs.umich.edu i->second->used = false; 1133804Ssaidi@eecs.umich.edu usedEntries--; 1143804Ssaidi@eecs.umich.edu } 1153811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); 1163804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1173569Sgblack@eecs.umich.edu } 1183569Sgblack@eecs.umich.edu 1193804Ssaidi@eecs.umich.edu lookupTable.insert(new_entry->range, new_entry);; 1203804Ssaidi@eecs.umich.edu 1213804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1223804Ssaidi@eecs.umich.edu // one we just inserted 1233804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1243804Ssaidi@eecs.umich.edu clearUsedBits(); 1253804Ssaidi@eecs.umich.edu new_entry->used = true; 1263804Ssaidi@eecs.umich.edu usedEntries++; 1273804Ssaidi@eecs.umich.edu } 1283804Ssaidi@eecs.umich.edu 1293569Sgblack@eecs.umich.edu} 1303804Ssaidi@eecs.umich.edu 1313804Ssaidi@eecs.umich.edu 1323804Ssaidi@eecs.umich.eduTlbEntry* 1333804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 1343804Ssaidi@eecs.umich.edu{ 1353804Ssaidi@eecs.umich.edu MapIter i; 1363804Ssaidi@eecs.umich.edu TlbRange tr; 1373804Ssaidi@eecs.umich.edu TlbEntry *t; 1383804Ssaidi@eecs.umich.edu 1393811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 1403811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 1413804Ssaidi@eecs.umich.edu // Assemble full address structure 1423804Ssaidi@eecs.umich.edu tr.va = va; 1433804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 1443804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1453804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1463804Ssaidi@eecs.umich.edu tr.real = real; 1473804Ssaidi@eecs.umich.edu 1483804Ssaidi@eecs.umich.edu // Try to find the entry 1493804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1503804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 1513811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 1523804Ssaidi@eecs.umich.edu return NULL; 1533804Ssaidi@eecs.umich.edu } 1543811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found\n"); 1553804Ssaidi@eecs.umich.edu 1563804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 1573804Ssaidi@eecs.umich.edu t = i->second; 1583804Ssaidi@eecs.umich.edu if (!t->used) { 1593804Ssaidi@eecs.umich.edu t->used = true; 1603804Ssaidi@eecs.umich.edu usedEntries++; 1613804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1623804Ssaidi@eecs.umich.edu clearUsedBits(); 1633804Ssaidi@eecs.umich.edu t->used = true; 1643804Ssaidi@eecs.umich.edu usedEntries++; 1653804Ssaidi@eecs.umich.edu } 1663804Ssaidi@eecs.umich.edu } 1673804Ssaidi@eecs.umich.edu 1683804Ssaidi@eecs.umich.edu return t; 1693804Ssaidi@eecs.umich.edu} 1703804Ssaidi@eecs.umich.edu 1713804Ssaidi@eecs.umich.edu 1723804Ssaidi@eecs.umich.eduvoid 1733804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 1743804Ssaidi@eecs.umich.edu{ 1753804Ssaidi@eecs.umich.edu TlbRange tr; 1763804Ssaidi@eecs.umich.edu MapIter i; 1773804Ssaidi@eecs.umich.edu 1783804Ssaidi@eecs.umich.edu // Assemble full address structure 1793804Ssaidi@eecs.umich.edu tr.va = va; 1803804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 1813804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1823804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1833804Ssaidi@eecs.umich.edu tr.real = real; 1843804Ssaidi@eecs.umich.edu 1853804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1863804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1873804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1883804Ssaidi@eecs.umich.edu i->second->valid = false; 1893804Ssaidi@eecs.umich.edu if (i->second->used) { 1903804Ssaidi@eecs.umich.edu i->second->used = false; 1913804Ssaidi@eecs.umich.edu usedEntries--; 1923804Ssaidi@eecs.umich.edu } 1933804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1943804Ssaidi@eecs.umich.edu } 1953804Ssaidi@eecs.umich.edu} 1963804Ssaidi@eecs.umich.edu 1973804Ssaidi@eecs.umich.eduvoid 1983804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 1993804Ssaidi@eecs.umich.edu{ 2003804Ssaidi@eecs.umich.edu int x; 2013804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2023804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2033804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2043804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2053804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2063804Ssaidi@eecs.umich.edu tlb[x].used = false; 2073804Ssaidi@eecs.umich.edu usedEntries--; 2083804Ssaidi@eecs.umich.edu } 2093804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2103804Ssaidi@eecs.umich.edu } 2113804Ssaidi@eecs.umich.edu } 2123804Ssaidi@eecs.umich.edu} 2133804Ssaidi@eecs.umich.edu 2143804Ssaidi@eecs.umich.eduvoid 2153804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 2163804Ssaidi@eecs.umich.edu{ 2173804Ssaidi@eecs.umich.edu int x; 2183804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2193804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 2203804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2213804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2223804Ssaidi@eecs.umich.edu tlb[x].used = false; 2233804Ssaidi@eecs.umich.edu usedEntries--; 2243804Ssaidi@eecs.umich.edu } 2253804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2263804Ssaidi@eecs.umich.edu } 2273804Ssaidi@eecs.umich.edu } 2283804Ssaidi@eecs.umich.edu} 2293804Ssaidi@eecs.umich.edu 2303804Ssaidi@eecs.umich.eduvoid 2313804Ssaidi@eecs.umich.eduTLB::invalidateAll() 2323804Ssaidi@eecs.umich.edu{ 2333804Ssaidi@eecs.umich.edu int x; 2343804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2353804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2363804Ssaidi@eecs.umich.edu } 2373804Ssaidi@eecs.umich.edu usedEntries = 0; 2383804Ssaidi@eecs.umich.edu} 2393804Ssaidi@eecs.umich.edu 2403804Ssaidi@eecs.umich.eduuint64_t 2413804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 2423804Ssaidi@eecs.umich.edu assert(entry < size); 2433804Ssaidi@eecs.umich.edu return tlb[entry].pte(); 2443804Ssaidi@eecs.umich.edu} 2453804Ssaidi@eecs.umich.edu 2463804Ssaidi@eecs.umich.eduuint64_t 2473804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 2483804Ssaidi@eecs.umich.edu assert(entry < size); 2493804Ssaidi@eecs.umich.edu uint64_t tag; 2503804Ssaidi@eecs.umich.edu 2513804Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId | tlb[entry].range.va | 2523804Ssaidi@eecs.umich.edu (uint64_t)tlb[entry].range.partitionId << 61; 2533804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 2543804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 2553804Ssaidi@eecs.umich.edu return tag; 2563804Ssaidi@eecs.umich.edu} 2573804Ssaidi@eecs.umich.edu 2583804Ssaidi@eecs.umich.edubool 2593804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 2603804Ssaidi@eecs.umich.edu{ 2613804Ssaidi@eecs.umich.edu if (am) 2623804Ssaidi@eecs.umich.edu return true; 2633804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 2643804Ssaidi@eecs.umich.edu return false; 2653804Ssaidi@eecs.umich.edu return true; 2663804Ssaidi@eecs.umich.edu} 2673804Ssaidi@eecs.umich.edu 2683804Ssaidi@eecs.umich.eduvoid 2693804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 2703804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2713804Ssaidi@eecs.umich.edu{ 2723804Ssaidi@eecs.umich.edu uint64_t sfsr; 2733804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 2743804Ssaidi@eecs.umich.edu 2753804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 2763804Ssaidi@eecs.umich.edu sfsr = 0x3; 2773804Ssaidi@eecs.umich.edu else 2783804Ssaidi@eecs.umich.edu sfsr = 1; 2793804Ssaidi@eecs.umich.edu 2803804Ssaidi@eecs.umich.edu if (write) 2813804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 2823804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 2833804Ssaidi@eecs.umich.edu if (se) 2843804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 2853804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 2863804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 2873804Ssaidi@eecs.umich.edu tc->setMiscReg(reg, sfsr); 2883804Ssaidi@eecs.umich.edu} 2893804Ssaidi@eecs.umich.edu 2903804Ssaidi@eecs.umich.edu 2913804Ssaidi@eecs.umich.eduvoid 2923804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 2933804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2943804Ssaidi@eecs.umich.edu{ 2953811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 2963811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 2973804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 2983804Ssaidi@eecs.umich.edu} 2993804Ssaidi@eecs.umich.edu 3003804Ssaidi@eecs.umich.eduvoid 3013804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 3023804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3033804Ssaidi@eecs.umich.edu{ 3043811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 3053811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 3063804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 3073804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); 3083804Ssaidi@eecs.umich.edu} 3093804Ssaidi@eecs.umich.edu 3103804Ssaidi@eecs.umich.edu 3113804Ssaidi@eecs.umich.eduFault 3123804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3133804Ssaidi@eecs.umich.edu{ 3143804Ssaidi@eecs.umich.edu uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); 3153804Ssaidi@eecs.umich.edu uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); 3163804Ssaidi@eecs.umich.edu bool lsuIm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 2 & 0x1; 3173804Ssaidi@eecs.umich.edu uint64_t tl = tc->readMiscReg(MISCREG_TL); 3183804Ssaidi@eecs.umich.edu uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 3193804Ssaidi@eecs.umich.edu bool addr_mask = pstate >> 3 & 0x1; 3203804Ssaidi@eecs.umich.edu bool priv = pstate >> 2 & 0x1; 3213804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 3223804Ssaidi@eecs.umich.edu int context; 3233804Ssaidi@eecs.umich.edu ContextType ct; 3243804Ssaidi@eecs.umich.edu int asi; 3253804Ssaidi@eecs.umich.edu bool real = false; 3263804Ssaidi@eecs.umich.edu TlbEntry *e; 3273804Ssaidi@eecs.umich.edu 3283811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 3293811Ssaidi@eecs.umich.edu vaddr, req->getSize()); 3303811Ssaidi@eecs.umich.edu 3313804Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 3323804Ssaidi@eecs.umich.edu 3333804Ssaidi@eecs.umich.edu if (tl > 0) { 3343804Ssaidi@eecs.umich.edu asi = ASI_N; 3353804Ssaidi@eecs.umich.edu ct = Nucleus; 3363804Ssaidi@eecs.umich.edu context = 0; 3373804Ssaidi@eecs.umich.edu } else { 3383804Ssaidi@eecs.umich.edu asi = ASI_P; 3393804Ssaidi@eecs.umich.edu ct = Primary; 3403804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 3413804Ssaidi@eecs.umich.edu } 3423804Ssaidi@eecs.umich.edu 3433804Ssaidi@eecs.umich.edu if ( hpstate >> 2 & 0x1 || hpstate >> 5 & 0x1 ) { 3443804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 3453804Ssaidi@eecs.umich.edu return NoFault; 3463804Ssaidi@eecs.umich.edu } 3473804Ssaidi@eecs.umich.edu 3483804Ssaidi@eecs.umich.edu // If the asi is unaligned trap 3493804Ssaidi@eecs.umich.edu if (vaddr & 0x7) { 3503804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 3513804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 3523804Ssaidi@eecs.umich.edu } 3533804Ssaidi@eecs.umich.edu 3543804Ssaidi@eecs.umich.edu if (addr_mask) 3553804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 3563804Ssaidi@eecs.umich.edu 3573804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 3583804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 3593804Ssaidi@eecs.umich.edu return new InstructionAccessException; 3603804Ssaidi@eecs.umich.edu } 3613804Ssaidi@eecs.umich.edu 3623804Ssaidi@eecs.umich.edu if (lsuIm) { 3633804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, true); 3643804Ssaidi@eecs.umich.edu real = true; 3653804Ssaidi@eecs.umich.edu context = 0; 3663804Ssaidi@eecs.umich.edu } else { 3673804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 3683804Ssaidi@eecs.umich.edu } 3693804Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 3713804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 3723804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 3733804Ssaidi@eecs.umich.edu if (real) 3743804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 3753804Ssaidi@eecs.umich.edu else 3763804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 3773804Ssaidi@eecs.umich.edu } 3783804Ssaidi@eecs.umich.edu 3793804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 3803804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 3813804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 3823804Ssaidi@eecs.umich.edu return new InstructionAccessException; 3833804Ssaidi@eecs.umich.edu } 3843804Ssaidi@eecs.umich.edu 3853804Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~e->pte.size() | 3863804Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()); 3873804Ssaidi@eecs.umich.edu return NoFault; 3883804Ssaidi@eecs.umich.edu} 3893804Ssaidi@eecs.umich.edu 3903804Ssaidi@eecs.umich.edu 3913804Ssaidi@eecs.umich.edu 3923804Ssaidi@eecs.umich.eduFault 3933804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 3943804Ssaidi@eecs.umich.edu{ 3953804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 3963804Ssaidi@eecs.umich.edu uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); 3973804Ssaidi@eecs.umich.edu uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); 3983804Ssaidi@eecs.umich.edu bool lsuDm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 3 & 0x1; 3993804Ssaidi@eecs.umich.edu uint64_t tl = tc->readMiscReg(MISCREG_TL); 4003804Ssaidi@eecs.umich.edu uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 4013804Ssaidi@eecs.umich.edu bool hpriv = hpstate >> 2 & 0x1; 4023804Ssaidi@eecs.umich.edu bool red = hpstate >> 5 >> 0x1; 4033804Ssaidi@eecs.umich.edu bool addr_mask = pstate >> 3 & 0x1; 4043804Ssaidi@eecs.umich.edu bool priv = pstate >> 2 & 0x1; 4053804Ssaidi@eecs.umich.edu bool implicit = false; 4063804Ssaidi@eecs.umich.edu bool real = false; 4073804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4083811Ssaidi@eecs.umich.edu Addr size = req->getSize(); 4093804Ssaidi@eecs.umich.edu ContextType ct; 4103804Ssaidi@eecs.umich.edu int context; 4113804Ssaidi@eecs.umich.edu ASI asi; 4123804Ssaidi@eecs.umich.edu 4133804Ssaidi@eecs.umich.edu TlbEntry *e; 4143804Ssaidi@eecs.umich.edu 4153811Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 4163811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 4173811Ssaidi@eecs.umich.edu vaddr, size, asi); 4183804Ssaidi@eecs.umich.edu 4193804Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 4203804Ssaidi@eecs.umich.edu implicit = true; 4213804Ssaidi@eecs.umich.edu 4223804Ssaidi@eecs.umich.edu if (implicit) { 4233804Ssaidi@eecs.umich.edu if (tl > 0) { 4243804Ssaidi@eecs.umich.edu asi = ASI_N; 4253804Ssaidi@eecs.umich.edu ct = Nucleus; 4263804Ssaidi@eecs.umich.edu context = 0; 4273804Ssaidi@eecs.umich.edu } else { 4283804Ssaidi@eecs.umich.edu asi = ASI_P; 4293804Ssaidi@eecs.umich.edu ct = Primary; 4303804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 4313804Ssaidi@eecs.umich.edu } 4323804Ssaidi@eecs.umich.edu } else if (!hpriv && !red) { 4333823Ssaidi@eecs.umich.edu if (tl > 0 || AsiIsNucleus(asi)) { 4343804Ssaidi@eecs.umich.edu ct = Nucleus; 4353804Ssaidi@eecs.umich.edu context = 0; 4363804Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 4373804Ssaidi@eecs.umich.edu ct = Secondary; 4383804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 4393804Ssaidi@eecs.umich.edu } else { 4403804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 4413804Ssaidi@eecs.umich.edu ct = Primary; //??? 4423804Ssaidi@eecs.umich.edu } 4433804Ssaidi@eecs.umich.edu 4443804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 4453804Ssaidi@eecs.umich.edu if (!priv && !AsiIsUnPriv(asi)) { 4463804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 4473804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 4483804Ssaidi@eecs.umich.edu return new PrivilegedAction; 4493804Ssaidi@eecs.umich.edu } 4503804Ssaidi@eecs.umich.edu if (priv && AsiIsHPriv(asi)) { 4513804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 4523804Ssaidi@eecs.umich.edu return new DataAccessException; 4533804Ssaidi@eecs.umich.edu } 4543804Ssaidi@eecs.umich.edu 4553804Ssaidi@eecs.umich.edu } 4563804Ssaidi@eecs.umich.edu 4573804Ssaidi@eecs.umich.edu // If the asi is unaligned trap 4583811Ssaidi@eecs.umich.edu if (vaddr & size-1) { 4593804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 4603804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4613804Ssaidi@eecs.umich.edu } 4623804Ssaidi@eecs.umich.edu 4633804Ssaidi@eecs.umich.edu if (addr_mask) 4643804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4653804Ssaidi@eecs.umich.edu 4663804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4673804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 4683804Ssaidi@eecs.umich.edu return new DataAccessException; 4693804Ssaidi@eecs.umich.edu } 4703804Ssaidi@eecs.umich.edu 4713804Ssaidi@eecs.umich.edu if (!implicit) { 4723804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 4733804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 4743804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 4753804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 4763804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 4773804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 4783804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 4793804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 4803804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 4813804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 4823823Ssaidi@eecs.umich.edu 4833804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 4843804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 4853804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 4863804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 4873823Ssaidi@eecs.umich.edu 4883823Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 4893823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 4903804Ssaidi@eecs.umich.edu } 4913804Ssaidi@eecs.umich.edu 4923804Ssaidi@eecs.umich.edu if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { 4933804Ssaidi@eecs.umich.edu real = true; 4943804Ssaidi@eecs.umich.edu context = 0; 4953804Ssaidi@eecs.umich.edu }; 4963804Ssaidi@eecs.umich.edu 4973804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 4983804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 4993804Ssaidi@eecs.umich.edu return NoFault; 5003804Ssaidi@eecs.umich.edu } 5013804Ssaidi@eecs.umich.edu 5023804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, real, context); 5033804Ssaidi@eecs.umich.edu 5043804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5053804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 5063804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 5073811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 5083804Ssaidi@eecs.umich.edu if (real) 5093804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 5103804Ssaidi@eecs.umich.edu else 5113804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 5123804Ssaidi@eecs.umich.edu 5133804Ssaidi@eecs.umich.edu } 5143804Ssaidi@eecs.umich.edu 5153804Ssaidi@eecs.umich.edu 5163804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 5173804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 5183804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 5193804Ssaidi@eecs.umich.edu } 5203804Ssaidi@eecs.umich.edu 5213804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 5223804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 5233804Ssaidi@eecs.umich.edu return new DataAccessException; 5243804Ssaidi@eecs.umich.edu } 5253804Ssaidi@eecs.umich.edu 5263804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 5273804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 5283804Ssaidi@eecs.umich.edu 5293804Ssaidi@eecs.umich.edu 5303804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5313804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 5323804Ssaidi@eecs.umich.edu return new DataAccessException; 5333804Ssaidi@eecs.umich.edu } 5343804Ssaidi@eecs.umich.edu 5353804Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~e->pte.size() | 5363804Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()); 5373804Ssaidi@eecs.umich.edu return NoFault; 5383806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 5393804Ssaidi@eecs.umich.edu 5403806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 5413806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 5423806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 5433806Ssaidi@eecs.umich.edu return new DataAccessException; 5443806Ssaidi@eecs.umich.edu } 5453804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 5463811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 5473806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 5483806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 5493806Ssaidi@eecs.umich.edu return NoFault; 5503804Ssaidi@eecs.umich.edu}; 5513804Ssaidi@eecs.umich.edu 5523806Ssaidi@eecs.umich.eduTick 5533806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 5543806Ssaidi@eecs.umich.edu{ 5553823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 5563823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 5573823Ssaidi@eecs.umich.edu 5583823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 5593823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 5603823Ssaidi@eecs.umich.edu 5613823Ssaidi@eecs.umich.edu switch (asi) { 5623823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 5633823Ssaidi@eecs.umich.edu assert(va == 0); 5643823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 5653823Ssaidi@eecs.umich.edu break; 5663823Ssaidi@eecs.umich.edu case ASI_MMU: 5673823Ssaidi@eecs.umich.edu switch (va) { 5683823Ssaidi@eecs.umich.edu case 0x8: 5693823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 5703823Ssaidi@eecs.umich.edu break; 5713823Ssaidi@eecs.umich.edu case 0x10: 5723823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 5733823Ssaidi@eecs.umich.edu break; 5743823Ssaidi@eecs.umich.edu default: 5753823Ssaidi@eecs.umich.edu goto doMmuReadError; 5763823Ssaidi@eecs.umich.edu } 5773823Ssaidi@eecs.umich.edu break; 5783823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 5793823Ssaidi@eecs.umich.edu assert(va == 0); 5803823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 5813823Ssaidi@eecs.umich.edu break; 5823823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 5833823Ssaidi@eecs.umich.edu assert(va == 0); 5843823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 5853823Ssaidi@eecs.umich.edu break; 5863823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 5873823Ssaidi@eecs.umich.edu assert(va == 0); 5883823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 5893823Ssaidi@eecs.umich.edu break; 5903823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 5913823Ssaidi@eecs.umich.edu assert(va == 0); 5923823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 5933823Ssaidi@eecs.umich.edu break; 5943823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 5953823Ssaidi@eecs.umich.edu assert(va == 0); 5963823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 5973823Ssaidi@eecs.umich.edu break; 5983823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 5993823Ssaidi@eecs.umich.edu assert(va == 0); 6003823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 6013823Ssaidi@eecs.umich.edu break; 6023823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 6033823Ssaidi@eecs.umich.edu assert(va == 0); 6043823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 6053823Ssaidi@eecs.umich.edu break; 6063823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 6073823Ssaidi@eecs.umich.edu assert(va == 0); 6083823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 6093823Ssaidi@eecs.umich.edu break; 6103823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 6113823Ssaidi@eecs.umich.edu assert(va == 0); 6123823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 6133823Ssaidi@eecs.umich.edu break; 6143823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 6153823Ssaidi@eecs.umich.edu assert(va == 0); 6163823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 6173823Ssaidi@eecs.umich.edu break; 6183823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 6193823Ssaidi@eecs.umich.edu assert(va == 0); 6203823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 6213823Ssaidi@eecs.umich.edu break; 6223823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 6233823Ssaidi@eecs.umich.edu assert(va == 0); 6243823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 6253823Ssaidi@eecs.umich.edu break; 6263823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 6273823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 6283823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 6293823Ssaidi@eecs.umich.edu break; 6303823Ssaidi@eecs.umich.edu case ASI_DMMU: 6313823Ssaidi@eecs.umich.edu switch (va) { 6323823Ssaidi@eecs.umich.edu case 0x80: 6333823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 6343823Ssaidi@eecs.umich.edu break; 6353823Ssaidi@eecs.umich.edu default: 6363823Ssaidi@eecs.umich.edu goto doMmuReadError; 6373823Ssaidi@eecs.umich.edu } 6383823Ssaidi@eecs.umich.edu break; 6393823Ssaidi@eecs.umich.edu default: 6403823Ssaidi@eecs.umich.edudoMmuReadError: 6413823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 6423823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 6433823Ssaidi@eecs.umich.edu } 6443823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 6453823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 6463806Ssaidi@eecs.umich.edu} 6473806Ssaidi@eecs.umich.edu 6483806Ssaidi@eecs.umich.eduTick 6493806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 6503806Ssaidi@eecs.umich.edu{ 6513823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 6523823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 6533823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 6543823Ssaidi@eecs.umich.edu 6553823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n", 6563823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 6573823Ssaidi@eecs.umich.edu 6583823Ssaidi@eecs.umich.edu switch (asi) { 6593823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 6603823Ssaidi@eecs.umich.edu assert(va == 0); 6613823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 6623823Ssaidi@eecs.umich.edu break; 6633823Ssaidi@eecs.umich.edu case ASI_MMU: 6643823Ssaidi@eecs.umich.edu switch (va) { 6653823Ssaidi@eecs.umich.edu case 0x8: 6663823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 6673823Ssaidi@eecs.umich.edu break; 6683823Ssaidi@eecs.umich.edu case 0x10: 6693823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 6703823Ssaidi@eecs.umich.edu break; 6713823Ssaidi@eecs.umich.edu default: 6723823Ssaidi@eecs.umich.edu goto doMmuWriteError; 6733823Ssaidi@eecs.umich.edu } 6743823Ssaidi@eecs.umich.edu break; 6753823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 6763823Ssaidi@eecs.umich.edu assert(va == 0); 6773823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 6783823Ssaidi@eecs.umich.edu break; 6793823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 6803823Ssaidi@eecs.umich.edu assert(va == 0); 6813823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 6823823Ssaidi@eecs.umich.edu break; 6833823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 6843823Ssaidi@eecs.umich.edu assert(va == 0); 6853823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 6863823Ssaidi@eecs.umich.edu break; 6873823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 6883823Ssaidi@eecs.umich.edu assert(va == 0); 6893823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 6903823Ssaidi@eecs.umich.edu break; 6913823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 6923823Ssaidi@eecs.umich.edu assert(va == 0); 6933823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 6943823Ssaidi@eecs.umich.edu break; 6953823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 6963823Ssaidi@eecs.umich.edu assert(va == 0); 6973823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 6983823Ssaidi@eecs.umich.edu break; 6993823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 7003823Ssaidi@eecs.umich.edu assert(va == 0); 7013823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 7023823Ssaidi@eecs.umich.edu break; 7033823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 7043823Ssaidi@eecs.umich.edu assert(va == 0); 7053823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 7063823Ssaidi@eecs.umich.edu break; 7073823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 7083823Ssaidi@eecs.umich.edu assert(va == 0); 7093823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 7103823Ssaidi@eecs.umich.edu break; 7113823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 7123823Ssaidi@eecs.umich.edu assert(va == 0); 7133823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 7143823Ssaidi@eecs.umich.edu break; 7153823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 7163823Ssaidi@eecs.umich.edu assert(va == 0); 7173823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 7183823Ssaidi@eecs.umich.edu break; 7193823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 7203823Ssaidi@eecs.umich.edu assert(va == 0); 7213823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 7223823Ssaidi@eecs.umich.edu break; 7233823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 7243823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 7253823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 7263823Ssaidi@eecs.umich.edu break; 7273823Ssaidi@eecs.umich.edu case ASI_DMMU: 7283823Ssaidi@eecs.umich.edu switch (va) { 7293823Ssaidi@eecs.umich.edu case 0x80: 7303823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 7313823Ssaidi@eecs.umich.edu break; 7323823Ssaidi@eecs.umich.edu default: 7333823Ssaidi@eecs.umich.edu goto doMmuWriteError; 7343823Ssaidi@eecs.umich.edu } 7353823Ssaidi@eecs.umich.edu break; 7363823Ssaidi@eecs.umich.edu default: 7373823Ssaidi@eecs.umich.edudoMmuWriteError: 7383823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 7393823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 7403823Ssaidi@eecs.umich.edu } 7413823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 7423823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 7433806Ssaidi@eecs.umich.edu} 7443806Ssaidi@eecs.umich.edu 7453804Ssaidi@eecs.umich.eduvoid 7463804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 7473804Ssaidi@eecs.umich.edu{ 7483804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 7493804Ssaidi@eecs.umich.edu} 7503804Ssaidi@eecs.umich.edu 7513804Ssaidi@eecs.umich.eduvoid 7523804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 7533804Ssaidi@eecs.umich.edu{ 7543804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 7553804Ssaidi@eecs.umich.edu} 7563804Ssaidi@eecs.umich.edu 7573804Ssaidi@eecs.umich.edu 7583804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 7593804Ssaidi@eecs.umich.edu 7603804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 7613804Ssaidi@eecs.umich.edu 7623804Ssaidi@eecs.umich.edu Param<int> size; 7633804Ssaidi@eecs.umich.edu 7643804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 7653804Ssaidi@eecs.umich.edu 7663804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 7673804Ssaidi@eecs.umich.edu 7683804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 7693804Ssaidi@eecs.umich.edu 7703804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 7713804Ssaidi@eecs.umich.edu 7723804Ssaidi@eecs.umich.edu 7733804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 7743804Ssaidi@eecs.umich.edu{ 7753804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 7763804Ssaidi@eecs.umich.edu} 7773804Ssaidi@eecs.umich.edu 7783804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 7793804Ssaidi@eecs.umich.edu 7803804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 7813804Ssaidi@eecs.umich.edu 7823804Ssaidi@eecs.umich.edu Param<int> size; 7833804Ssaidi@eecs.umich.edu 7843804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 7853804Ssaidi@eecs.umich.edu 7863804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 7873804Ssaidi@eecs.umich.edu 7883804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 7893804Ssaidi@eecs.umich.edu 7903804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 7913804Ssaidi@eecs.umich.edu 7923804Ssaidi@eecs.umich.edu 7933804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 7943804Ssaidi@eecs.umich.edu{ 7953804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 7963804Ssaidi@eecs.umich.edu} 7973804Ssaidi@eecs.umich.edu 7983804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 7993804Ssaidi@eecs.umich.edu} 800