tlb.cc revision 12620
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#include "arch/sparc/tlb.hh" 3211793Sbrandon.potter@amd.com 333918Ssaidi@eecs.umich.edu#include <cstring> 343918Ssaidi@eecs.umich.edu 353804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 367678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 376335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 383824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 3912620Sgabeblack@google.com#include "base/compiler.hh" 403811Ssaidi@eecs.umich.edu#include "base/trace.hh" 418229Snate@binkert.org#include "cpu/base.hh" 423811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 438232Snate@binkert.org#include "debug/IPR.hh" 448232Snate@binkert.org#include "debug/TLB.hh" 453823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 463823Ssaidi@eecs.umich.edu#include "mem/request.hh" 478751Sgblack@eecs.umich.edu#include "sim/full_system.hh" 484103Ssaidi@eecs.umich.edu#include "sim/system.hh" 493569Sgblack@eecs.umich.edu 503804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 513804Ssaidi@eecs.umich.edu * */ 524088Sbinkertn@umich.edunamespace SparcISA { 533569Sgblack@eecs.umich.edu 545034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 555358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 568374Sksewell@umich.edu cacheState(0), cacheValid(false) 573804Ssaidi@eecs.umich.edu{ 583804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 593804Ssaidi@eecs.umich.edu if (size > 64) 605555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 613569Sgblack@eecs.umich.edu 623804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 633918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 643881Ssaidi@eecs.umich.edu 653881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 663881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 674990Sgblack@eecs.umich.edu 684990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 694990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 704990Sgblack@eecs.umich.edu c0_config = 0; 714990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 724990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 734990Sgblack@eecs.umich.edu cx_config = 0; 744990Sgblack@eecs.umich.edu sfsr = 0; 754990Sgblack@eecs.umich.edu tag_access = 0; 766022Sgblack@eecs.umich.edu sfar = 0; 776022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 786022Sgblack@eecs.umich.edu cacheEntry[1] = NULL; 793804Ssaidi@eecs.umich.edu} 803569Sgblack@eecs.umich.edu 813804Ssaidi@eecs.umich.eduvoid 823804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 833804Ssaidi@eecs.umich.edu{ 843804Ssaidi@eecs.umich.edu MapIter i; 853881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 863804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 873804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 883804Ssaidi@eecs.umich.edu t->used = false; 893804Ssaidi@eecs.umich.edu usedEntries--; 903804Ssaidi@eecs.umich.edu } 913804Ssaidi@eecs.umich.edu } 923804Ssaidi@eecs.umich.edu} 933569Sgblack@eecs.umich.edu 943569Sgblack@eecs.umich.edu 953804Ssaidi@eecs.umich.eduvoid 963804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 973826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 983804Ssaidi@eecs.umich.edu{ 993804Ssaidi@eecs.umich.edu MapIter i; 1003826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 1013907Ssaidi@eecs.umich.edu// TlbRange tr; 1023826Ssaidi@eecs.umich.edu int x; 1033811Ssaidi@eecs.umich.edu 1043836Ssaidi@eecs.umich.edu cacheValid = false; 1053915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1063907Ssaidi@eecs.umich.edu /* tr.va = va; 1073881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1083881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1093881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1103881Ssaidi@eecs.umich.edu tr.real = real; 1113907Ssaidi@eecs.umich.edu*/ 1123881Ssaidi@eecs.umich.edu 1135555Snate@binkert.org DPRINTF(TLB, 1145555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1155555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1163881Ssaidi@eecs.umich.edu 1173881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1183907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1193907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1203907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1213907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1223907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1233907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1243907Ssaidi@eecs.umich.edu { 1253907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1263907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1273907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1283907Ssaidi@eecs.umich.edu 1293907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1303907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1313907Ssaidi@eecs.umich.edu tlb[x].used = false; 1323907Ssaidi@eecs.umich.edu usedEntries--; 1333907Ssaidi@eecs.umich.edu } 1343907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1353907Ssaidi@eecs.umich.edu } 1363907Ssaidi@eecs.umich.edu } 1373907Ssaidi@eecs.umich.edu } 1383907Ssaidi@eecs.umich.edu 1393826Ssaidi@eecs.umich.edu if (entry != -1) { 1403826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1413826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1423826Ssaidi@eecs.umich.edu } else { 1433881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1443881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1453881Ssaidi@eecs.umich.edu } else { 1463881Ssaidi@eecs.umich.edu x = lastReplaced; 1473881Ssaidi@eecs.umich.edu do { 1483881Ssaidi@eecs.umich.edu ++x; 1493881Ssaidi@eecs.umich.edu if (x == size) 1503881Ssaidi@eecs.umich.edu x = 0; 1513881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1523881Ssaidi@eecs.umich.edu goto insertAllLocked; 1533881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1543881Ssaidi@eecs.umich.edu lastReplaced = x; 1553881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1563881Ssaidi@eecs.umich.edu } 1573569Sgblack@eecs.umich.edu } 1583569Sgblack@eecs.umich.edu 1593881Ssaidi@eecs.umich.eduinsertAllLocked: 1603804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1613881Ssaidi@eecs.umich.edu if (!new_entry) { 1623826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1633881Ssaidi@eecs.umich.edu } 1643881Ssaidi@eecs.umich.edu 1653881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1663907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1673907Ssaidi@eecs.umich.edu usedEntries--; 1683929Ssaidi@eecs.umich.edu if (new_entry->valid) 1693929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1703907Ssaidi@eecs.umich.edu 1713907Ssaidi@eecs.umich.edu 1723804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1733804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1743881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1753804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1763804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1773804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1783804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1793804Ssaidi@eecs.umich.edu new_entry->used = true;; 1803804Ssaidi@eecs.umich.edu new_entry->valid = true; 1813804Ssaidi@eecs.umich.edu usedEntries++; 1823569Sgblack@eecs.umich.edu 1833863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1843863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1853804Ssaidi@eecs.umich.edu 1865555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 1875555Snate@binkert.org // but the one we just inserted 1883804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1893804Ssaidi@eecs.umich.edu clearUsedBits(); 1903804Ssaidi@eecs.umich.edu new_entry->used = true; 1913804Ssaidi@eecs.umich.edu usedEntries++; 1923804Ssaidi@eecs.umich.edu } 1933569Sgblack@eecs.umich.edu} 1943804Ssaidi@eecs.umich.edu 1953804Ssaidi@eecs.umich.edu 1963804Ssaidi@eecs.umich.eduTlbEntry* 1975555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 1985555Snate@binkert.org bool update_used) 1993804Ssaidi@eecs.umich.edu{ 2003804Ssaidi@eecs.umich.edu MapIter i; 2013804Ssaidi@eecs.umich.edu TlbRange tr; 2023804Ssaidi@eecs.umich.edu TlbEntry *t; 2033804Ssaidi@eecs.umich.edu 2043811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2053811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2063804Ssaidi@eecs.umich.edu // Assemble full address structure 2073804Ssaidi@eecs.umich.edu tr.va = va; 2085312Sgblack@eecs.umich.edu tr.size = 1; 2093804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2103804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2113804Ssaidi@eecs.umich.edu tr.real = real; 2123804Ssaidi@eecs.umich.edu 2133804Ssaidi@eecs.umich.edu // Try to find the entry 2143804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2153804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2163811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2173804Ssaidi@eecs.umich.edu return NULL; 2183804Ssaidi@eecs.umich.edu } 2193804Ssaidi@eecs.umich.edu 2203804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2213804Ssaidi@eecs.umich.edu t = i->second; 2223826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2233826Ssaidi@eecs.umich.edu t->pte.size()); 2244070Ssaidi@eecs.umich.edu 2255555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2265555Snate@binkert.org // one from virttophys() 2274070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2283804Ssaidi@eecs.umich.edu t->used = true; 2293804Ssaidi@eecs.umich.edu usedEntries++; 2303804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2313804Ssaidi@eecs.umich.edu clearUsedBits(); 2323804Ssaidi@eecs.umich.edu t->used = true; 2333804Ssaidi@eecs.umich.edu usedEntries++; 2343804Ssaidi@eecs.umich.edu } 2353804Ssaidi@eecs.umich.edu } 2363804Ssaidi@eecs.umich.edu 2373804Ssaidi@eecs.umich.edu return t; 2383804Ssaidi@eecs.umich.edu} 2393804Ssaidi@eecs.umich.edu 2403826Ssaidi@eecs.umich.eduvoid 2413826Ssaidi@eecs.umich.eduTLB::dumpAll() 2423826Ssaidi@eecs.umich.edu{ 2433863Ssaidi@eecs.umich.edu MapIter i; 2443826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2453826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2463826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2473826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2483826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2493826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2503826Ssaidi@eecs.umich.edu } 2513826Ssaidi@eecs.umich.edu } 2523826Ssaidi@eecs.umich.edu} 2533804Ssaidi@eecs.umich.edu 2543804Ssaidi@eecs.umich.eduvoid 2553804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2563804Ssaidi@eecs.umich.edu{ 2573804Ssaidi@eecs.umich.edu TlbRange tr; 2583804Ssaidi@eecs.umich.edu MapIter i; 2593804Ssaidi@eecs.umich.edu 2603863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2613863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2623863Ssaidi@eecs.umich.edu 2633836Ssaidi@eecs.umich.edu cacheValid = false; 2643836Ssaidi@eecs.umich.edu 2653804Ssaidi@eecs.umich.edu // Assemble full address structure 2663804Ssaidi@eecs.umich.edu tr.va = va; 2675312Sgblack@eecs.umich.edu tr.size = 1; 2683804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2693804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2703804Ssaidi@eecs.umich.edu tr.real = real; 2713804Ssaidi@eecs.umich.edu 2723804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2733804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2743804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2753863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2763804Ssaidi@eecs.umich.edu i->second->valid = false; 2773804Ssaidi@eecs.umich.edu if (i->second->used) { 2783804Ssaidi@eecs.umich.edu i->second->used = false; 2793804Ssaidi@eecs.umich.edu usedEntries--; 2803804Ssaidi@eecs.umich.edu } 2813881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2823804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2833804Ssaidi@eecs.umich.edu } 2843804Ssaidi@eecs.umich.edu} 2853804Ssaidi@eecs.umich.edu 2863804Ssaidi@eecs.umich.eduvoid 2873804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2883804Ssaidi@eecs.umich.edu{ 2893863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2903863Ssaidi@eecs.umich.edu partition_id, context_id); 2913836Ssaidi@eecs.umich.edu cacheValid = false; 2925555Snate@binkert.org for (int x = 0; x < size; x++) { 2933804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2943804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 29510231Ssteve.reinhardt@amd.com if (tlb[x].valid) { 2963881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2973881Ssaidi@eecs.umich.edu } 2983804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2993804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3003804Ssaidi@eecs.umich.edu tlb[x].used = false; 3013804Ssaidi@eecs.umich.edu usedEntries--; 3023804Ssaidi@eecs.umich.edu } 3033804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3043804Ssaidi@eecs.umich.edu } 3053804Ssaidi@eecs.umich.edu } 3063804Ssaidi@eecs.umich.edu} 3073804Ssaidi@eecs.umich.edu 3083804Ssaidi@eecs.umich.eduvoid 3093804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3103804Ssaidi@eecs.umich.edu{ 3113863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3123836Ssaidi@eecs.umich.edu cacheValid = false; 3135555Snate@binkert.org for (int x = 0; x < size; x++) { 3145288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3155288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3165288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3173804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3183804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3193804Ssaidi@eecs.umich.edu tlb[x].used = false; 3203804Ssaidi@eecs.umich.edu usedEntries--; 3213804Ssaidi@eecs.umich.edu } 3223804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3233804Ssaidi@eecs.umich.edu } 3243804Ssaidi@eecs.umich.edu } 3253804Ssaidi@eecs.umich.edu} 3263804Ssaidi@eecs.umich.edu 3273804Ssaidi@eecs.umich.eduvoid 3289423SAndreas.Sandberg@arm.comTLB::flushAll() 3293804Ssaidi@eecs.umich.edu{ 3303836Ssaidi@eecs.umich.edu cacheValid = false; 3315555Snate@binkert.org lookupTable.clear(); 3323836Ssaidi@eecs.umich.edu 3335555Snate@binkert.org for (int x = 0; x < size; x++) { 33410231Ssteve.reinhardt@amd.com if (tlb[x].valid) 3353881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3363804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3373907Ssaidi@eecs.umich.edu tlb[x].used = false; 3383804Ssaidi@eecs.umich.edu } 3393804Ssaidi@eecs.umich.edu usedEntries = 0; 3403804Ssaidi@eecs.umich.edu} 3413804Ssaidi@eecs.umich.edu 3423804Ssaidi@eecs.umich.eduuint64_t 3435555Snate@binkert.orgTLB::TteRead(int entry) 3445555Snate@binkert.org{ 3453881Ssaidi@eecs.umich.edu if (entry >= size) 3463881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3473881Ssaidi@eecs.umich.edu 3483804Ssaidi@eecs.umich.edu assert(entry < size); 3493881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3503881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3513881Ssaidi@eecs.umich.edu else 3523881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3533804Ssaidi@eecs.umich.edu} 3543804Ssaidi@eecs.umich.edu 3553804Ssaidi@eecs.umich.eduuint64_t 3565555Snate@binkert.orgTLB::TagRead(int entry) 3575555Snate@binkert.org{ 3583804Ssaidi@eecs.umich.edu assert(entry < size); 3593804Ssaidi@eecs.umich.edu uint64_t tag; 3603881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3613881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3623804Ssaidi@eecs.umich.edu 3633881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3643881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3653881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3663804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3673804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3683804Ssaidi@eecs.umich.edu return tag; 3693804Ssaidi@eecs.umich.edu} 3703804Ssaidi@eecs.umich.edu 3713804Ssaidi@eecs.umich.edubool 3723804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3733804Ssaidi@eecs.umich.edu{ 3743804Ssaidi@eecs.umich.edu if (am) 3753804Ssaidi@eecs.umich.edu return true; 3763804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3773804Ssaidi@eecs.umich.edu return false; 3783804Ssaidi@eecs.umich.edu return true; 3793804Ssaidi@eecs.umich.edu} 3803804Ssaidi@eecs.umich.edu 3813804Ssaidi@eecs.umich.eduvoid 3824990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3833804Ssaidi@eecs.umich.edu{ 3843804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3853804Ssaidi@eecs.umich.edu sfsr = 0x3; 3863804Ssaidi@eecs.umich.edu else 3873804Ssaidi@eecs.umich.edu sfsr = 1; 3883804Ssaidi@eecs.umich.edu 3893804Ssaidi@eecs.umich.edu if (write) 3903804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3913804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3923804Ssaidi@eecs.umich.edu if (se) 3933804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3943804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3953804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3963804Ssaidi@eecs.umich.edu} 3973804Ssaidi@eecs.umich.edu 3983826Ssaidi@eecs.umich.eduvoid 3994990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 4003826Ssaidi@eecs.umich.edu{ 4013916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4023916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4033916Ssaidi@eecs.umich.edu 4044990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4053826Ssaidi@eecs.umich.edu} 4063804Ssaidi@eecs.umich.edu 4073804Ssaidi@eecs.umich.eduvoid 4086022Sgblack@eecs.umich.eduTLB::writeSfsr(Addr a, bool write, ContextType ct, 4093804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4103804Ssaidi@eecs.umich.edu{ 4116022Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4123811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4134990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4144990Sgblack@eecs.umich.edu sfar = a; 4153804Ssaidi@eecs.umich.edu} 4163804Ssaidi@eecs.umich.edu 4173804Ssaidi@eecs.umich.eduFault 4186022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 4193804Ssaidi@eecs.umich.edu{ 4204172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4213833Ssaidi@eecs.umich.edu 4223836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4233836Ssaidi@eecs.umich.edu TlbEntry *e; 4243836Ssaidi@eecs.umich.edu 4259912Sandreas@sandberg.pp.se assert(req->getArchFlags() == ASI_IMPLICIT); 4263836Ssaidi@eecs.umich.edu 4273836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4283836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4293836Ssaidi@eecs.umich.edu 4303836Ssaidi@eecs.umich.edu // Be fast if we can! 4313836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4326022Sgblack@eecs.umich.edu if (cacheEntry[0]) { 4336022Sgblack@eecs.umich.edu if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 4346022Sgblack@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4356022Sgblack@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 4365555Snate@binkert.org return NoFault; 4373836Ssaidi@eecs.umich.edu } 4383836Ssaidi@eecs.umich.edu } else { 4393836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4403836Ssaidi@eecs.umich.edu return NoFault; 4413836Ssaidi@eecs.umich.edu } 4423836Ssaidi@eecs.umich.edu } 4433836Ssaidi@eecs.umich.edu 4443833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4453833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4463833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4473833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4483833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4493833Ssaidi@eecs.umich.edu 4503833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4513833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4523833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4533804Ssaidi@eecs.umich.edu int context; 4543804Ssaidi@eecs.umich.edu ContextType ct; 4553804Ssaidi@eecs.umich.edu int asi; 4563804Ssaidi@eecs.umich.edu bool real = false; 4573804Ssaidi@eecs.umich.edu 4583833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4593833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4603811Ssaidi@eecs.umich.edu 4613804Ssaidi@eecs.umich.edu if (tl > 0) { 4623804Ssaidi@eecs.umich.edu asi = ASI_N; 4633804Ssaidi@eecs.umich.edu ct = Nucleus; 4643804Ssaidi@eecs.umich.edu context = 0; 4653804Ssaidi@eecs.umich.edu } else { 4663804Ssaidi@eecs.umich.edu asi = ASI_P; 4673804Ssaidi@eecs.umich.edu ct = Primary; 4683833Ssaidi@eecs.umich.edu context = pri_context; 4693804Ssaidi@eecs.umich.edu } 4703804Ssaidi@eecs.umich.edu 4713833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4723836Ssaidi@eecs.umich.edu cacheValid = true; 4733836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4746022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 4753836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4763804Ssaidi@eecs.umich.edu return NoFault; 4773804Ssaidi@eecs.umich.edu } 4783804Ssaidi@eecs.umich.edu 4793836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4803836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4814990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 48210474Sandreas.hansson@arm.com return std::make_shared<MemAddressNotAligned>(); 4833804Ssaidi@eecs.umich.edu } 4843804Ssaidi@eecs.umich.edu 4853804Ssaidi@eecs.umich.edu if (addr_mask) 4863804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4873804Ssaidi@eecs.umich.edu 4883804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4894990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 49010474Sandreas.hansson@arm.com return std::make_shared<InstructionAccessException>(); 4913804Ssaidi@eecs.umich.edu } 4923804Ssaidi@eecs.umich.edu 4933833Ssaidi@eecs.umich.edu if (!lsu_im) { 4943836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4953804Ssaidi@eecs.umich.edu real = true; 4963804Ssaidi@eecs.umich.edu context = 0; 4973804Ssaidi@eecs.umich.edu } else { 4983804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4993804Ssaidi@eecs.umich.edu } 5003804Ssaidi@eecs.umich.edu 5013804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5024990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5038751Sgblack@eecs.umich.edu if (real) { 50410474Sandreas.hansson@arm.com return std::make_shared<InstructionRealTranslationMiss>(); 5058751Sgblack@eecs.umich.edu } else { 5068751Sgblack@eecs.umich.edu if (FullSystem) 50710474Sandreas.hansson@arm.com return std::make_shared<FastInstructionAccessMMUMiss>(); 5088751Sgblack@eecs.umich.edu else 50910474Sandreas.hansson@arm.com return std::make_shared<FastInstructionAccessMMUMiss>( 51010474Sandreas.hansson@arm.com req->getVaddr()); 5118751Sgblack@eecs.umich.edu } 5123804Ssaidi@eecs.umich.edu } 5133804Ssaidi@eecs.umich.edu 5143804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5153804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5164990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5174990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 51810474Sandreas.hansson@arm.com return std::make_shared<InstructionAccessException>(); 5193804Ssaidi@eecs.umich.edu } 5203804Ssaidi@eecs.umich.edu 5213836Ssaidi@eecs.umich.edu // cache translation date for next translation 5223836Ssaidi@eecs.umich.edu cacheValid = true; 5233836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5246022Sgblack@eecs.umich.edu cacheEntry[0] = e; 5253836Ssaidi@eecs.umich.edu 5265555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5273836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5283804Ssaidi@eecs.umich.edu return NoFault; 5293804Ssaidi@eecs.umich.edu} 5303804Ssaidi@eecs.umich.edu 5313804Ssaidi@eecs.umich.eduFault 5326022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 5333804Ssaidi@eecs.umich.edu{ 5345555Snate@binkert.org /* 5355555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5365555Snate@binkert.org * it faster! 5375555Snate@binkert.org */ 5384172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5393836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5403836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5413836Ssaidi@eecs.umich.edu ASI asi; 5429912Sandreas@sandberg.pp.se asi = (ASI)req->getArchFlags(); 5433836Ssaidi@eecs.umich.edu bool implicit = false; 5443836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5455570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5463833Ssaidi@eecs.umich.edu 5473836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5483836Ssaidi@eecs.umich.edu vaddr, size, asi); 5493836Ssaidi@eecs.umich.edu 5503929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5513929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5523929Ssaidi@eecs.umich.edu freeList.size()); 5533836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5543836Ssaidi@eecs.umich.edu implicit = true; 5553836Ssaidi@eecs.umich.edu 5564996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5574996Sgblack@eecs.umich.edu // trap later 5584996Sgblack@eecs.umich.edu if (!unaligned) { 5594996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5604996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5614996Sgblack@eecs.umich.edu return NoFault; 5624996Sgblack@eecs.umich.edu } 5634996Sgblack@eecs.umich.edu 5644996Sgblack@eecs.umich.edu // Be fast if we can! 5654996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5664996Sgblack@eecs.umich.edu 5674996Sgblack@eecs.umich.edu 5684996Sgblack@eecs.umich.edu 5694996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5704996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5714996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5724996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5734996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5744996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5755555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 57610824SAndreas.Sandberg@ARM.com if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 57710824SAndreas.Sandberg@ARM.com req->setFlags( 57810824SAndreas.Sandberg@ARM.com Request::UNCACHEABLE | Request::STRICT_ORDER); 57910824SAndreas.Sandberg@ARM.com } 5805555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5815555Snate@binkert.org return NoFault; 5824996Sgblack@eecs.umich.edu } // if matched 5834996Sgblack@eecs.umich.edu } // if cache entry valid 5844996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 5854996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 5864996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5874996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 5884996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5894996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5905555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 59110824SAndreas.Sandberg@ARM.com if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 59210824SAndreas.Sandberg@ARM.com req->setFlags( 59310824SAndreas.Sandberg@ARM.com Request::UNCACHEABLE | Request::STRICT_ORDER); 59410824SAndreas.Sandberg@ARM.com } 5955555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5965555Snate@binkert.org return NoFault; 5974996Sgblack@eecs.umich.edu } // if matched 5984996Sgblack@eecs.umich.edu } // if cache entry valid 5994996Sgblack@eecs.umich.edu } 6003836Ssaidi@eecs.umich.edu } 6013836Ssaidi@eecs.umich.edu 6023833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6033833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6043833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6053833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6063833Ssaidi@eecs.umich.edu 6073833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6083833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6093833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6103916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6113833Ssaidi@eecs.umich.edu 6123804Ssaidi@eecs.umich.edu bool real = false; 6133832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6143832Ssaidi@eecs.umich.edu int context = 0; 6153804Ssaidi@eecs.umich.edu 6163804Ssaidi@eecs.umich.edu TlbEntry *e; 6173804Ssaidi@eecs.umich.edu 6183833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6195555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6203804Ssaidi@eecs.umich.edu 6213804Ssaidi@eecs.umich.edu if (implicit) { 6223804Ssaidi@eecs.umich.edu if (tl > 0) { 6233804Ssaidi@eecs.umich.edu asi = ASI_N; 6243804Ssaidi@eecs.umich.edu ct = Nucleus; 6253804Ssaidi@eecs.umich.edu context = 0; 6263804Ssaidi@eecs.umich.edu } else { 6273804Ssaidi@eecs.umich.edu asi = ASI_P; 6283804Ssaidi@eecs.umich.edu ct = Primary; 6293833Ssaidi@eecs.umich.edu context = pri_context; 6303804Ssaidi@eecs.umich.edu } 6313910Ssaidi@eecs.umich.edu } else { 6323804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6337741Sgblack@eecs.umich.edu if (!priv && !hpriv && !asiIsUnPriv(asi)) { 6343804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6354990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 63610474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 6373804Ssaidi@eecs.umich.edu } 6383910Ssaidi@eecs.umich.edu 6397741Sgblack@eecs.umich.edu if (!hpriv && asiIsHPriv(asi)) { 6404990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 64110474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 6423804Ssaidi@eecs.umich.edu } 6433804Ssaidi@eecs.umich.edu 6447741Sgblack@eecs.umich.edu if (asiIsPrimary(asi)) { 6453910Ssaidi@eecs.umich.edu context = pri_context; 6463910Ssaidi@eecs.umich.edu ct = Primary; 6477741Sgblack@eecs.umich.edu } else if (asiIsSecondary(asi)) { 6483910Ssaidi@eecs.umich.edu context = sec_context; 6493910Ssaidi@eecs.umich.edu ct = Secondary; 6507741Sgblack@eecs.umich.edu } else if (asiIsNucleus(asi)) { 6513910Ssaidi@eecs.umich.edu ct = Nucleus; 6523910Ssaidi@eecs.umich.edu context = 0; 6533910Ssaidi@eecs.umich.edu } else { // ???? 6543910Ssaidi@eecs.umich.edu ct = Primary; 6553910Ssaidi@eecs.umich.edu context = pri_context; 6563910Ssaidi@eecs.umich.edu } 6573902Ssaidi@eecs.umich.edu } 6583804Ssaidi@eecs.umich.edu 6593926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6607741Sgblack@eecs.umich.edu if (asiIsLittle(asi)) 6613804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6624989Sgblack@eecs.umich.edu 6634989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6647741Sgblack@eecs.umich.edu // load differs from a regular one, other than what happens concerning 6657741Sgblack@eecs.umich.edu // nfo and e bits in the TTE 6667741Sgblack@eecs.umich.edu// if (asiIsNoFault(asi)) 6674989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6683856Ssaidi@eecs.umich.edu 6697741Sgblack@eecs.umich.edu if (asiIsPartialStore(asi)) 6703804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6714103Ssaidi@eecs.umich.edu 6727741Sgblack@eecs.umich.edu if (asiIsCmt(asi)) 6734191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6744191Ssaidi@eecs.umich.edu 6757741Sgblack@eecs.umich.edu if (asiIsInterrupt(asi)) 6764103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6777741Sgblack@eecs.umich.edu if (asiIsMmu(asi)) 6783804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6797741Sgblack@eecs.umich.edu if (asiIsScratchPad(asi)) 6803804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6817741Sgblack@eecs.umich.edu if (asiIsQueue(asi)) 6823824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6837741Sgblack@eecs.umich.edu if (asiIsSparcError(asi)) 6843825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6853823Ssaidi@eecs.umich.edu 6867741Sgblack@eecs.umich.edu if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 6877741Sgblack@eecs.umich.edu !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 6883823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6893804Ssaidi@eecs.umich.edu } 6903804Ssaidi@eecs.umich.edu 6913826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6924996Sgblack@eecs.umich.edu if (unaligned) { 6934990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 69410474Sandreas.hansson@arm.com return std::make_shared<MemAddressNotAligned>(); 6953826Ssaidi@eecs.umich.edu } 6963826Ssaidi@eecs.umich.edu 6973826Ssaidi@eecs.umich.edu if (addr_mask) 6983826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6993826Ssaidi@eecs.umich.edu 7003826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7014990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 70210474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7033826Ssaidi@eecs.umich.edu } 7043826Ssaidi@eecs.umich.edu 7057741Sgblack@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 7063804Ssaidi@eecs.umich.edu real = true; 7073804Ssaidi@eecs.umich.edu context = 0; 7085555Snate@binkert.org } 7093804Ssaidi@eecs.umich.edu 7107741Sgblack@eecs.umich.edu if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 7113836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7123804Ssaidi@eecs.umich.edu return NoFault; 7133804Ssaidi@eecs.umich.edu } 7143804Ssaidi@eecs.umich.edu 7153836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7163804Ssaidi@eecs.umich.edu 7173804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7184990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7193811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7208751Sgblack@eecs.umich.edu if (real) { 72110474Sandreas.hansson@arm.com return std::make_shared<DataRealTranslationMiss>(); 7228751Sgblack@eecs.umich.edu } else { 7238751Sgblack@eecs.umich.edu if (FullSystem) 72410474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessMMUMiss>(); 7258751Sgblack@eecs.umich.edu else 72610474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessMMUMiss>( 72710474Sandreas.hansson@arm.com req->getVaddr()); 7288751Sgblack@eecs.umich.edu } 7293804Ssaidi@eecs.umich.edu 7303804Ssaidi@eecs.umich.edu } 7313804Ssaidi@eecs.umich.edu 7323928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7334990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7344990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 73510474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7363928Ssaidi@eecs.umich.edu } 7373804Ssaidi@eecs.umich.edu 7383804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7394990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7404990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 74110474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessProtection>(); 7423804Ssaidi@eecs.umich.edu } 7433804Ssaidi@eecs.umich.edu 7447741Sgblack@eecs.umich.edu if (e->pte.nofault() && !asiIsNoFault(asi)) { 7454990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7464990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 74710474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7483804Ssaidi@eecs.umich.edu } 7493804Ssaidi@eecs.umich.edu 7507741Sgblack@eecs.umich.edu if (e->pte.sideffect() && asiIsNoFault(asi)) { 7514990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7524990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 75310474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7543928Ssaidi@eecs.umich.edu } 7553928Ssaidi@eecs.umich.edu 7564090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 75710824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 7583804Ssaidi@eecs.umich.edu 7593836Ssaidi@eecs.umich.edu // cache translation date for next translation 7603836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7613881Ssaidi@eecs.umich.edu if (!cacheValid) { 7623881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7633881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7643881Ssaidi@eecs.umich.edu } 7653881Ssaidi@eecs.umich.edu 7663836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7673836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7683836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7693836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7703836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7713836Ssaidi@eecs.umich.edu if (implicit) 7723836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7733836Ssaidi@eecs.umich.edu } 7743881Ssaidi@eecs.umich.edu cacheValid = true; 7755555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7763836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7773804Ssaidi@eecs.umich.edu return NoFault; 7784103Ssaidi@eecs.umich.edu 7793806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7804103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7814103Ssaidi@eecs.umich.edu if (!hpriv) { 7824990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7834103Ssaidi@eecs.umich.edu if (priv) 78410474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7854103Ssaidi@eecs.umich.edu else 78610474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 7874103Ssaidi@eecs.umich.edu } 7884103Ssaidi@eecs.umich.edu 7895570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 7905570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 7914990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 79210474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7934103Ssaidi@eecs.umich.edu } 7944103Ssaidi@eecs.umich.edu 7954103Ssaidi@eecs.umich.edu goto regAccessOk; 7964103Ssaidi@eecs.umich.edu 7973804Ssaidi@eecs.umich.edu 7983806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7993806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8004990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 80110474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8023806Ssaidi@eecs.umich.edu } 8033824Ssaidi@eecs.umich.edu goto regAccessOk; 8043824Ssaidi@eecs.umich.edu 8053824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8063824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8074990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 80810474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 8093824Ssaidi@eecs.umich.edu } 8105570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8114990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 81210474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8133824Ssaidi@eecs.umich.edu } 8143824Ssaidi@eecs.umich.edu goto regAccessOk; 8153824Ssaidi@eecs.umich.edu 8163825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8173825Ssaidi@eecs.umich.edu if (!hpriv) { 8184990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8194070Ssaidi@eecs.umich.edu if (priv) 82010474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8214070Ssaidi@eecs.umich.edu else 82210474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 8233825Ssaidi@eecs.umich.edu } 8243825Ssaidi@eecs.umich.edu goto regAccessOk; 8253825Ssaidi@eecs.umich.edu 8263825Ssaidi@eecs.umich.edu 8273824Ssaidi@eecs.umich.eduregAccessOk: 8283804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8293811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8308105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 8313806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8323806Ssaidi@eecs.umich.edu return NoFault; 8333804Ssaidi@eecs.umich.edu}; 8343804Ssaidi@eecs.umich.edu 8356022Sgblack@eecs.umich.eduFault 8366023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 8376022Sgblack@eecs.umich.edu{ 8386023Snate@binkert.org if (mode == Execute) 8396022Sgblack@eecs.umich.edu return translateInst(req, tc); 8406022Sgblack@eecs.umich.edu else 8416023Snate@binkert.org return translateData(req, tc, mode == Write); 8426022Sgblack@eecs.umich.edu} 8436022Sgblack@eecs.umich.edu 8445894Sgblack@eecs.umich.eduvoid 8456022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 8466023Snate@binkert.org Translation *translation, Mode mode) 8475894Sgblack@eecs.umich.edu{ 8485894Sgblack@eecs.umich.edu assert(translation); 8496023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 8505894Sgblack@eecs.umich.edu} 8515894Sgblack@eecs.umich.edu 8528888Sgeoffrey.blake@arm.comFault 8539738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 8549738Sandreas@sandberg.pp.se{ 8559738Sandreas@sandberg.pp.se return NoFault; 8569738Sandreas@sandberg.pp.se} 8579738Sandreas@sandberg.pp.se 8589180Sandreas.hansson@arm.comCycles 8596022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8603806Ssaidi@eecs.umich.edu{ 8613823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8629912Sandreas@sandberg.pp.se ASI asi = (ASI)pkt->req->getArchFlags(); 8634070Ssaidi@eecs.umich.edu uint64_t temp; 8643823Ssaidi@eecs.umich.edu 8653823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8669912Sandreas@sandberg.pp.se (uint32_t)pkt->req->getArchFlags(), pkt->getAddr()); 8673823Ssaidi@eecs.umich.edu 86812406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 8694990Sgblack@eecs.umich.edu 8703823Ssaidi@eecs.umich.edu switch (asi) { 8713823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8723823Ssaidi@eecs.umich.edu assert(va == 0); 8734172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8743823Ssaidi@eecs.umich.edu break; 8753823Ssaidi@eecs.umich.edu case ASI_MMU: 8763823Ssaidi@eecs.umich.edu switch (va) { 8773823Ssaidi@eecs.umich.edu case 0x8: 8784172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8793823Ssaidi@eecs.umich.edu break; 8803823Ssaidi@eecs.umich.edu case 0x10: 8814172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8823823Ssaidi@eecs.umich.edu break; 8833823Ssaidi@eecs.umich.edu default: 8843823Ssaidi@eecs.umich.edu goto doMmuReadError; 8853823Ssaidi@eecs.umich.edu } 8863823Ssaidi@eecs.umich.edu break; 8873824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8884172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8893824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8903824Ssaidi@eecs.umich.edu break; 8913823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8923823Ssaidi@eecs.umich.edu assert(va == 0); 8934990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 8943823Ssaidi@eecs.umich.edu break; 8953823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8963823Ssaidi@eecs.umich.edu assert(va == 0); 8974990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 8983823Ssaidi@eecs.umich.edu break; 8993823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9003823Ssaidi@eecs.umich.edu assert(va == 0); 9014990Sgblack@eecs.umich.edu pkt->set(c0_config); 9023823Ssaidi@eecs.umich.edu break; 9033823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9043823Ssaidi@eecs.umich.edu assert(va == 0); 9054990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9063823Ssaidi@eecs.umich.edu break; 9073823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9083823Ssaidi@eecs.umich.edu assert(va == 0); 9094990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9103823Ssaidi@eecs.umich.edu break; 9113823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9123823Ssaidi@eecs.umich.edu assert(va == 0); 9134990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9143823Ssaidi@eecs.umich.edu break; 9153823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9163823Ssaidi@eecs.umich.edu assert(va == 0); 9174990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9183823Ssaidi@eecs.umich.edu break; 9193823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9203823Ssaidi@eecs.umich.edu assert(va == 0); 9214990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9223823Ssaidi@eecs.umich.edu break; 9233823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9243823Ssaidi@eecs.umich.edu assert(va == 0); 9254990Sgblack@eecs.umich.edu pkt->set(cx_config); 9263823Ssaidi@eecs.umich.edu break; 9273823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9283823Ssaidi@eecs.umich.edu assert(va == 0); 9294990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9303823Ssaidi@eecs.umich.edu break; 9313823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9323823Ssaidi@eecs.umich.edu assert(va == 0); 9334990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9343823Ssaidi@eecs.umich.edu break; 9353823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9363823Ssaidi@eecs.umich.edu assert(va == 0); 9374990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9383823Ssaidi@eecs.umich.edu break; 9393826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9403912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9413826Ssaidi@eecs.umich.edu break; 9423823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9433823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9444172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9453823Ssaidi@eecs.umich.edu break; 9463826Ssaidi@eecs.umich.edu case ASI_IMMU: 9473826Ssaidi@eecs.umich.edu switch (va) { 9483833Ssaidi@eecs.umich.edu case 0x0: 9494990Sgblack@eecs.umich.edu temp = itb->tag_access; 9503833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9513833Ssaidi@eecs.umich.edu break; 9523906Ssaidi@eecs.umich.edu case 0x18: 9534990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9543906Ssaidi@eecs.umich.edu break; 9553826Ssaidi@eecs.umich.edu case 0x30: 9564990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9573826Ssaidi@eecs.umich.edu break; 9583826Ssaidi@eecs.umich.edu default: 9593826Ssaidi@eecs.umich.edu goto doMmuReadError; 9603826Ssaidi@eecs.umich.edu } 9613826Ssaidi@eecs.umich.edu break; 9623823Ssaidi@eecs.umich.edu case ASI_DMMU: 9633823Ssaidi@eecs.umich.edu switch (va) { 9643833Ssaidi@eecs.umich.edu case 0x0: 9654990Sgblack@eecs.umich.edu temp = tag_access; 9663833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9673833Ssaidi@eecs.umich.edu break; 9683906Ssaidi@eecs.umich.edu case 0x18: 9694990Sgblack@eecs.umich.edu pkt->set(sfsr); 9703906Ssaidi@eecs.umich.edu break; 9713906Ssaidi@eecs.umich.edu case 0x20: 9724990Sgblack@eecs.umich.edu pkt->set(sfar); 9733906Ssaidi@eecs.umich.edu break; 9743826Ssaidi@eecs.umich.edu case 0x30: 9754990Sgblack@eecs.umich.edu pkt->set(tag_access); 9763826Ssaidi@eecs.umich.edu break; 9773823Ssaidi@eecs.umich.edu case 0x80: 9784172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9793823Ssaidi@eecs.umich.edu break; 9803823Ssaidi@eecs.umich.edu default: 9813823Ssaidi@eecs.umich.edu goto doMmuReadError; 9823823Ssaidi@eecs.umich.edu } 9833823Ssaidi@eecs.umich.edu break; 9843833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9854070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9864990Sgblack@eecs.umich.edu tag_access, 9874990Sgblack@eecs.umich.edu c0_tsb_ps0, 9884990Sgblack@eecs.umich.edu c0_config, 9894990Sgblack@eecs.umich.edu cx_tsb_ps0, 9904990Sgblack@eecs.umich.edu cx_config)); 9913833Ssaidi@eecs.umich.edu break; 9923833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9934070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9944990Sgblack@eecs.umich.edu tag_access, 9954990Sgblack@eecs.umich.edu c0_tsb_ps1, 9964990Sgblack@eecs.umich.edu c0_config, 9974990Sgblack@eecs.umich.edu cx_tsb_ps1, 9984990Sgblack@eecs.umich.edu cx_config)); 9993833Ssaidi@eecs.umich.edu break; 10003899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 10014070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10024990Sgblack@eecs.umich.edu itb->tag_access, 10034990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10044990Sgblack@eecs.umich.edu itb->c0_config, 10054990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10064990Sgblack@eecs.umich.edu itb->cx_config)); 10073899Ssaidi@eecs.umich.edu break; 10083899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10094070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10104990Sgblack@eecs.umich.edu itb->tag_access, 10114990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10124990Sgblack@eecs.umich.edu itb->c0_config, 10134990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10144990Sgblack@eecs.umich.edu itb->cx_config)); 10153899Ssaidi@eecs.umich.edu break; 10164103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10175646Sgblack@eecs.umich.edu { 10185646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10195646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 102011150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 10215646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10225646Sgblack@eecs.umich.edu } 10234103Ssaidi@eecs.umich.edu break; 10244103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10255646Sgblack@eecs.umich.edu { 10265646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10275646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 102811150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 10295646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 103011150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp); 10315646Sgblack@eecs.umich.edu pkt->set(temp); 10325646Sgblack@eecs.umich.edu } 10334103Ssaidi@eecs.umich.edu break; 10343823Ssaidi@eecs.umich.edu default: 10353823Ssaidi@eecs.umich.edudoMmuReadError: 10363823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10373823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10383823Ssaidi@eecs.umich.edu } 10394870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10409180Sandreas.hansson@arm.com return Cycles(1); 10413806Ssaidi@eecs.umich.edu} 10423806Ssaidi@eecs.umich.edu 10439180Sandreas.hansson@arm.comCycles 10446022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10453806Ssaidi@eecs.umich.edu{ 10467518Sgblack@eecs.umich.edu uint64_t data = pkt->get<uint64_t>(); 10473823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10489912Sandreas@sandberg.pp.se ASI asi = (ASI)pkt->req->getArchFlags(); 10493823Ssaidi@eecs.umich.edu 10503826Ssaidi@eecs.umich.edu Addr ta_insert; 10513826Ssaidi@eecs.umich.edu Addr va_insert; 10523826Ssaidi@eecs.umich.edu Addr ct_insert; 10533826Ssaidi@eecs.umich.edu int part_insert; 10543826Ssaidi@eecs.umich.edu int entry_insert = -1; 10553826Ssaidi@eecs.umich.edu bool real_insert; 10563863Ssaidi@eecs.umich.edu bool ignore; 10573863Ssaidi@eecs.umich.edu int part_id; 10583863Ssaidi@eecs.umich.edu int ctx_id; 10593826Ssaidi@eecs.umich.edu PageTableEntry pte; 10603826Ssaidi@eecs.umich.edu 10613825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10623823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10633823Ssaidi@eecs.umich.edu 106412406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 10654990Sgblack@eecs.umich.edu 10663823Ssaidi@eecs.umich.edu switch (asi) { 10673823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10683823Ssaidi@eecs.umich.edu assert(va == 0); 10694172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10703823Ssaidi@eecs.umich.edu break; 10713823Ssaidi@eecs.umich.edu case ASI_MMU: 10723823Ssaidi@eecs.umich.edu switch (va) { 10733823Ssaidi@eecs.umich.edu case 0x8: 10744172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10753823Ssaidi@eecs.umich.edu break; 10763823Ssaidi@eecs.umich.edu case 0x10: 10774172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10783823Ssaidi@eecs.umich.edu break; 10793823Ssaidi@eecs.umich.edu default: 10803823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10813823Ssaidi@eecs.umich.edu } 10823823Ssaidi@eecs.umich.edu break; 10833824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10843825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10854172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10863824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10873824Ssaidi@eecs.umich.edu break; 10883823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10893823Ssaidi@eecs.umich.edu assert(va == 0); 10904990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10913823Ssaidi@eecs.umich.edu break; 10923823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10933823Ssaidi@eecs.umich.edu assert(va == 0); 10944990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10953823Ssaidi@eecs.umich.edu break; 10963823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10973823Ssaidi@eecs.umich.edu assert(va == 0); 10984990Sgblack@eecs.umich.edu c0_config = data; 10993823Ssaidi@eecs.umich.edu break; 11003823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 11013823Ssaidi@eecs.umich.edu assert(va == 0); 11024990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 11033823Ssaidi@eecs.umich.edu break; 11043823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 11053823Ssaidi@eecs.umich.edu assert(va == 0); 11064990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11073823Ssaidi@eecs.umich.edu break; 11083823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11093823Ssaidi@eecs.umich.edu assert(va == 0); 11104990Sgblack@eecs.umich.edu itb->c0_config = data; 11113823Ssaidi@eecs.umich.edu break; 11123823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11133823Ssaidi@eecs.umich.edu assert(va == 0); 11144990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11153823Ssaidi@eecs.umich.edu break; 11163823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11173823Ssaidi@eecs.umich.edu assert(va == 0); 11184990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11193823Ssaidi@eecs.umich.edu break; 11203823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11213823Ssaidi@eecs.umich.edu assert(va == 0); 11224990Sgblack@eecs.umich.edu cx_config = data; 11233823Ssaidi@eecs.umich.edu break; 11243823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11253823Ssaidi@eecs.umich.edu assert(va == 0); 11264990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11273823Ssaidi@eecs.umich.edu break; 11283823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11293823Ssaidi@eecs.umich.edu assert(va == 0); 11304990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11313823Ssaidi@eecs.umich.edu break; 11323823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11333823Ssaidi@eecs.umich.edu assert(va == 0); 11344990Sgblack@eecs.umich.edu itb->cx_config = data; 11353823Ssaidi@eecs.umich.edu break; 11363825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11373825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11385823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11393825Ssaidi@eecs.umich.edu break; 11403823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11413823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11424172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11433823Ssaidi@eecs.umich.edu break; 11443826Ssaidi@eecs.umich.edu case ASI_IMMU: 11453826Ssaidi@eecs.umich.edu switch (va) { 11463906Ssaidi@eecs.umich.edu case 0x18: 11474990Sgblack@eecs.umich.edu itb->sfsr = data; 11483906Ssaidi@eecs.umich.edu break; 11493826Ssaidi@eecs.umich.edu case 0x30: 11503916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11514990Sgblack@eecs.umich.edu itb->tag_access = data; 11523826Ssaidi@eecs.umich.edu break; 11533826Ssaidi@eecs.umich.edu default: 11543826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11553826Ssaidi@eecs.umich.edu } 11563826Ssaidi@eecs.umich.edu break; 11573826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11583826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 115912620Sgabeblack@google.com M5_FALLTHROUGH; 11603826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11613826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11624990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11633826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11643826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11654172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11663826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11673826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11683826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 116912406Sgabeblack@google.com itb->insert(va_insert, part_insert, ct_insert, real_insert, 117012406Sgabeblack@google.com pte, entry_insert); 11713826Ssaidi@eecs.umich.edu break; 11723826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11733826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 117412620Sgabeblack@google.com M5_FALLTHROUGH; 11753826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11763826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11774990Sgblack@eecs.umich.edu ta_insert = tag_access; 11783826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11793826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11804172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11813826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11823826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11833826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11845555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11855555Snate@binkert.org entry_insert); 11863826Ssaidi@eecs.umich.edu break; 11873863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11883863Ssaidi@eecs.umich.edu ignore = false; 11893863Ssaidi@eecs.umich.edu ctx_id = -1; 11904172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11913863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11923863Ssaidi@eecs.umich.edu case 0: 11934172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11943863Ssaidi@eecs.umich.edu break; 11953863Ssaidi@eecs.umich.edu case 1: 11963863Ssaidi@eecs.umich.edu ignore = true; 11973863Ssaidi@eecs.umich.edu break; 11983863Ssaidi@eecs.umich.edu case 3: 11993863Ssaidi@eecs.umich.edu ctx_id = 0; 12003863Ssaidi@eecs.umich.edu break; 12013863Ssaidi@eecs.umich.edu default: 12023863Ssaidi@eecs.umich.edu ignore = true; 12033863Ssaidi@eecs.umich.edu } 12043863Ssaidi@eecs.umich.edu 12057741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12063863Ssaidi@eecs.umich.edu case 0: // demap page 12073863Ssaidi@eecs.umich.edu if (!ignore) 120812406Sgabeblack@google.com itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12093863Ssaidi@eecs.umich.edu break; 12107741Sgblack@eecs.umich.edu case 1: // demap context 12113863Ssaidi@eecs.umich.edu if (!ignore) 121212406Sgabeblack@google.com itb->demapContext(part_id, ctx_id); 12133863Ssaidi@eecs.umich.edu break; 12143863Ssaidi@eecs.umich.edu case 2: 121512406Sgabeblack@google.com itb->demapAll(part_id); 12163863Ssaidi@eecs.umich.edu break; 12173863Ssaidi@eecs.umich.edu default: 12183863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12193863Ssaidi@eecs.umich.edu } 12203863Ssaidi@eecs.umich.edu break; 12213823Ssaidi@eecs.umich.edu case ASI_DMMU: 12223823Ssaidi@eecs.umich.edu switch (va) { 12233906Ssaidi@eecs.umich.edu case 0x18: 12244990Sgblack@eecs.umich.edu sfsr = data; 12253906Ssaidi@eecs.umich.edu break; 12263826Ssaidi@eecs.umich.edu case 0x30: 12273916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12284990Sgblack@eecs.umich.edu tag_access = data; 12293826Ssaidi@eecs.umich.edu break; 12303823Ssaidi@eecs.umich.edu case 0x80: 12314172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12323823Ssaidi@eecs.umich.edu break; 12333823Ssaidi@eecs.umich.edu default: 12343823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12353823Ssaidi@eecs.umich.edu } 12363823Ssaidi@eecs.umich.edu break; 12373863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12383863Ssaidi@eecs.umich.edu ignore = false; 12393863Ssaidi@eecs.umich.edu ctx_id = -1; 12404172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12413863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12423863Ssaidi@eecs.umich.edu case 0: 12434172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12443863Ssaidi@eecs.umich.edu break; 12453863Ssaidi@eecs.umich.edu case 1: 12464172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12473863Ssaidi@eecs.umich.edu break; 12483863Ssaidi@eecs.umich.edu case 3: 12493863Ssaidi@eecs.umich.edu ctx_id = 0; 12503863Ssaidi@eecs.umich.edu break; 12513863Ssaidi@eecs.umich.edu default: 12523863Ssaidi@eecs.umich.edu ignore = true; 12533863Ssaidi@eecs.umich.edu } 12543863Ssaidi@eecs.umich.edu 12557741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12563863Ssaidi@eecs.umich.edu case 0: // demap page 12573863Ssaidi@eecs.umich.edu if (!ignore) 12583863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12593863Ssaidi@eecs.umich.edu break; 12607741Sgblack@eecs.umich.edu case 1: // demap context 12613863Ssaidi@eecs.umich.edu if (!ignore) 12623863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12633863Ssaidi@eecs.umich.edu break; 12643863Ssaidi@eecs.umich.edu case 2: 12653863Ssaidi@eecs.umich.edu demapAll(part_id); 12663863Ssaidi@eecs.umich.edu break; 12673863Ssaidi@eecs.umich.edu default: 12683863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12693863Ssaidi@eecs.umich.edu } 12703863Ssaidi@eecs.umich.edu break; 12714103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12725646Sgblack@eecs.umich.edu { 12735646Sgblack@eecs.umich.edu int msb; 12745646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12755646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12765646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 127711150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 12785704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12795646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 128011150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb); 12815646Sgblack@eecs.umich.edu } 12824103Ssaidi@eecs.umich.edu } 12834103Ssaidi@eecs.umich.edu break; 12844103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12854103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 128611150Smitch.hayenga@arm.com postInterrupt(0, bits(data, 5, 0), 0); 12874103Ssaidi@eecs.umich.edu break; 12885555Snate@binkert.org default: 12893823Ssaidi@eecs.umich.edudoMmuWriteError: 12903823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12919912Sandreas@sandberg.pp.se (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data); 12923823Ssaidi@eecs.umich.edu } 12934870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12949180Sandreas.hansson@arm.com return Cycles(1); 12953806Ssaidi@eecs.umich.edu} 12963806Ssaidi@eecs.umich.edu 12973804Ssaidi@eecs.umich.eduvoid 12986022Sgblack@eecs.umich.eduTLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12994070Ssaidi@eecs.umich.edu{ 13004070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 130112406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 13024070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 13034990Sgblack@eecs.umich.edu c0_tsb_ps0, 13044990Sgblack@eecs.umich.edu c0_config, 13054990Sgblack@eecs.umich.edu cx_tsb_ps0, 13064990Sgblack@eecs.umich.edu cx_config); 13074070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 13084990Sgblack@eecs.umich.edu c0_tsb_ps1, 13094990Sgblack@eecs.umich.edu c0_config, 13104990Sgblack@eecs.umich.edu cx_tsb_ps1, 13114990Sgblack@eecs.umich.edu cx_config); 13124070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13134990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13144990Sgblack@eecs.umich.edu itb->c0_config, 13154990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13164990Sgblack@eecs.umich.edu itb->cx_config); 13174070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13184990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13194990Sgblack@eecs.umich.edu itb->c0_config, 13204990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13214990Sgblack@eecs.umich.edu itb->cx_config); 13224070Ssaidi@eecs.umich.edu} 13234070Ssaidi@eecs.umich.edu 13244070Ssaidi@eecs.umich.eduuint64_t 13256022Sgblack@eecs.umich.eduTLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13264070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13274070Ssaidi@eecs.umich.edu{ 13284070Ssaidi@eecs.umich.edu uint64_t tsb; 13294070Ssaidi@eecs.umich.edu uint64_t config; 13304070Ssaidi@eecs.umich.edu 13314070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13324070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13334070Ssaidi@eecs.umich.edu config = c0_config; 13344070Ssaidi@eecs.umich.edu } else { 13354070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13364070Ssaidi@eecs.umich.edu config = cX_config; 13374070Ssaidi@eecs.umich.edu } 13384070Ssaidi@eecs.umich.edu 13394070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13404070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13414070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13424070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13434070Ssaidi@eecs.umich.edu 13444070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13454070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13464070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13474070Ssaidi@eecs.umich.edu 13484070Ssaidi@eecs.umich.edu return ptr; 13494070Ssaidi@eecs.umich.edu} 13504070Ssaidi@eecs.umich.edu 13514070Ssaidi@eecs.umich.eduvoid 135210905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 13533804Ssaidi@eecs.umich.edu{ 13544000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13554000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13564000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13574000Ssaidi@eecs.umich.edu 13584000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 135910905Sandreas.sandberg@arm.com std::vector<int> free_list; 136010905Sandreas.sandberg@arm.com for (const TlbEntry *entry : freeList) 136110905Sandreas.sandberg@arm.com free_list.push_back(entry - tlb); 136210905Sandreas.sandberg@arm.com 136310905Sandreas.sandberg@arm.com SERIALIZE_CONTAINER(free_list); 13644000Ssaidi@eecs.umich.edu 13654990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13664990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13674990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13684990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13694990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13704990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13714990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13724990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 137312544Skhalique913@gmail.com SERIALIZE_SCALAR(sfar); 13745276Ssaidi@eecs.umich.edu 13755276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 137610905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 137710905Sandreas.sandberg@arm.com tlb[x].serialize(cp); 13785276Ssaidi@eecs.umich.edu } 13793804Ssaidi@eecs.umich.edu} 13803804Ssaidi@eecs.umich.edu 13813804Ssaidi@eecs.umich.eduvoid 138210905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 13833804Ssaidi@eecs.umich.edu{ 13844000Ssaidi@eecs.umich.edu int oldSize; 13854000Ssaidi@eecs.umich.edu 138610905Sandreas.sandberg@arm.com paramIn(cp, "size", oldSize); 13874000Ssaidi@eecs.umich.edu if (oldSize != size) 13884000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13894000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13904000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13914000Ssaidi@eecs.umich.edu 139210905Sandreas.sandberg@arm.com std::vector<int> free_list; 139310905Sandreas.sandberg@arm.com UNSERIALIZE_CONTAINER(free_list); 13944000Ssaidi@eecs.umich.edu freeList.clear(); 139510905Sandreas.sandberg@arm.com for (int idx : free_list) 139610905Sandreas.sandberg@arm.com freeList.push_back(&tlb[idx]); 13974000Ssaidi@eecs.umich.edu 13984990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 13994990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14004990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14014990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14024990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14034990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14044990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14054990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14065276Ssaidi@eecs.umich.edu 14075276Ssaidi@eecs.umich.edu lookupTable.clear(); 14085276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 140910905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 141010905Sandreas.sandberg@arm.com tlb[x].unserialize(cp); 14115276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14125276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14135276Ssaidi@eecs.umich.edu 14145276Ssaidi@eecs.umich.edu } 14154990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14163804Ssaidi@eecs.umich.edu} 14173804Ssaidi@eecs.umich.edu 14187811Ssteve.reinhardt@amd.com} // namespace SparcISA 14194088Sbinkertn@umich.edu 14206022Sgblack@eecs.umich.eduSparcISA::TLB * 14216022Sgblack@eecs.umich.eduSparcTLBParams::create() 14223804Ssaidi@eecs.umich.edu{ 14236022Sgblack@eecs.umich.edu return new SparcISA::TLB(this); 14243804Ssaidi@eecs.umich.edu} 1425