registers.hh revision 9046:a1104cc13db2
13534Sgblack@eecs.umich.edu/* 23534Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 33534Sgblack@eecs.umich.edu * All rights reserved. 43534Sgblack@eecs.umich.edu * 53534Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63534Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73534Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83534Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93534Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103534Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113534Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123534Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133534Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143534Sgblack@eecs.umich.edu * this software without specific prior written permission. 153534Sgblack@eecs.umich.edu * 163534Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173534Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183534Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193534Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203534Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213534Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223534Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233534Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243534Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253534Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263534Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273534Sgblack@eecs.umich.edu * 283534Sgblack@eecs.umich.edu * Authors: Gabe Black 293534Sgblack@eecs.umich.edu * Ali Saidi 303534Sgblack@eecs.umich.edu */ 313534Sgblack@eecs.umich.edu 324202Sbinkertn@umich.edu#ifndef __ARCH_SPARC_REGISTERS_HH__ 333534Sgblack@eecs.umich.edu#define __ARCH_SPARC_REGISTERS_HH__ 3410069Sandreas.hansson@arm.com 3510069Sandreas.hansson@arm.com#include "arch/sparc/generated/max_inst_regs.hh" 3610069Sandreas.hansson@arm.com#include "arch/sparc/miscregs.hh" 3711765Sandreas.sandberg@arm.com#include "arch/sparc/sparc_traits.hh" 3811765Sandreas.sandberg@arm.com#include "base/types.hh" 3910069Sandreas.hansson@arm.com 4011765Sandreas.sandberg@arm.comnamespace SparcISA 4110069Sandreas.hansson@arm.com{ 4213227Sgabeblack@google.com 4313227Sgabeblack@google.comusing SparcISAInst::MaxInstSrcRegs; 4413227Sgabeblack@google.comusing SparcISAInst::MaxInstDestRegs; 459850Sandreas.hansson@arm.comusing SparcISAInst::MaxMiscDestRegs; 467768SAli.Saidi@ARM.com 477768SAli.Saidi@ARM.comtypedef uint64_t IntReg; 488739Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 494486Sbinkertn@umich.edutypedef float FloatReg; 508739Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits; 518739Sgblack@eecs.umich.edutypedef union 528739Sgblack@eecs.umich.edu{ 5311012Sandreas.sandberg@arm.com IntReg intReg; 545192Ssaidi@eecs.umich.edu FloatReg fpreg; 558739Sgblack@eecs.umich.edu MiscReg ctrlreg; 568739Sgblack@eecs.umich.edu} AnyReg; 57 58typedef uint16_t RegIndex; 59 60// These enumerate all the registers for dependence tracking. 61enum DependenceTags { 62 FP_Base_DepTag = 32*3+9, 63 Ctrl_Base_DepTag = FP_Base_DepTag + 64, 64 Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs 65}; 66 67// semantically meaningful register indices 68const int ZeroReg = 0; // architecturally meaningful 69// the rest of these depend on the ABI 70const int ReturnAddressReg = 31; // post call, precall is 15 71const int ReturnValueReg = 8; // Post return, 24 is pre-return. 72const int StackPointerReg = 14; 73const int FramePointerReg = 30; 74 75// Some OS syscall use a second register (o1) to return a second value 76const int SyscallPseudoReturnReg = 9; 77 78const int NumIntArchRegs = 32; 79const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; 80 81const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 82 83} // namespace SparcISA 84 85#endif 86