registers.hh revision 13386:3447b3202bb1
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 611308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 711308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 811308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 911308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 1011308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 1111308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 1211308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 1311308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 1411308Santhony.gutierrez@amd.com * this software without specific prior written permission. 1511308Santhony.gutierrez@amd.com * 1611308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711308Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911308Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711308Santhony.gutierrez@amd.com * 2811308Santhony.gutierrez@amd.com * Authors: Gabe Black 2911308Santhony.gutierrez@amd.com * Ali Saidi 3011308Santhony.gutierrez@amd.com */ 3111308Santhony.gutierrez@amd.com 3211308Santhony.gutierrez@amd.com#ifndef __ARCH_SPARC_REGISTERS_HH__ 3311308Santhony.gutierrez@amd.com#define __ARCH_SPARC_REGISTERS_HH__ 3411308Santhony.gutierrez@amd.com 3511308Santhony.gutierrez@amd.com#include "arch/generic/vec_reg.hh" 3611308Santhony.gutierrez@amd.com#include "arch/sparc/generated/max_inst_regs.hh" 3711308Santhony.gutierrez@amd.com#include "arch/sparc/miscregs.hh" 3811308Santhony.gutierrez@amd.com#include "arch/sparc/sparc_traits.hh" 3911308Santhony.gutierrez@amd.com#include "base/types.hh" 4011308Santhony.gutierrez@amd.com 4111308Santhony.gutierrez@amd.comnamespace SparcISA 4211308Santhony.gutierrez@amd.com{ 4311308Santhony.gutierrez@amd.com 4411308Santhony.gutierrez@amd.comusing SparcISAInst::MaxInstSrcRegs; 4511308Santhony.gutierrez@amd.comusing SparcISAInst::MaxInstDestRegs; 4611308Santhony.gutierrez@amd.comusing SparcISAInst::MaxMiscDestRegs; 4711308Santhony.gutierrez@amd.com 4811308Santhony.gutierrez@amd.comtypedef uint64_t IntReg; 4911308Santhony.gutierrez@amd.comtypedef uint64_t MiscReg; 5011308Santhony.gutierrez@amd.comtypedef double FloatReg; 5111308Santhony.gutierrez@amd.comtypedef uint64_t FloatRegBits; 5211308Santhony.gutierrez@amd.com 5311308Santhony.gutierrez@amd.com// dummy typedef since we don't have CC regs 5411308Santhony.gutierrez@amd.comtypedef uint8_t CCReg; 5511308Santhony.gutierrez@amd.com 5611308Santhony.gutierrez@amd.com// dummy typedefs since we don't have vector regs 5711308Santhony.gutierrez@amd.comconstexpr unsigned NumVecElemPerVecReg = 2; 5811308Santhony.gutierrez@amd.comusing VecElem = uint32_t; 5911308Santhony.gutierrez@amd.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 6011308Santhony.gutierrez@amd.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 6111308Santhony.gutierrez@amd.comusing VecRegContainer = VecReg::Container; 6211308Santhony.gutierrez@amd.com// This has to be one to prevent warnings that are treated as errors 6311308Santhony.gutierrez@amd.comconstexpr unsigned NumVecRegs = 1; 6411308Santhony.gutierrez@amd.com 6511308Santhony.gutierrez@amd.com// semantically meaningful register indices 6611308Santhony.gutierrez@amd.comconst int ZeroReg = 0; // architecturally meaningful 6711308Santhony.gutierrez@amd.com// the rest of these depend on the ABI 6811308Santhony.gutierrez@amd.comconst int ReturnAddressReg = 31; // post call, precall is 15 6911308Santhony.gutierrez@amd.comconst int ReturnValueReg = 8; // Post return, 24 is pre-return. 7011308Santhony.gutierrez@amd.comconst int StackPointerReg = 14; 7111308Santhony.gutierrez@amd.comconst int FramePointerReg = 30; 7211308Santhony.gutierrez@amd.com 7311308Santhony.gutierrez@amd.com// Some OS syscall use a second register (o1) to return a second value 7411308Santhony.gutierrez@amd.comconst int SyscallPseudoReturnReg = 9; 7511308Santhony.gutierrez@amd.com 7611308Santhony.gutierrez@amd.comconst int NumIntArchRegs = 32; 7711308Santhony.gutierrez@amd.comconst int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; 7811308Santhony.gutierrez@amd.comconst int NumCCRegs = 0; 7911308Santhony.gutierrez@amd.com 8011308Santhony.gutierrez@amd.comconst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 8111308Santhony.gutierrez@amd.com 8211308Santhony.gutierrez@amd.com} // namespace SparcISA 8311308Santhony.gutierrez@amd.com 8411308Santhony.gutierrez@amd.com#endif 8511308Santhony.gutierrez@amd.com