util.isa revision 7741
13931Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 23388Sgblack@eecs.umich.edu// All rights reserved. 33388Sgblack@eecs.umich.edu// 43388Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 53388Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 63388Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 73388Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 83388Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 93388Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 103388Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 113388Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 123388Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 133388Sgblack@eecs.umich.edu// this software without specific prior written permission. 143388Sgblack@eecs.umich.edu// 153388Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163388Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173388Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183388Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193388Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203388Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213388Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223388Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233388Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243388Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253388Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263388Sgblack@eecs.umich.edu// 273388Sgblack@eecs.umich.edu// Authors: Ali Saidi 283388Sgblack@eecs.umich.edu// Gabe Black 293388Sgblack@eecs.umich.edu// Steve Reinhardt 303388Sgblack@eecs.umich.edu 313388Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 323388Sgblack@eecs.umich.edu// 333388Sgblack@eecs.umich.edu// Mem utility templates and functions 343388Sgblack@eecs.umich.edu// 353388Sgblack@eecs.umich.edu 363441Sgblack@eecs.umich.eduoutput header {{ 373441Sgblack@eecs.umich.edu /** 383441Sgblack@eecs.umich.edu * Base class for memory operations. 393441Sgblack@eecs.umich.edu */ 403441Sgblack@eecs.umich.edu class Mem : public SparcStaticInst 413441Sgblack@eecs.umich.edu { 423441Sgblack@eecs.umich.edu protected: 433441Sgblack@eecs.umich.edu 443441Sgblack@eecs.umich.edu // Constructor 453441Sgblack@eecs.umich.edu Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 463441Sgblack@eecs.umich.edu SparcStaticInst(mnem, _machInst, __opClass) 473441Sgblack@eecs.umich.edu { 483441Sgblack@eecs.umich.edu } 493441Sgblack@eecs.umich.edu 503441Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, 513441Sgblack@eecs.umich.edu const SymbolTable *symtab) const; 523441Sgblack@eecs.umich.edu }; 533441Sgblack@eecs.umich.edu 543441Sgblack@eecs.umich.edu /** 553441Sgblack@eecs.umich.edu * Class for memory operations which use an immediate offset. 563441Sgblack@eecs.umich.edu */ 573441Sgblack@eecs.umich.edu class MemImm : public Mem 583441Sgblack@eecs.umich.edu { 593441Sgblack@eecs.umich.edu protected: 603441Sgblack@eecs.umich.edu 613441Sgblack@eecs.umich.edu // Constructor 623441Sgblack@eecs.umich.edu MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 633441Sgblack@eecs.umich.edu Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 643441Sgblack@eecs.umich.edu {} 653441Sgblack@eecs.umich.edu 663441Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, 673441Sgblack@eecs.umich.edu const SymbolTable *symtab) const; 683441Sgblack@eecs.umich.edu 693441Sgblack@eecs.umich.edu const int32_t imm; 703441Sgblack@eecs.umich.edu }; 713441Sgblack@eecs.umich.edu}}; 723441Sgblack@eecs.umich.edu 733441Sgblack@eecs.umich.eduoutput decoder {{ 743441Sgblack@eecs.umich.edu std::string Mem::generateDisassembly(Addr pc, 753441Sgblack@eecs.umich.edu const SymbolTable *symtab) const 763441Sgblack@eecs.umich.edu { 773441Sgblack@eecs.umich.edu std::stringstream response; 783441Sgblack@eecs.umich.edu bool load = flags[IsLoad]; 793627Sgblack@eecs.umich.edu bool store = flags[IsStore]; 803441Sgblack@eecs.umich.edu 813441Sgblack@eecs.umich.edu printMnemonic(response, mnemonic); 827741Sgblack@eecs.umich.edu if (store) { 833627Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[0]); 843441Sgblack@eecs.umich.edu ccprintf(response, ", "); 853441Sgblack@eecs.umich.edu } 863627Sgblack@eecs.umich.edu ccprintf(response, "["); 877741Sgblack@eecs.umich.edu if (_srcRegIdx[!store ? 0 : 1] != 0) { 883627Sgblack@eecs.umich.edu printSrcReg(response, !store ? 0 : 1); 893627Sgblack@eecs.umich.edu ccprintf(response, " + "); 903627Sgblack@eecs.umich.edu } 913627Sgblack@eecs.umich.edu printSrcReg(response, !store ? 1 : 2); 923627Sgblack@eecs.umich.edu ccprintf(response, "]"); 937741Sgblack@eecs.umich.edu if (load) { 943441Sgblack@eecs.umich.edu ccprintf(response, ", "); 953627Sgblack@eecs.umich.edu printReg(response, _destRegIdx[0]); 963441Sgblack@eecs.umich.edu } 973441Sgblack@eecs.umich.edu 983441Sgblack@eecs.umich.edu return response.str(); 993441Sgblack@eecs.umich.edu } 1003441Sgblack@eecs.umich.edu 1013441Sgblack@eecs.umich.edu std::string MemImm::generateDisassembly(Addr pc, 1023441Sgblack@eecs.umich.edu const SymbolTable *symtab) const 1033441Sgblack@eecs.umich.edu { 1043441Sgblack@eecs.umich.edu std::stringstream response; 1053441Sgblack@eecs.umich.edu bool load = flags[IsLoad]; 1063441Sgblack@eecs.umich.edu bool save = flags[IsStore]; 1073441Sgblack@eecs.umich.edu 1083441Sgblack@eecs.umich.edu printMnemonic(response, mnemonic); 1097741Sgblack@eecs.umich.edu if (save) { 1103627Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[0]); 1113441Sgblack@eecs.umich.edu ccprintf(response, ", "); 1123441Sgblack@eecs.umich.edu } 1133627Sgblack@eecs.umich.edu ccprintf(response, "["); 1147741Sgblack@eecs.umich.edu if (_srcRegIdx[!save ? 0 : 1] != 0) { 1153627Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[!save ? 0 : 1]); 1163627Sgblack@eecs.umich.edu ccprintf(response, " + "); 1173627Sgblack@eecs.umich.edu } 1187741Sgblack@eecs.umich.edu if (imm >= 0) 1193627Sgblack@eecs.umich.edu ccprintf(response, "0x%x]", imm); 1203441Sgblack@eecs.umich.edu else 1213627Sgblack@eecs.umich.edu ccprintf(response, "-0x%x]", -imm); 1227741Sgblack@eecs.umich.edu if (load) { 1233441Sgblack@eecs.umich.edu ccprintf(response, ", "); 1243627Sgblack@eecs.umich.edu printReg(response, _destRegIdx[0]); 1253441Sgblack@eecs.umich.edu } 1263441Sgblack@eecs.umich.edu 1273441Sgblack@eecs.umich.edu return response.str(); 1283441Sgblack@eecs.umich.edu } 1293441Sgblack@eecs.umich.edu}}; 1303441Sgblack@eecs.umich.edu 1317741Sgblack@eecs.umich.edu// This template provides the execute functions for a load 1323388Sgblack@eecs.umich.edudef template LoadExecute {{ 1333388Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1343388Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1353388Sgblack@eecs.umich.edu { 1363388Sgblack@eecs.umich.edu Fault fault = NoFault; 1373388Sgblack@eecs.umich.edu Addr EA; 1383931Ssaidi@eecs.umich.edu %(fp_enable_check)s; 1393388Sgblack@eecs.umich.edu %(op_decl)s; 1403388Sgblack@eecs.umich.edu %(op_rd)s; 1413388Sgblack@eecs.umich.edu %(ea_code)s; 1423766Sgblack@eecs.umich.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 1433391Sgblack@eecs.umich.edu %(fault_check)s; 1447741Sgblack@eecs.umich.edu if (fault == NoFault) { 1454648Sgblack@eecs.umich.edu %(EA_trunc)s 1464040Ssaidi@eecs.umich.edu fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 1473391Sgblack@eecs.umich.edu } 1487741Sgblack@eecs.umich.edu if (fault == NoFault) { 1493391Sgblack@eecs.umich.edu %(code)s; 1503391Sgblack@eecs.umich.edu } 1517741Sgblack@eecs.umich.edu if (fault == NoFault) { 1527741Sgblack@eecs.umich.edu // Write the resulting state to the execution context 1537741Sgblack@eecs.umich.edu %(op_wb)s; 1543388Sgblack@eecs.umich.edu } 1553388Sgblack@eecs.umich.edu 1563388Sgblack@eecs.umich.edu return fault; 1573388Sgblack@eecs.umich.edu } 1583792Sgblack@eecs.umich.edu}}; 1593388Sgblack@eecs.umich.edu 1603792Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 1613388Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 1623388Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1633388Sgblack@eecs.umich.edu { 1643388Sgblack@eecs.umich.edu Fault fault = NoFault; 1653388Sgblack@eecs.umich.edu Addr EA; 1663931Ssaidi@eecs.umich.edu %(fp_enable_check)s; 1673792Sgblack@eecs.umich.edu %(op_decl)s; 1683792Sgblack@eecs.umich.edu %(op_rd)s; 1693388Sgblack@eecs.umich.edu %(ea_code)s; 1703766Sgblack@eecs.umich.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 1713391Sgblack@eecs.umich.edu %(fault_check)s; 1727741Sgblack@eecs.umich.edu if (fault == NoFault) { 1734648Sgblack@eecs.umich.edu %(EA_trunc)s 1744040Ssaidi@eecs.umich.edu fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 1753391Sgblack@eecs.umich.edu } 1763388Sgblack@eecs.umich.edu return fault; 1773388Sgblack@eecs.umich.edu } 1783792Sgblack@eecs.umich.edu}}; 1793388Sgblack@eecs.umich.edu 1803792Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 1813388Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 1823388Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1833388Sgblack@eecs.umich.edu { 1843388Sgblack@eecs.umich.edu Fault fault = NoFault; 1853792Sgblack@eecs.umich.edu %(op_decl)s; 1863792Sgblack@eecs.umich.edu %(op_rd)s; 1873388Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 1883388Sgblack@eecs.umich.edu %(code)s; 1897741Sgblack@eecs.umich.edu if (fault == NoFault) { 1903792Sgblack@eecs.umich.edu %(op_wb)s; 1913388Sgblack@eecs.umich.edu } 1923388Sgblack@eecs.umich.edu return fault; 1933388Sgblack@eecs.umich.edu } 1943388Sgblack@eecs.umich.edu}}; 1953388Sgblack@eecs.umich.edu 1967741Sgblack@eecs.umich.edu// This template provides the execute functions for a store 1973388Sgblack@eecs.umich.edudef template StoreExecute {{ 1983388Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1993388Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2003388Sgblack@eecs.umich.edu { 2013388Sgblack@eecs.umich.edu Fault fault = NoFault; 2027741Sgblack@eecs.umich.edu // This is to support the conditional store in cas instructions. 2037741Sgblack@eecs.umich.edu // It should be optomized out in all the others 2043439Sgblack@eecs.umich.edu bool storeCond = true; 2053388Sgblack@eecs.umich.edu Addr EA; 2063931Ssaidi@eecs.umich.edu %(fp_enable_check)s; 2073388Sgblack@eecs.umich.edu %(op_decl)s; 2083388Sgblack@eecs.umich.edu %(op_rd)s; 2093388Sgblack@eecs.umich.edu %(ea_code)s; 2103766Sgblack@eecs.umich.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 2113391Sgblack@eecs.umich.edu %(fault_check)s; 2127741Sgblack@eecs.umich.edu if (fault == NoFault) { 2133391Sgblack@eecs.umich.edu %(code)s; 2143391Sgblack@eecs.umich.edu } 2157741Sgblack@eecs.umich.edu if (storeCond && fault == NoFault) { 2164648Sgblack@eecs.umich.edu %(EA_trunc)s 2174224Sgblack@eecs.umich.edu fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 2183810Sgblack@eecs.umich.edu EA, %(asi_val)s, 0); 2193388Sgblack@eecs.umich.edu } 2207741Sgblack@eecs.umich.edu if (fault == NoFault) { 2217741Sgblack@eecs.umich.edu // Write the resulting state to the execution context 2227741Sgblack@eecs.umich.edu %(op_wb)s; 2233388Sgblack@eecs.umich.edu } 2243388Sgblack@eecs.umich.edu 2253388Sgblack@eecs.umich.edu return fault; 2263388Sgblack@eecs.umich.edu } 2273792Sgblack@eecs.umich.edu}}; 2283388Sgblack@eecs.umich.edu 2293792Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 2303388Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 2313388Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 2323388Sgblack@eecs.umich.edu { 2333388Sgblack@eecs.umich.edu Fault fault = NoFault; 2343439Sgblack@eecs.umich.edu bool storeCond = true; 2353388Sgblack@eecs.umich.edu Addr EA; 2363931Ssaidi@eecs.umich.edu %(fp_enable_check)s; 2373388Sgblack@eecs.umich.edu %(op_decl)s; 2384040Ssaidi@eecs.umich.edu 2393388Sgblack@eecs.umich.edu %(op_rd)s; 2403388Sgblack@eecs.umich.edu %(ea_code)s; 2413766Sgblack@eecs.umich.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 2423391Sgblack@eecs.umich.edu %(fault_check)s; 2437741Sgblack@eecs.umich.edu if (fault == NoFault) { 2443391Sgblack@eecs.umich.edu %(code)s; 2453391Sgblack@eecs.umich.edu } 2467741Sgblack@eecs.umich.edu if (storeCond && fault == NoFault) { 2474648Sgblack@eecs.umich.edu %(EA_trunc)s 2484224Sgblack@eecs.umich.edu fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 2493810Sgblack@eecs.umich.edu EA, %(asi_val)s, 0); 2503388Sgblack@eecs.umich.edu } 2513388Sgblack@eecs.umich.edu return fault; 2523388Sgblack@eecs.umich.edu } 2533792Sgblack@eecs.umich.edu}}; 2543388Sgblack@eecs.umich.edu 2553792Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 2563388Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 2573388Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 2583388Sgblack@eecs.umich.edu { 2593388Sgblack@eecs.umich.edu return NoFault; 2603388Sgblack@eecs.umich.edu } 2613388Sgblack@eecs.umich.edu}}; 2623388Sgblack@eecs.umich.edu 2637741Sgblack@eecs.umich.edu// This delcares the initiateAcc function in memory operations 2643388Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 2653388Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 2663388Sgblack@eecs.umich.edu}}; 2673388Sgblack@eecs.umich.edu 2687741Sgblack@eecs.umich.edu// This declares the completeAcc function in memory operations 2693388Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 2703388Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 2713388Sgblack@eecs.umich.edu}}; 2723388Sgblack@eecs.umich.edu 2737741Sgblack@eecs.umich.edu// Here are some code snippets which check for various fault conditions 2743391Sgblack@eecs.umich.edulet {{ 2753792Sgblack@eecs.umich.edu LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] 2763792Sgblack@eecs.umich.edu StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] 2774040Ssaidi@eecs.umich.edu 2783391Sgblack@eecs.umich.edu # The LSB can be zero, since it's really the MSB in doubles and quads 2793391Sgblack@eecs.umich.edu # and we're dealing with doubles 2803391Sgblack@eecs.umich.edu BlockAlignmentFaultCheck = ''' 2817741Sgblack@eecs.umich.edu if (RD & 0xe) 2823391Sgblack@eecs.umich.edu fault = new IllegalInstruction; 2837741Sgblack@eecs.umich.edu else if (EA & 0x3f) 2843391Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 2853391Sgblack@eecs.umich.edu ''' 2863835Sgblack@eecs.umich.edu TwinAlignmentFaultCheck = ''' 2877741Sgblack@eecs.umich.edu if (RD & 0x1) 2883835Sgblack@eecs.umich.edu fault = new IllegalInstruction; 2897741Sgblack@eecs.umich.edu else if (EA & 0xf) 2903835Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 2913835Sgblack@eecs.umich.edu ''' 2923391Sgblack@eecs.umich.edu # XXX Need to take care of pstate.hpriv as well. The lower ASIs 2933391Sgblack@eecs.umich.edu # are split into ones that are available in priv and hpriv, and 2943391Sgblack@eecs.umich.edu # those that are only available in hpriv 2953391Sgblack@eecs.umich.edu AlternateASIPrivFaultCheck = ''' 2965570Snate@binkert.org if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) && 2977741Sgblack@eecs.umich.edu !asiIsUnPriv((ASI)EXT_ASI)) || 2987741Sgblack@eecs.umich.edu (!bits(Hpstate,2,2) && asiIsHPriv((ASI)EXT_ASI))) 2995570Snate@binkert.org fault = new PrivilegedAction; 3007741Sgblack@eecs.umich.edu else if (asiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 3013391Sgblack@eecs.umich.edu fault = new PrivilegedAction; 3023391Sgblack@eecs.umich.edu ''' 3033391Sgblack@eecs.umich.edu 3044648Sgblack@eecs.umich.edu TruncateEA = ''' 3054648Sgblack@eecs.umich.edu#if !FULL_SYSTEM 3064648Sgblack@eecs.umich.edu EA = Pstate<3:> ? EA<31:0> : EA; 3074648Sgblack@eecs.umich.edu#endif 3084648Sgblack@eecs.umich.edu ''' 3093391Sgblack@eecs.umich.edu}}; 3103391Sgblack@eecs.umich.edu 3117741Sgblack@eecs.umich.edu// A simple function to generate the name of the macro op of a certain 3127741Sgblack@eecs.umich.edu// instruction at a certain micropc 3133391Sgblack@eecs.umich.edulet {{ 3143391Sgblack@eecs.umich.edu def makeMicroName(name, microPc): 3153616Sgblack@eecs.umich.edu return name + "::" + name + "_" + str(microPc) 3163391Sgblack@eecs.umich.edu}}; 3173391Sgblack@eecs.umich.edu 3187741Sgblack@eecs.umich.edu// This function properly generates the execute functions for one of the 3197741Sgblack@eecs.umich.edu// templates above. This is needed because in one case, ea computation, 3207741Sgblack@eecs.umich.edu// fault checks and the actual code all occur in the same function, 3217741Sgblack@eecs.umich.edu// and in the other they're distributed across two. Also note that for 3227741Sgblack@eecs.umich.edu// execute functions, the name of the base class doesn't matter. 3233388Sgblack@eecs.umich.edulet {{ 3243949Sgblack@eecs.umich.edu def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): 3253810Sgblack@eecs.umich.edu microParam["asi_val"] = asi; 3263792Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, '', microParam, opt_flags) 3273792Sgblack@eecs.umich.edu (execf, initf, compf) = execute 3283792Sgblack@eecs.umich.edu return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) 3293439Sgblack@eecs.umich.edu 3303439Sgblack@eecs.umich.edu 3314040Ssaidi@eecs.umich.edu def doDualSplitExecute(code, postacc_code, eaRegCode, eaImmCode, execute, 3323810Sgblack@eecs.umich.edu faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 3333388Sgblack@eecs.umich.edu executeCode = '' 3343388Sgblack@eecs.umich.edu for (eaCode, name, Name) in ( 3353388Sgblack@eecs.umich.edu (eaRegCode, nameReg, NameReg), 3363388Sgblack@eecs.umich.edu (eaImmCode, nameImm, NameImm)): 3374040Ssaidi@eecs.umich.edu microParams = {"code": code, "postacc_code" : postacc_code, 3384648Sgblack@eecs.umich.edu "ea_code": eaCode, "fault_check": faultCode, 3394648Sgblack@eecs.umich.edu "EA_trunc" : TruncateEA} 3403792Sgblack@eecs.umich.edu executeCode += doSplitExecute(execute, name, Name, 3413810Sgblack@eecs.umich.edu asi, opt_flags, microParams) 3423388Sgblack@eecs.umich.edu return executeCode 3433388Sgblack@eecs.umich.edu}}; 344