decoder.isa revision 7784
13900Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 407741Sgblack@eecs.umich.edu // Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 447741Sgblack@eecs.umich.edu // bpcc 453056Sgblack@eecs.umich.edu 0x1: decode COND2 462469SN/A { 477741Sgblack@eecs.umich.edu // Branch Always 485091Sgblack@eecs.umich.edu 0x8: bpa(19, annul_code={{ 497720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 507720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 517720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 527720Sgblack@eecs.umich.edu PCS = pc; 535091Sgblack@eecs.umich.edu }}); 547741Sgblack@eecs.umich.edu // Branch Never 555091Sgblack@eecs.umich.edu 0x0: bpn(19, {{;}}, 565091Sgblack@eecs.umich.edu annul_code={{ 577720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 587720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 597720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 607720Sgblack@eecs.umich.edu PCS = pc; 615091Sgblack@eecs.umich.edu }}); 623056Sgblack@eecs.umich.edu default: decode BPCC 633056Sgblack@eecs.umich.edu { 645091Sgblack@eecs.umich.edu 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 655091Sgblack@eecs.umich.edu 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 663056Sgblack@eecs.umich.edu } 672482SN/A } 687741Sgblack@eecs.umich.edu // bicc 693598Sgblack@eecs.umich.edu 0x2: decode COND2 703598Sgblack@eecs.umich.edu { 717741Sgblack@eecs.umich.edu // Branch Always 725091Sgblack@eecs.umich.edu 0x8: ba(22, annul_code={{ 737720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 747720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 757720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 767720Sgblack@eecs.umich.edu PCS = pc; 775091Sgblack@eecs.umich.edu }}); 787741Sgblack@eecs.umich.edu // Branch Never 795091Sgblack@eecs.umich.edu 0x0: bn(22, {{;}}, 805091Sgblack@eecs.umich.edu annul_code={{ 817720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 827720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 837720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 847720Sgblack@eecs.umich.edu PCS = pc; 855091Sgblack@eecs.umich.edu }}); 865091Sgblack@eecs.umich.edu default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 873598Sgblack@eecs.umich.edu } 882516SN/A } 892516SN/A 0x3: decode RCOND2 902516SN/A { 912516SN/A format BranchSplit 922482SN/A { 935091Sgblack@eecs.umich.edu 0x1: bpreq(test={{Rs1.sdw == 0}}); 945091Sgblack@eecs.umich.edu 0x2: bprle(test={{Rs1.sdw <= 0}}); 955091Sgblack@eecs.umich.edu 0x3: bprl(test={{Rs1.sdw < 0}}); 965091Sgblack@eecs.umich.edu 0x5: bprne(test={{Rs1.sdw != 0}}); 975091Sgblack@eecs.umich.edu 0x6: bprg(test={{Rs1.sdw > 0}}); 985091Sgblack@eecs.umich.edu 0x7: bprge(test={{Rs1.sdw >= 0}}); 992469SN/A } 1002482SN/A } 1017741Sgblack@eecs.umich.edu // SETHI (or NOP if rd == 0 and imm == 0) 1023042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 1037741Sgblack@eecs.umich.edu // fbpfcc 1044004Sgblack@eecs.umich.edu 0x5: decode COND2 { 1054004Sgblack@eecs.umich.edu format BranchN { 1067741Sgblack@eecs.umich.edu // Branch Always 1075091Sgblack@eecs.umich.edu 0x8: fbpa(22, annul_code={{ 1087720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1097720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 1107720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 1117720Sgblack@eecs.umich.edu PCS = pc; 1125091Sgblack@eecs.umich.edu }}); 1137741Sgblack@eecs.umich.edu // Branch Never 1145091Sgblack@eecs.umich.edu 0x0: fbpn(22, {{;}}, 1155091Sgblack@eecs.umich.edu annul_code={{ 1167720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1177720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 1187720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 1197720Sgblack@eecs.umich.edu PCS = pc; 1205091Sgblack@eecs.umich.edu }}); 1214004Sgblack@eecs.umich.edu default: decode BPCC { 1225091Sgblack@eecs.umich.edu 0x0: fbpfcc0(19, test= 1235091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1245091Sgblack@eecs.umich.edu 0x1: fbpfcc1(19, test= 1255091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<33:32>, COND2)}}); 1265091Sgblack@eecs.umich.edu 0x2: fbpfcc2(19, test= 1275091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<35:34>, COND2)}}); 1285091Sgblack@eecs.umich.edu 0x3: fbpfcc3(19, test= 1295091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<37:36>, COND2)}}); 1304004Sgblack@eecs.umich.edu } 1314004Sgblack@eecs.umich.edu } 1324004Sgblack@eecs.umich.edu } 1337741Sgblack@eecs.umich.edu // fbfcc 1344004Sgblack@eecs.umich.edu 0x6: decode COND2 { 1354004Sgblack@eecs.umich.edu format BranchN { 1367741Sgblack@eecs.umich.edu // Branch Always 1375091Sgblack@eecs.umich.edu 0x8: fba(22, annul_code={{ 1387720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1397720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 1407720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 1417720Sgblack@eecs.umich.edu PCS = pc; 1425091Sgblack@eecs.umich.edu }}); 1437741Sgblack@eecs.umich.edu // Branch Never 1445091Sgblack@eecs.umich.edu 0x0: fbn(22, {{;}}, 1455091Sgblack@eecs.umich.edu annul_code={{ 1467720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1477720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 1487720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 1497720Sgblack@eecs.umich.edu PCS = pc; 1505091Sgblack@eecs.umich.edu }}); 1515091Sgblack@eecs.umich.edu default: fbfcc(22, test= 1525091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1534004Sgblack@eecs.umich.edu } 1544004Sgblack@eecs.umich.edu } 1552469SN/A } 1562944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1577720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1583928Ssaidi@eecs.umich.edu if (Pstate<3:>) 1597720Sgblack@eecs.umich.edu R15 = (pc.pc())<31:0>; 1603928Ssaidi@eecs.umich.edu else 1617720Sgblack@eecs.umich.edu R15 = pc.pc(); 1627720Sgblack@eecs.umich.edu pc.nnpc(R15 + disp); 1637720Sgblack@eecs.umich.edu PCS = pc; 1642469SN/A }}); 1652469SN/A 0x2: decode OP3 { 1662482SN/A format IntOp { 1672482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1682974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1692974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1702974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1712526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1722974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1732974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1742974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1752646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1762974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1772469SN/A 0x0A: umul({{ 1782516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1792646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1802482SN/A }}); 1812469SN/A 0x0B: smul({{ 1823931Ssaidi@eecs.umich.edu Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 1833900Ssaidi@eecs.umich.edu Y = Rd.sdw<63:32>; 1842482SN/A }}); 1852954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1862469SN/A 0x0D: udivx({{ 1877741Sgblack@eecs.umich.edu if (Rs2_or_imm13 == 0) 1887741Sgblack@eecs.umich.edu fault = new DivisionByZero; 1897741Sgblack@eecs.umich.edu else 1907741Sgblack@eecs.umich.edu Rd.udw = Rs1.udw / Rs2_or_imm13; 1912482SN/A }}); 1922469SN/A 0x0E: udiv({{ 1937741Sgblack@eecs.umich.edu if (Rs2_or_imm13 == 0) { 1947741Sgblack@eecs.umich.edu fault = new DivisionByZero; 1957741Sgblack@eecs.umich.edu } else { 1962646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1977741Sgblack@eecs.umich.edu if (Rd.udw >> 32 != 0) 1982482SN/A Rd.udw = 0xFFFFFFFF; 1992482SN/A } 2002482SN/A }}); 2012482SN/A 0x0F: sdiv({{ 2027741Sgblack@eecs.umich.edu if (Rs2_or_imm13.sdw == 0) { 2032469SN/A fault = new DivisionByZero; 2047741Sgblack@eecs.umich.edu } else { 2057741Sgblack@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | 2067741Sgblack@eecs.umich.edu Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 2077741Sgblack@eecs.umich.edu if ((int64_t)Rd.udw >= 2087741Sgblack@eecs.umich.edu std::numeric_limits<int32_t>::max()) { 2092482SN/A Rd.udw = 0x7FFFFFFF; 2107741Sgblack@eecs.umich.edu } else if ((int64_t)Rd.udw <= 2117741Sgblack@eecs.umich.edu std::numeric_limits<int32_t>::min()) { 2123929Ssaidi@eecs.umich.edu Rd.udw = ULL(0xFFFFFFFF80000000); 2137741Sgblack@eecs.umich.edu } 2142482SN/A } 2152526SN/A }}); 2162469SN/A } 2172482SN/A format IntOpCc { 2182469SN/A 0x10: addcc({{ 2195093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2205093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 2215093Sgblack@eecs.umich.edu }}); 2222482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 2232482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2242482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2252469SN/A 0x14: subcc({{ 2265093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2275093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2285093Sgblack@eecs.umich.edu }}, sub=True); 2292482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2302482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2312482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2322469SN/A 0x18: addccc({{ 2335093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2345093Sgblack@eecs.umich.edu Rd = res = op1 + op2 + Ccr<0:>; 2355093Sgblack@eecs.umich.edu }}); 2363765Sgblack@eecs.umich.edu 0x1A: IntOpCcRes::umulcc({{ 2372615SN/A uint64_t resTemp; 2382615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2393765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2403765Sgblack@eecs.umich.edu 0x1B: IntOpCcRes::smulcc({{ 2412615SN/A int64_t resTemp; 2423931Ssaidi@eecs.umich.edu Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 2433765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2442469SN/A 0x1C: subccc({{ 2455093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2465093Sgblack@eecs.umich.edu Rd = res = op1 - op2 - Ccr<0:>; 2475093Sgblack@eecs.umich.edu }}, sub=True); 2483765Sgblack@eecs.umich.edu 0x1D: IntOpCcRes::udivxcc({{ 2497741Sgblack@eecs.umich.edu if (Rs2_or_imm13.udw == 0) 2507741Sgblack@eecs.umich.edu fault = new DivisionByZero; 2517741Sgblack@eecs.umich.edu else 2527741Sgblack@eecs.umich.edu Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 2535093Sgblack@eecs.umich.edu 0x1E: IntOpCcRes::udivcc({{ 2546639Svince@csl.cornell.edu uint64_t resTemp; 2556639Svince@csl.cornell.edu uint32_t val2 = Rs2_or_imm13.udw; 2565093Sgblack@eecs.umich.edu int32_t overflow = 0; 2577741Sgblack@eecs.umich.edu if (val2 == 0) { 2587741Sgblack@eecs.umich.edu fault = new DivisionByZero; 2597741Sgblack@eecs.umich.edu } else { 2605093Sgblack@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2615093Sgblack@eecs.umich.edu overflow = (resTemp<63:32> != 0); 2627741Sgblack@eecs.umich.edu if (overflow) 2637741Sgblack@eecs.umich.edu Rd = resTemp = 0xFFFFFFFF; 2647741Sgblack@eecs.umich.edu else 2657741Sgblack@eecs.umich.edu Rd = resTemp; 2665093Sgblack@eecs.umich.edu } 2675093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2685093Sgblack@eecs.umich.edu 0x1F: IntOpCcRes::sdivcc({{ 2695093Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2705093Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 2717741Sgblack@eecs.umich.edu if (val2 == 0) { 2727741Sgblack@eecs.umich.edu fault = new DivisionByZero; 2737741Sgblack@eecs.umich.edu } else { 2745093Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2755093Sgblack@eecs.umich.edu overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 2765093Sgblack@eecs.umich.edu underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 2777741Sgblack@eecs.umich.edu if (overflow) 2787741Sgblack@eecs.umich.edu Rd = 0x7FFFFFFF; 2797741Sgblack@eecs.umich.edu else if (underflow) 2807741Sgblack@eecs.umich.edu Rd = ULL(0xFFFFFFFF80000000); 2815093Sgblack@eecs.umich.edu } 2825093Sgblack@eecs.umich.edu }}, iv={{overflow || underflow}}); 2832469SN/A 0x20: taddcc({{ 2845093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2855093Sgblack@eecs.umich.edu Rd = res = Rs1 + op2; 2865093Sgblack@eecs.umich.edu }}, iv={{ 2875093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2885093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2) 2895093Sgblack@eecs.umich.edu }}); 2902469SN/A 0x21: tsubcc({{ 2915093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2925093Sgblack@eecs.umich.edu Rd = res = Rs1 - op2; 2935093Sgblack@eecs.umich.edu }}, iv={{ 2945093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2955093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2) 2965093Sgblack@eecs.umich.edu }}, sub=True); 2972469SN/A 0x22: taddcctv({{ 2985093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2995093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 3005093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 3015093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2); 3027741Sgblack@eecs.umich.edu if (overflow) 3037741Sgblack@eecs.umich.edu fault = new TagOverflow; 3045093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 3052469SN/A 0x23: tsubcctv({{ 3065093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 3075093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 3085093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 3095093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2); 3107741Sgblack@eecs.umich.edu if (overflow) 3117741Sgblack@eecs.umich.edu fault = new TagOverflow; 3125093Sgblack@eecs.umich.edu }}, iv={{overflow}}, sub=True); 3132469SN/A 0x24: mulscc({{ 3145093Sgblack@eecs.umich.edu int32_t savedLSB = Rs1<0:>; 3154237Sgblack@eecs.umich.edu 3167741Sgblack@eecs.umich.edu // Step 1 3175093Sgblack@eecs.umich.edu int64_t multiplicand = Rs2_or_imm13; 3187741Sgblack@eecs.umich.edu // Step 2 3195093Sgblack@eecs.umich.edu int32_t partialP = Rs1<31:1> | 3205093Sgblack@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 31); 3217741Sgblack@eecs.umich.edu // Step 3 3225093Sgblack@eecs.umich.edu int32_t added = Y<0:> ? multiplicand : 0; 3235093Sgblack@eecs.umich.edu int64_t res, op1 = partialP, op2 = added; 3245093Sgblack@eecs.umich.edu Rd = res = partialP + added; 3257741Sgblack@eecs.umich.edu // Steps 4 & 5 3265093Sgblack@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31); 3275093Sgblack@eecs.umich.edu }}); 3282526SN/A } 3292526SN/A format IntOp 3302526SN/A { 3312526SN/A 0x25: decode X { 3322526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3332526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3342469SN/A } 3352526SN/A 0x26: decode X { 3362526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3372526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3382526SN/A } 3392526SN/A 0x27: decode X { 3402526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3412526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3422526SN/A } 3432954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3443929Ssaidi@eecs.umich.edu 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 3457741Sgblack@eecs.umich.edu // 1 should cause an illegal instruction exception 3463587Sgblack@eecs.umich.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 3473587Sgblack@eecs.umich.edu 0x03: NoPriv::rdasi({{Rd = Asi;}}); 3485094Sgblack@eecs.umich.edu 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 3493587Sgblack@eecs.umich.edu 0x05: NoPriv::rdpc({{ 3507720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 3517741Sgblack@eecs.umich.edu if (Pstate<3:>) 3527720Sgblack@eecs.umich.edu Rd = (pc.pc())<31:0>; 3533587Sgblack@eecs.umich.edu else 3547720Sgblack@eecs.umich.edu Rd = pc.pc(); 3557720Sgblack@eecs.umich.edu }}); 3563587Sgblack@eecs.umich.edu 0x06: NoPriv::rdfprs({{ 3577741Sgblack@eecs.umich.edu // Wait for all fpops to finish. 3583587Sgblack@eecs.umich.edu Rd = Fprs; 3593587Sgblack@eecs.umich.edu }}); 3607741Sgblack@eecs.umich.edu // 7-14 should cause an illegal instruction exception 3613587Sgblack@eecs.umich.edu 0x0F: decode I { 3624040Ssaidi@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 3634040Ssaidi@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 3642954Sgblack@eecs.umich.edu } 3653587Sgblack@eecs.umich.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 3665094Sgblack@eecs.umich.edu 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 3677741Sgblack@eecs.umich.edu // 0x12 should cause an illegal instruction exception 3683587Sgblack@eecs.umich.edu 0x13: NoPriv::rdgsr({{ 3694010Ssaidi@eecs.umich.edu fault = checkFpEnableFault(xc); 3704010Ssaidi@eecs.umich.edu if (fault) 3714010Ssaidi@eecs.umich.edu return fault; 3724010Ssaidi@eecs.umich.edu Rd = Gsr; 3732954Sgblack@eecs.umich.edu }}); 3747741Sgblack@eecs.umich.edu // 0x14-0x15 should cause an illegal instruction exception 3753587Sgblack@eecs.umich.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 3763823Ssaidi@eecs.umich.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 3775094Sgblack@eecs.umich.edu 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 3783823Ssaidi@eecs.umich.edu 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 3793598Sgblack@eecs.umich.edu 0x1A: Priv::rdstrand_sts_reg({{ 3807741Sgblack@eecs.umich.edu if (Pstate<2:> && !Hpstate<2:>) 3813598Sgblack@eecs.umich.edu Rd = StrandStsReg<0:>; 3823598Sgblack@eecs.umich.edu else 3833598Sgblack@eecs.umich.edu Rd = StrandStsReg; 3843598Sgblack@eecs.umich.edu }}); 3857741Sgblack@eecs.umich.edu // 0x1A is supposed to be reserved, but it reads the strand 3867741Sgblack@eecs.umich.edu // status register. 3877741Sgblack@eecs.umich.edu // 0x1B-0x1F should cause an illegal instruction exception 3882954Sgblack@eecs.umich.edu } 3893587Sgblack@eecs.umich.edu 0x29: decode RS1 { 3903587Sgblack@eecs.umich.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 3915094Sgblack@eecs.umich.edu 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 3927741Sgblack@eecs.umich.edu // 0x02 should cause an illegal instruction exception 3933587Sgblack@eecs.umich.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 3947741Sgblack@eecs.umich.edu // 0x04 should cause an illegal instruction exception 3953587Sgblack@eecs.umich.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 3963587Sgblack@eecs.umich.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 3977741Sgblack@eecs.umich.edu // 0x07-0x1E should cause an illegal instruction exception 3983823Ssaidi@eecs.umich.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 3993587Sgblack@eecs.umich.edu } 4003587Sgblack@eecs.umich.edu 0x2A: decode RS1 { 4015094Sgblack@eecs.umich.edu 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 4025094Sgblack@eecs.umich.edu 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 4035094Sgblack@eecs.umich.edu 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 4045094Sgblack@eecs.umich.edu 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 4053823Ssaidi@eecs.umich.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 4063587Sgblack@eecs.umich.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 4073587Sgblack@eecs.umich.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 4083587Sgblack@eecs.umich.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 4093587Sgblack@eecs.umich.edu 0x08: Priv::rdprpil({{Rd = Pil;}}); 4103587Sgblack@eecs.umich.edu 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 4113587Sgblack@eecs.umich.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 4123587Sgblack@eecs.umich.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 4133587Sgblack@eecs.umich.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 4143587Sgblack@eecs.umich.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 4153587Sgblack@eecs.umich.edu 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 4167741Sgblack@eecs.umich.edu // 0x0F should cause an illegal instruction exception 4173587Sgblack@eecs.umich.edu 0x10: Priv::rdprgl({{Rd = Gl;}}); 4187741Sgblack@eecs.umich.edu // 0x11-0x1F should cause an illegal instruction exception 4193587Sgblack@eecs.umich.edu } 4202526SN/A 0x2B: BasicOperate::flushw({{ 4217741Sgblack@eecs.umich.edu if (NWindows - 2 - Cansave != 0) { 4227741Sgblack@eecs.umich.edu if (Otherwin) 4233909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 4242526SN/A else 4253909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 4262526SN/A } 4272526SN/A }}); 4282526SN/A 0x2C: decode MOVCC3 4292469SN/A { 4307085Sgblack@eecs.umich.edu 0x0: decode CC 4317085Sgblack@eecs.umich.edu { 4327085Sgblack@eecs.umich.edu 0x0: movccfcc0({{ 4337741Sgblack@eecs.umich.edu if (passesCondition(Fsr<11:10>, COND4)) 4347085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4357085Sgblack@eecs.umich.edu else 4367085Sgblack@eecs.umich.edu Rd = Rd; 4377085Sgblack@eecs.umich.edu }}); 4387085Sgblack@eecs.umich.edu 0x1: movccfcc1({{ 4397741Sgblack@eecs.umich.edu if (passesCondition(Fsr<33:32>, COND4)) 4407085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4417085Sgblack@eecs.umich.edu else 4427085Sgblack@eecs.umich.edu Rd = Rd; 4437085Sgblack@eecs.umich.edu }}); 4447085Sgblack@eecs.umich.edu 0x2: movccfcc2({{ 4457741Sgblack@eecs.umich.edu if (passesCondition(Fsr<35:34>, COND4)) 4467085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4477085Sgblack@eecs.umich.edu else 4487085Sgblack@eecs.umich.edu Rd = Rd; 4497085Sgblack@eecs.umich.edu }}); 4507085Sgblack@eecs.umich.edu 0x3: movccfcc3({{ 4517741Sgblack@eecs.umich.edu if (passesCondition(Fsr<37:36>, COND4)) 4527085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4537085Sgblack@eecs.umich.edu else 4547085Sgblack@eecs.umich.edu Rd = Rd; 4557085Sgblack@eecs.umich.edu }}); 4567085Sgblack@eecs.umich.edu } 4572526SN/A 0x1: decode CC 4582526SN/A { 4592526SN/A 0x0: movcci({{ 4607741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND4)) 4612591SN/A Rd = Rs2_or_imm11; 4622591SN/A else 4632591SN/A Rd = Rd; 4642526SN/A }}); 4652526SN/A 0x2: movccx({{ 4667741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND4)) 4672591SN/A Rd = Rs2_or_imm11; 4682591SN/A else 4692591SN/A Rd = Rd; 4702526SN/A }}); 4712224SN/A } 4722526SN/A } 4732526SN/A 0x2D: sdivx({{ 4747741Sgblack@eecs.umich.edu if (Rs2_or_imm13.sdw == 0) 4757741Sgblack@eecs.umich.edu fault = new DivisionByZero; 4767741Sgblack@eecs.umich.edu else 4777741Sgblack@eecs.umich.edu Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4782526SN/A }}); 4793941Ssaidi@eecs.umich.edu 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 4802526SN/A 0x2F: decode RCOND3 4812526SN/A { 4822615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4832615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4842615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4852615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4862615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4872615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4882526SN/A } 4893587Sgblack@eecs.umich.edu 0x30: decode RD { 4903929Ssaidi@eecs.umich.edu 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 4917741Sgblack@eecs.umich.edu // 0x01 should cause an illegal instruction exception 4923587Sgblack@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 4937784SAli.Saidi@ARM.com 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false, 4947784SAli.Saidi@ARM.com IsSquashAfter); 4957741Sgblack@eecs.umich.edu // 0x04-0x05 should cause an illegal instruction exception 4963587Sgblack@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 4977741Sgblack@eecs.umich.edu // 0x07-0x0E should cause an illegal instruction exception 4983587Sgblack@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 4993587Sgblack@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 5005094Sgblack@eecs.umich.edu 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 5017741Sgblack@eecs.umich.edu // 0x12 should cause an illegal instruction exception 5023587Sgblack@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 5037741Sgblack@eecs.umich.edu if (Fprs<2:> == 0 || Pstate<4:> == 0) 5043587Sgblack@eecs.umich.edu return new FpDisabled; 5053587Sgblack@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 5063587Sgblack@eecs.umich.edu }}); 5073587Sgblack@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 5083587Sgblack@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 5093587Sgblack@eecs.umich.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 5103823Ssaidi@eecs.umich.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5113587Sgblack@eecs.umich.edu 0x18: NoPriv::wrstick({{ 5127741Sgblack@eecs.umich.edu if (!Hpstate<2:>) 5133587Sgblack@eecs.umich.edu return new IllegalInstruction; 5143823Ssaidi@eecs.umich.edu Stick = Rs1 ^ Rs2_or_imm13; 5153587Sgblack@eecs.umich.edu }}); 5163823Ssaidi@eecs.umich.edu 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5173598Sgblack@eecs.umich.edu 0x1A: Priv::wrstrand_sts_reg({{ 5183598Sgblack@eecs.umich.edu StrandStsReg = Rs1 ^ Rs2_or_imm13; 5193598Sgblack@eecs.umich.edu }}); 5207741Sgblack@eecs.umich.edu // 0x1A is supposed to be reserved, but it writes the strand 5217741Sgblack@eecs.umich.edu // status register. 5227741Sgblack@eecs.umich.edu // 0x1B-0x1F should cause an illegal instruction exception 5233587Sgblack@eecs.umich.edu } 5242526SN/A 0x31: decode FCN { 5253417Sgblack@eecs.umich.edu 0x0: Priv::saved({{ 5263417Sgblack@eecs.umich.edu assert(Cansave < NWindows - 2); 5273417Sgblack@eecs.umich.edu assert(Otherwin || Canrestore); 5283417Sgblack@eecs.umich.edu Cansave = Cansave + 1; 5297741Sgblack@eecs.umich.edu if (Otherwin == 0) 5303417Sgblack@eecs.umich.edu Canrestore = Canrestore - 1; 5313417Sgblack@eecs.umich.edu else 5323417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5333417Sgblack@eecs.umich.edu }}); 5343598Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 5353417Sgblack@eecs.umich.edu assert(Cansave || Otherwin); 5363417Sgblack@eecs.umich.edu assert(Canrestore < NWindows - 2); 5373417Sgblack@eecs.umich.edu Canrestore = Canrestore + 1; 5387741Sgblack@eecs.umich.edu if (Otherwin == 0) 5393417Sgblack@eecs.umich.edu Cansave = Cansave - 1; 5403417Sgblack@eecs.umich.edu else 5413417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5423928Ssaidi@eecs.umich.edu 5437741Sgblack@eecs.umich.edu if (Cleanwin < NWindows - 1) 5443928Ssaidi@eecs.umich.edu Cleanwin = Cleanwin + 1; 5453417Sgblack@eecs.umich.edu }}); 5462526SN/A } 5473587Sgblack@eecs.umich.edu 0x32: decode RD { 5485094Sgblack@eecs.umich.edu 0x00: Priv::wrprtpc( 5495094Sgblack@eecs.umich.edu {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5505094Sgblack@eecs.umich.edu 0x01: Priv::wrprtnpc( 5515094Sgblack@eecs.umich.edu {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5525094Sgblack@eecs.umich.edu 0x02: Priv::wrprtstate( 5535094Sgblack@eecs.umich.edu {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5545094Sgblack@eecs.umich.edu 0x03: Priv::wrprtt( 5555094Sgblack@eecs.umich.edu {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5563823Ssaidi@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 5573587Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 5583587Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 5593587Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 5607741Sgblack@eecs.umich.edu if (Pstate<2:> && !Hpstate<2:>) 5613587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 5623587Sgblack@eecs.umich.edu else 5633587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 5643587Sgblack@eecs.umich.edu }}); 5653587Sgblack@eecs.umich.edu 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 5663587Sgblack@eecs.umich.edu 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 5673587Sgblack@eecs.umich.edu 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 5683587Sgblack@eecs.umich.edu 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 5693587Sgblack@eecs.umich.edu 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 5703587Sgblack@eecs.umich.edu 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 5713587Sgblack@eecs.umich.edu 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 5727741Sgblack@eecs.umich.edu // 0x0F should cause an illegal instruction exception 5733587Sgblack@eecs.umich.edu 0x10: Priv::wrprgl({{ 5747741Sgblack@eecs.umich.edu if (Pstate<2:> && !Hpstate<2:>) 5753587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 5763587Sgblack@eecs.umich.edu else 5773587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 5783587Sgblack@eecs.umich.edu }}); 5797741Sgblack@eecs.umich.edu // 0x11-0x1F should cause an illegal instruction exception 5803587Sgblack@eecs.umich.edu } 5813587Sgblack@eecs.umich.edu 0x33: decode RD { 5823587Sgblack@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 5835094Sgblack@eecs.umich.edu 0x01: HPriv::wrhprhtstate( 5845094Sgblack@eecs.umich.edu {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5857741Sgblack@eecs.umich.edu // 0x02 should cause an illegal instruction exception 5863587Sgblack@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 5877741Sgblack@eecs.umich.edu // 0x04 should cause an illegal instruction exception 5883587Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 5897741Sgblack@eecs.umich.edu // 0x06-0x01D should cause an illegal instruction exception 5903823Ssaidi@eecs.umich.edu 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5913587Sgblack@eecs.umich.edu } 5922954Sgblack@eecs.umich.edu 0x34: decode OPF{ 5934008Ssaidi@eecs.umich.edu format FpBasic{ 5945095Sgblack@eecs.umich.edu 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 5955095Sgblack@eecs.umich.edu 0x02: fmovd({{Frd.udw = Frs2.udw;}}); 5963995Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq(); 5975095Sgblack@eecs.umich.edu 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 5985095Sgblack@eecs.umich.edu 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 5993995Sgblack@eecs.umich.edu 0x07: FpUnimpl::fnegq(); 6005095Sgblack@eecs.umich.edu 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 6015095Sgblack@eecs.umich.edu 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 6023995Sgblack@eecs.umich.edu 0x0B: FpUnimpl::fabsq(); 6033918Ssaidi@eecs.umich.edu 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 6043918Ssaidi@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 6053995Sgblack@eecs.umich.edu 0x2B: FpUnimpl::fsqrtq(); 6063279Sgblack@eecs.umich.edu 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 6072963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 6083995Sgblack@eecs.umich.edu 0x43: FpUnimpl::faddq(); 6093279Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 6104008Ssaidi@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 6113995Sgblack@eecs.umich.edu 0x47: FpUnimpl::fsubq(); 6123279Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 6132963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 6143995Sgblack@eecs.umich.edu 0x4B: FpUnimpl::fmulq(); 6153279Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 6162963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 6173995Sgblack@eecs.umich.edu 0x4F: FpUnimpl::fdivq(); 6183279Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 6193995Sgblack@eecs.umich.edu 0x6E: FpUnimpl::fdmulq(); 6205095Sgblack@eecs.umich.edu 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 6215095Sgblack@eecs.umich.edu 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 6223995Sgblack@eecs.umich.edu 0x83: FpUnimpl::fqtox(); 6235095Sgblack@eecs.umich.edu 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 6245095Sgblack@eecs.umich.edu 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 6253995Sgblack@eecs.umich.edu 0x8C: FpUnimpl::fxtoq(); 6265095Sgblack@eecs.umich.edu 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 6273279Sgblack@eecs.umich.edu 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 6283995Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fqtos(); 6295095Sgblack@eecs.umich.edu 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 6303279Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 6313995Sgblack@eecs.umich.edu 0xCB: FpUnimpl::fqtod(); 6323995Sgblack@eecs.umich.edu 0xCC: FpUnimpl::fitoq(); 6333995Sgblack@eecs.umich.edu 0xCD: FpUnimpl::fstoq(); 6343995Sgblack@eecs.umich.edu 0xCE: FpUnimpl::fdtoq(); 6352963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 6364008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2s.sf); 6374008Ssaidi@eecs.umich.edu float t = Frds.sw; 6384008Ssaidi@eecs.umich.edu if (t != Frs2s.sf) 6394008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6402963Sgblack@eecs.umich.edu }}); 6412963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 6424008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2.df); 6434008Ssaidi@eecs.umich.edu double t = Frds.sw; 6444008Ssaidi@eecs.umich.edu if (t != Frs2.df) 6454008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6462963Sgblack@eecs.umich.edu }}); 6473995Sgblack@eecs.umich.edu 0xD3: FpUnimpl::fqtoi(); 6483941Ssaidi@eecs.umich.edu default: FailUnimpl::fpop1(); 6492963Sgblack@eecs.umich.edu } 6502954Sgblack@eecs.umich.edu } 6513992Sgblack@eecs.umich.edu 0x35: decode OPF{ 6524008Ssaidi@eecs.umich.edu format FpBasic{ 6534204Sgblack@eecs.umich.edu 0x01: fmovs_fcc0({{ 6547741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<11:10>, COND4)) 6554204Sgblack@eecs.umich.edu Frds = Frs2s; 6564204Sgblack@eecs.umich.edu else 6574204Sgblack@eecs.umich.edu Frds = Frds; 6584204Sgblack@eecs.umich.edu }}); 6594204Sgblack@eecs.umich.edu 0x02: fmovd_fcc0({{ 6607741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<11:10>, COND4)) 6614204Sgblack@eecs.umich.edu Frd = Frs2; 6624204Sgblack@eecs.umich.edu else 6634204Sgblack@eecs.umich.edu Frd = Frd; 6644204Sgblack@eecs.umich.edu }}); 6654204Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq_fcc0(); 6664204Sgblack@eecs.umich.edu 0x25: fmovrsz({{ 6677741Sgblack@eecs.umich.edu if (Rs1 == 0) 6684204Sgblack@eecs.umich.edu Frds = Frs2s; 6694204Sgblack@eecs.umich.edu else 6704204Sgblack@eecs.umich.edu Frds = Frds; 6714204Sgblack@eecs.umich.edu }}); 6724204Sgblack@eecs.umich.edu 0x26: fmovrdz({{ 6737741Sgblack@eecs.umich.edu if (Rs1 == 0) 6744204Sgblack@eecs.umich.edu Frd = Frs2; 6754204Sgblack@eecs.umich.edu else 6764204Sgblack@eecs.umich.edu Frd = Frd; 6774204Sgblack@eecs.umich.edu }}); 6784204Sgblack@eecs.umich.edu 0x27: FpUnimpl::fmovrqz(); 6794204Sgblack@eecs.umich.edu 0x41: fmovs_fcc1({{ 6807741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<33:32>, COND4)) 6814204Sgblack@eecs.umich.edu Frds = Frs2s; 6824204Sgblack@eecs.umich.edu else 6834204Sgblack@eecs.umich.edu Frds = Frds; 6844204Sgblack@eecs.umich.edu }}); 6854204Sgblack@eecs.umich.edu 0x42: fmovd_fcc1({{ 6867741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<33:32>, COND4)) 6874204Sgblack@eecs.umich.edu Frd = Frs2; 6884204Sgblack@eecs.umich.edu else 6894204Sgblack@eecs.umich.edu Frd = Frd; 6904204Sgblack@eecs.umich.edu }}); 6914204Sgblack@eecs.umich.edu 0x43: FpUnimpl::fmovq_fcc1(); 6924204Sgblack@eecs.umich.edu 0x45: fmovrslez({{ 6937741Sgblack@eecs.umich.edu if (Rs1 <= 0) 6944204Sgblack@eecs.umich.edu Frds = Frs2s; 6954204Sgblack@eecs.umich.edu else 6964204Sgblack@eecs.umich.edu Frds = Frds; 6974204Sgblack@eecs.umich.edu }}); 6984204Sgblack@eecs.umich.edu 0x46: fmovrdlez({{ 6997741Sgblack@eecs.umich.edu if (Rs1 <= 0) 7004204Sgblack@eecs.umich.edu Frd = Frs2; 7014204Sgblack@eecs.umich.edu else 7024204Sgblack@eecs.umich.edu Frd = Frd; 7034204Sgblack@eecs.umich.edu }}); 7044204Sgblack@eecs.umich.edu 0x47: FpUnimpl::fmovrqlez(); 7053992Sgblack@eecs.umich.edu 0x51: fcmps({{ 7063992Sgblack@eecs.umich.edu uint8_t fcc; 7077741Sgblack@eecs.umich.edu if (isnan(Frs1s) || isnan(Frs2s)) 7083992Sgblack@eecs.umich.edu fcc = 3; 7097741Sgblack@eecs.umich.edu else if (Frs1s < Frs2s) 7103992Sgblack@eecs.umich.edu fcc = 1; 7117741Sgblack@eecs.umich.edu else if (Frs1s > Frs2s) 7123992Sgblack@eecs.umich.edu fcc = 2; 7133992Sgblack@eecs.umich.edu else 7143992Sgblack@eecs.umich.edu fcc = 0; 7153992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7167741Sgblack@eecs.umich.edu if (FCMPCC) 7173992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7183992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7193992Sgblack@eecs.umich.edu }}); 7203992Sgblack@eecs.umich.edu 0x52: fcmpd({{ 7213992Sgblack@eecs.umich.edu uint8_t fcc; 7227741Sgblack@eecs.umich.edu if (isnan(Frs1) || isnan(Frs2)) 7233992Sgblack@eecs.umich.edu fcc = 3; 7247741Sgblack@eecs.umich.edu else if (Frs1 < Frs2) 7253992Sgblack@eecs.umich.edu fcc = 1; 7267741Sgblack@eecs.umich.edu else if (Frs1 > Frs2) 7273992Sgblack@eecs.umich.edu fcc = 2; 7283992Sgblack@eecs.umich.edu else 7293992Sgblack@eecs.umich.edu fcc = 0; 7303992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7317741Sgblack@eecs.umich.edu if (FCMPCC) 7323992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7333992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7343992Sgblack@eecs.umich.edu }}); 7353995Sgblack@eecs.umich.edu 0x53: FpUnimpl::fcmpq(); 7363997Ssaidi@eecs.umich.edu 0x55: fcmpes({{ 7373992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7387741Sgblack@eecs.umich.edu if (isnan(Frs1s) || isnan(Frs2s)) 7393992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7407741Sgblack@eecs.umich.edu if (Frs1s < Frs2s) 7413992Sgblack@eecs.umich.edu fcc = 1; 7427741Sgblack@eecs.umich.edu else if (Frs1s > Frs2s) 7433992Sgblack@eecs.umich.edu fcc = 2; 7443992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7457741Sgblack@eecs.umich.edu if (FCMPCC) 7463992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7473992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7483992Sgblack@eecs.umich.edu }}); 7493997Ssaidi@eecs.umich.edu 0x56: fcmped({{ 7503992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7517741Sgblack@eecs.umich.edu if (isnan(Frs1) || isnan(Frs2)) 7523992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7537741Sgblack@eecs.umich.edu if (Frs1 < Frs2) 7543992Sgblack@eecs.umich.edu fcc = 1; 7557741Sgblack@eecs.umich.edu else if (Frs1 > Frs2) 7563992Sgblack@eecs.umich.edu fcc = 2; 7573992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7587741Sgblack@eecs.umich.edu if (FCMPCC) 7593992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7603992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7613992Sgblack@eecs.umich.edu }}); 7623997Ssaidi@eecs.umich.edu 0x57: FpUnimpl::fcmpeq(); 7634204Sgblack@eecs.umich.edu 0x65: fmovrslz({{ 7647741Sgblack@eecs.umich.edu if (Rs1 < 0) 7654204Sgblack@eecs.umich.edu Frds = Frs2s; 7664204Sgblack@eecs.umich.edu else 7674204Sgblack@eecs.umich.edu Frds = Frds; 7684204Sgblack@eecs.umich.edu }}); 7694204Sgblack@eecs.umich.edu 0x66: fmovrdlz({{ 7707741Sgblack@eecs.umich.edu if (Rs1 < 0) 7714204Sgblack@eecs.umich.edu Frd = Frs2; 7724204Sgblack@eecs.umich.edu else 7734204Sgblack@eecs.umich.edu Frd = Frd; 7744204Sgblack@eecs.umich.edu }}); 7754204Sgblack@eecs.umich.edu 0x67: FpUnimpl::fmovrqlz(); 7764204Sgblack@eecs.umich.edu 0x81: fmovs_fcc2({{ 7777741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<35:34>, COND4)) 7784204Sgblack@eecs.umich.edu Frds = Frs2s; 7794204Sgblack@eecs.umich.edu else 7804204Sgblack@eecs.umich.edu Frds = Frds; 7814204Sgblack@eecs.umich.edu }}); 7824204Sgblack@eecs.umich.edu 0x82: fmovd_fcc2({{ 7837741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<35:34>, COND4)) 7844204Sgblack@eecs.umich.edu Frd = Frs2; 7854204Sgblack@eecs.umich.edu else 7864204Sgblack@eecs.umich.edu Frd = Frd; 7874204Sgblack@eecs.umich.edu }}); 7884204Sgblack@eecs.umich.edu 0x83: FpUnimpl::fmovq_fcc2(); 7894204Sgblack@eecs.umich.edu 0xA5: fmovrsnz({{ 7907741Sgblack@eecs.umich.edu if (Rs1 != 0) 7914204Sgblack@eecs.umich.edu Frds = Frs2s; 7924204Sgblack@eecs.umich.edu else 7934204Sgblack@eecs.umich.edu Frds = Frds; 7944204Sgblack@eecs.umich.edu }}); 7954204Sgblack@eecs.umich.edu 0xA6: fmovrdnz({{ 7967741Sgblack@eecs.umich.edu if (Rs1 != 0) 7974204Sgblack@eecs.umich.edu Frd = Frs2; 7984204Sgblack@eecs.umich.edu else 7994204Sgblack@eecs.umich.edu Frd = Frd; 8004204Sgblack@eecs.umich.edu }}); 8014204Sgblack@eecs.umich.edu 0xA7: FpUnimpl::fmovrqnz(); 8024204Sgblack@eecs.umich.edu 0xC1: fmovs_fcc3({{ 8037741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<37:36>, COND4)) 8044204Sgblack@eecs.umich.edu Frds = Frs2s; 8054204Sgblack@eecs.umich.edu else 8064204Sgblack@eecs.umich.edu Frds = Frds; 8074204Sgblack@eecs.umich.edu }}); 8084204Sgblack@eecs.umich.edu 0xC2: fmovd_fcc3({{ 8097741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<37:36>, COND4)) 8104204Sgblack@eecs.umich.edu Frd = Frs2; 8114204Sgblack@eecs.umich.edu else 8124204Sgblack@eecs.umich.edu Frd = Frd; 8134204Sgblack@eecs.umich.edu }}); 8144204Sgblack@eecs.umich.edu 0xC3: FpUnimpl::fmovq_fcc3(); 8154204Sgblack@eecs.umich.edu 0xC5: fmovrsgz({{ 8167741Sgblack@eecs.umich.edu if (Rs1 > 0) 8174204Sgblack@eecs.umich.edu Frds = Frs2s; 8184204Sgblack@eecs.umich.edu else 8194204Sgblack@eecs.umich.edu Frds = Frds; 8204204Sgblack@eecs.umich.edu }}); 8214204Sgblack@eecs.umich.edu 0xC6: fmovrdgz({{ 8227741Sgblack@eecs.umich.edu if (Rs1 > 0) 8234204Sgblack@eecs.umich.edu Frd = Frs2; 8244204Sgblack@eecs.umich.edu else 8254204Sgblack@eecs.umich.edu Frd = Frd; 8264204Sgblack@eecs.umich.edu }}); 8274204Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fmovrqgz(); 8284204Sgblack@eecs.umich.edu 0xE5: fmovrsgez({{ 8297741Sgblack@eecs.umich.edu if (Rs1 >= 0) 8304204Sgblack@eecs.umich.edu Frds = Frs2s; 8314204Sgblack@eecs.umich.edu else 8324204Sgblack@eecs.umich.edu Frds = Frds; 8334204Sgblack@eecs.umich.edu }}); 8344204Sgblack@eecs.umich.edu 0xE6: fmovrdgez({{ 8357741Sgblack@eecs.umich.edu if (Rs1 >= 0) 8364204Sgblack@eecs.umich.edu Frd = Frs2; 8374204Sgblack@eecs.umich.edu else 8384204Sgblack@eecs.umich.edu Frd = Frd; 8394204Sgblack@eecs.umich.edu }}); 8404204Sgblack@eecs.umich.edu 0xE7: FpUnimpl::fmovrqgez(); 8414204Sgblack@eecs.umich.edu 0x101: fmovs_icc({{ 8427741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND4)) 8434204Sgblack@eecs.umich.edu Frds = Frs2s; 8444204Sgblack@eecs.umich.edu else 8454204Sgblack@eecs.umich.edu Frds = Frds; 8464204Sgblack@eecs.umich.edu }}); 8474204Sgblack@eecs.umich.edu 0x102: fmovd_icc({{ 8487741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND4)) 8494204Sgblack@eecs.umich.edu Frd = Frs2; 8504204Sgblack@eecs.umich.edu else 8514204Sgblack@eecs.umich.edu Frd = Frd; 8524204Sgblack@eecs.umich.edu }}); 8534204Sgblack@eecs.umich.edu 0x103: FpUnimpl::fmovq_icc(); 8544204Sgblack@eecs.umich.edu 0x181: fmovs_xcc({{ 8557741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND4)) 8564204Sgblack@eecs.umich.edu Frds = Frs2s; 8574204Sgblack@eecs.umich.edu else 8584204Sgblack@eecs.umich.edu Frds = Frds; 8594204Sgblack@eecs.umich.edu }}); 8604204Sgblack@eecs.umich.edu 0x182: fmovd_xcc({{ 8617741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND4)) 8624204Sgblack@eecs.umich.edu Frd = Frs2; 8634204Sgblack@eecs.umich.edu else 8644204Sgblack@eecs.umich.edu Frd = Frd; 8654204Sgblack@eecs.umich.edu }}); 8664204Sgblack@eecs.umich.edu 0x183: FpUnimpl::fmovq_xcc(); 8673992Sgblack@eecs.umich.edu default: FailUnimpl::fpop2(); 8683992Sgblack@eecs.umich.edu } 8693992Sgblack@eecs.umich.edu } 8707741Sgblack@eecs.umich.edu // This used to be just impdep1, but now it's a whole bunch 8717741Sgblack@eecs.umich.edu // of instructions 8722954Sgblack@eecs.umich.edu 0x36: decode OPF{ 8733941Ssaidi@eecs.umich.edu 0x00: FailUnimpl::edge8(); 8743941Ssaidi@eecs.umich.edu 0x01: FailUnimpl::edge8n(); 8753941Ssaidi@eecs.umich.edu 0x02: FailUnimpl::edge8l(); 8763941Ssaidi@eecs.umich.edu 0x03: FailUnimpl::edge8ln(); 8773941Ssaidi@eecs.umich.edu 0x04: FailUnimpl::edge16(); 8783941Ssaidi@eecs.umich.edu 0x05: FailUnimpl::edge16n(); 8793941Ssaidi@eecs.umich.edu 0x06: FailUnimpl::edge16l(); 8803941Ssaidi@eecs.umich.edu 0x07: FailUnimpl::edge16ln(); 8813941Ssaidi@eecs.umich.edu 0x08: FailUnimpl::edge32(); 8823941Ssaidi@eecs.umich.edu 0x09: FailUnimpl::edge32n(); 8833941Ssaidi@eecs.umich.edu 0x0A: FailUnimpl::edge32l(); 8843941Ssaidi@eecs.umich.edu 0x0B: FailUnimpl::edge32ln(); 8853941Ssaidi@eecs.umich.edu 0x10: FailUnimpl::array8(); 8863941Ssaidi@eecs.umich.edu 0x12: FailUnimpl::array16(); 8873941Ssaidi@eecs.umich.edu 0x14: FailUnimpl::array32(); 8883042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 8892963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8903042Sgblack@eecs.umich.edu Rd = sum & ~7; 8912963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 8922963Sgblack@eecs.umich.edu }}); 8933941Ssaidi@eecs.umich.edu 0x19: FailUnimpl::bmask(); 8942963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 8952963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8963042Sgblack@eecs.umich.edu Rd = sum & ~7; 8972963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 8982963Sgblack@eecs.umich.edu }}); 8993941Ssaidi@eecs.umich.edu 0x20: FailUnimpl::fcmple16(); 9003941Ssaidi@eecs.umich.edu 0x22: FailUnimpl::fcmpne16(); 9013941Ssaidi@eecs.umich.edu 0x24: FailUnimpl::fcmple32(); 9023941Ssaidi@eecs.umich.edu 0x26: FailUnimpl::fcmpne32(); 9033941Ssaidi@eecs.umich.edu 0x28: FailUnimpl::fcmpgt16(); 9043941Ssaidi@eecs.umich.edu 0x2A: FailUnimpl::fcmpeq16(); 9053941Ssaidi@eecs.umich.edu 0x2C: FailUnimpl::fcmpgt32(); 9063941Ssaidi@eecs.umich.edu 0x2E: FailUnimpl::fcmpeq32(); 9073941Ssaidi@eecs.umich.edu 0x31: FailUnimpl::fmul8x16(); 9083941Ssaidi@eecs.umich.edu 0x33: FailUnimpl::fmul8x16au(); 9093941Ssaidi@eecs.umich.edu 0x35: FailUnimpl::fmul8x16al(); 9103941Ssaidi@eecs.umich.edu 0x36: FailUnimpl::fmul8sux16(); 9113941Ssaidi@eecs.umich.edu 0x37: FailUnimpl::fmul8ulx16(); 9123941Ssaidi@eecs.umich.edu 0x38: FailUnimpl::fmuld8sux16(); 9133941Ssaidi@eecs.umich.edu 0x39: FailUnimpl::fmuld8ulx16(); 9142954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 9152954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 9162954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 9172954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 9182963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 9193057Sgblack@eecs.umich.edu uint64_t msbX = Frs1.udw; 9203057Sgblack@eecs.umich.edu uint64_t lsbX = Frs2.udw; 9217741Sgblack@eecs.umich.edu // Some special cases need to be split out, first 9227741Sgblack@eecs.umich.edu // because they're the most likely to be used, and 9237741Sgblack@eecs.umich.edu // second because otherwise, we end up shifting by 9247741Sgblack@eecs.umich.edu // greater than the width of the type being shifted, 9257741Sgblack@eecs.umich.edu // namely 64, which produces undefined results 9267741Sgblack@eecs.umich.edu // according to the C standard. 9277741Sgblack@eecs.umich.edu switch (Gsr<2:0>) { 9287741Sgblack@eecs.umich.edu case 0: 9297741Sgblack@eecs.umich.edu Frd.udw = msbX; 9307741Sgblack@eecs.umich.edu break; 9317741Sgblack@eecs.umich.edu case 8: 9327741Sgblack@eecs.umich.edu Frd.udw = lsbX; 9337741Sgblack@eecs.umich.edu break; 9347741Sgblack@eecs.umich.edu default: 9357741Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 9367741Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 9377741Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 9387741Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 9397741Sgblack@eecs.umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 9407741Sgblack@eecs.umich.edu ((lsbX & lsbMask) >> lsbShift); 9413057Sgblack@eecs.umich.edu } 9422963Sgblack@eecs.umich.edu }}); 9432954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 9443941Ssaidi@eecs.umich.edu 0x4C: FailUnimpl::bshuffle(); 9453941Ssaidi@eecs.umich.edu 0x4D: FailUnimpl::fexpand(); 9463941Ssaidi@eecs.umich.edu 0x50: FailUnimpl::fpadd16(); 9473941Ssaidi@eecs.umich.edu 0x51: FailUnimpl::fpadd16s(); 9483941Ssaidi@eecs.umich.edu 0x52: FailUnimpl::fpadd32(); 9493941Ssaidi@eecs.umich.edu 0x53: FailUnimpl::fpadd32s(); 9503941Ssaidi@eecs.umich.edu 0x54: FailUnimpl::fpsub16(); 9513941Ssaidi@eecs.umich.edu 0x55: FailUnimpl::fpsub16s(); 9523941Ssaidi@eecs.umich.edu 0x56: FailUnimpl::fpsub32(); 9533941Ssaidi@eecs.umich.edu 0x57: FailUnimpl::fpsub32s(); 9544008Ssaidi@eecs.umich.edu 0x60: FpBasic::fzero({{Frd.df = 0;}}); 9554008Ssaidi@eecs.umich.edu 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 9563941Ssaidi@eecs.umich.edu 0x62: FailUnimpl::fnor(); 9573941Ssaidi@eecs.umich.edu 0x63: FailUnimpl::fnors(); 9583941Ssaidi@eecs.umich.edu 0x64: FailUnimpl::fandnot2(); 9593941Ssaidi@eecs.umich.edu 0x65: FailUnimpl::fandnot2s(); 9604008Ssaidi@eecs.umich.edu 0x66: FpBasic::fnot2({{ 9612963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 9622963Sgblack@eecs.umich.edu }}); 9634008Ssaidi@eecs.umich.edu 0x67: FpBasic::fnot2s({{ 9643279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 9652963Sgblack@eecs.umich.edu }}); 9663941Ssaidi@eecs.umich.edu 0x68: FailUnimpl::fandnot1(); 9673941Ssaidi@eecs.umich.edu 0x69: FailUnimpl::fandnot1s(); 9684008Ssaidi@eecs.umich.edu 0x6A: FpBasic::fnot1({{ 9692963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 9702963Sgblack@eecs.umich.edu }}); 9714008Ssaidi@eecs.umich.edu 0x6B: FpBasic::fnot1s({{ 9723279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 9732963Sgblack@eecs.umich.edu }}); 9743941Ssaidi@eecs.umich.edu 0x6C: FailUnimpl::fxor(); 9753941Ssaidi@eecs.umich.edu 0x6D: FailUnimpl::fxors(); 9763941Ssaidi@eecs.umich.edu 0x6E: FailUnimpl::fnand(); 9773941Ssaidi@eecs.umich.edu 0x6F: FailUnimpl::fnands(); 9783941Ssaidi@eecs.umich.edu 0x70: FailUnimpl::fand(); 9793941Ssaidi@eecs.umich.edu 0x71: FailUnimpl::fands(); 9803941Ssaidi@eecs.umich.edu 0x72: FailUnimpl::fxnor(); 9813941Ssaidi@eecs.umich.edu 0x73: FailUnimpl::fxnors(); 9824008Ssaidi@eecs.umich.edu 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 9834008Ssaidi@eecs.umich.edu 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 9843941Ssaidi@eecs.umich.edu 0x76: FailUnimpl::fornot2(); 9853941Ssaidi@eecs.umich.edu 0x77: FailUnimpl::fornot2s(); 9864008Ssaidi@eecs.umich.edu 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 9874008Ssaidi@eecs.umich.edu 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 9883941Ssaidi@eecs.umich.edu 0x7A: FailUnimpl::fornot1(); 9893941Ssaidi@eecs.umich.edu 0x7B: FailUnimpl::fornot1s(); 9903941Ssaidi@eecs.umich.edu 0x7C: FailUnimpl::for(); 9913941Ssaidi@eecs.umich.edu 0x7D: FailUnimpl::fors(); 9924008Ssaidi@eecs.umich.edu 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 9934008Ssaidi@eecs.umich.edu 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 9942954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 9953941Ssaidi@eecs.umich.edu 0x81: FailUnimpl::siam(); 9962954Sgblack@eecs.umich.edu } 9974090Ssaidi@eecs.umich.edu // M5 special opcodes use the reserved IMPDEP2A opcode space 9984090Ssaidi@eecs.umich.edu 0x37: decode M5FUNC { 9994096Sgblack@eecs.umich.edu#if FULL_SYSTEM 10004113Sgblack@eecs.umich.edu format BasicOperate { 10014113Sgblack@eecs.umich.edu // we have 7 bits of space here to play with... 10024113Sgblack@eecs.umich.edu 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 10034113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10044113Sgblack@eecs.umich.edu 0x50: m5readfile({{ 10054113Sgblack@eecs.umich.edu O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 10064113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10074113Sgblack@eecs.umich.edu 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 10084113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10094113Sgblack@eecs.umich.edu 0x54: m5panic({{ 10107720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 10117720Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc=%#x.", pc.pc()); 10124113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10134113Sgblack@eecs.umich.edu } 10144096Sgblack@eecs.umich.edu#endif 10154096Sgblack@eecs.umich.edu default: Trap::impdep2({{fault = new IllegalInstruction;}}); 10164090Ssaidi@eecs.umich.edu } 10172526SN/A 0x38: Branch::jmpl({{ 10182526SN/A Addr target = Rs1 + Rs2_or_imm13; 10197741Sgblack@eecs.umich.edu if (target & 0x3) { 10202526SN/A fault = new MemAddressNotAligned; 10217741Sgblack@eecs.umich.edu } else { 10227720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 10233928Ssaidi@eecs.umich.edu if (Pstate<3:>) 10247720Sgblack@eecs.umich.edu Rd = (pc.pc())<31:0>; 10253928Ssaidi@eecs.umich.edu else 10267720Sgblack@eecs.umich.edu Rd = pc.pc(); 10277720Sgblack@eecs.umich.edu pc.nnpc(target); 10287720Sgblack@eecs.umich.edu PCS = pc; 10292526SN/A } 10302526SN/A }}); 10312526SN/A 0x39: Branch::return({{ 10322526SN/A Addr target = Rs1 + Rs2_or_imm13; 10337741Sgblack@eecs.umich.edu if (fault == NoFault) { 10347741Sgblack@eecs.umich.edu // Check for fills which are higher priority than alignment 10357741Sgblack@eecs.umich.edu // faults. 10367741Sgblack@eecs.umich.edu if (Canrestore == 0) { 10377741Sgblack@eecs.umich.edu if (Otherwin) 10383909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10392561SN/A else 10403909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10417741Sgblack@eecs.umich.edu } else if (target & 0x3) { // Check for alignment faults 10423765Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 10437741Sgblack@eecs.umich.edu } else { 10447720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 10457720Sgblack@eecs.umich.edu pc.nnpc(target); 10467720Sgblack@eecs.umich.edu PCS = pc; 10473417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10482561SN/A Cansave = Cansave + 1; 10492561SN/A Canrestore = Canrestore - 1; 10502561SN/A } 10512561SN/A } 10522526SN/A }}); 10532526SN/A 0x3A: decode CC 10542526SN/A { 10552526SN/A 0x0: Trap::tcci({{ 10567741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND2)) { 10572561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10582561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10593531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10602561SN/A } 10614828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10622526SN/A 0x2: Trap::tccx({{ 10637741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND2)) { 10642561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10652561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10663531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10672526SN/A } 10684828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10692526SN/A } 10704090Ssaidi@eecs.umich.edu 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 10714090Ssaidi@eecs.umich.edu MemWriteOp); 10722526SN/A 0x3C: save({{ 10737741Sgblack@eecs.umich.edu if (Cansave == 0) { 10747741Sgblack@eecs.umich.edu if (Otherwin) 10753909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 10762526SN/A else 10773909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 10787741Sgblack@eecs.umich.edu } else if (Cleanwin - Canrestore == 0) { 10792526SN/A fault = new CleanWindow; 10807741Sgblack@eecs.umich.edu } else { 10812526SN/A Cwp = (Cwp + 1) % NWindows; 10823765Sgblack@eecs.umich.edu Rd_next = Rs1 + Rs2_or_imm13; 10832561SN/A Cansave = Cansave - 1; 10842561SN/A Canrestore = Canrestore + 1; 10852526SN/A } 10862526SN/A }}); 10872526SN/A 0x3D: restore({{ 10887741Sgblack@eecs.umich.edu if (Canrestore == 0) { 10897741Sgblack@eecs.umich.edu if (Otherwin) 10903909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10912526SN/A else 10923909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10937741Sgblack@eecs.umich.edu } else { 10943417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10953765Sgblack@eecs.umich.edu Rd_prev = Rs1 + Rs2_or_imm13; 10962561SN/A Cansave = Cansave + 1; 10972561SN/A Canrestore = Canrestore - 1; 10982526SN/A } 10992526SN/A }}); 11002526SN/A 0x3E: decode FCN { 11012526SN/A 0x0: Priv::done({{ 11022646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11032646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11042646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11052646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11062646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11073825Ssaidi@eecs.umich.edu Hpstate = Htstate; 11087720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 11097720Sgblack@eecs.umich.edu pc.npc(Tnpc); 11107720Sgblack@eecs.umich.edu pc.nnpc(Tnpc + 4); 11117720Sgblack@eecs.umich.edu PCS = pc; 11122526SN/A Tl = Tl - 1; 11135094Sgblack@eecs.umich.edu }}, checkTl=true); 11142938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 11152646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11162646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11172646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11182646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11192646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11203826Ssaidi@eecs.umich.edu Hpstate = Htstate; 11217720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 11227720Sgblack@eecs.umich.edu pc.npc(Tpc); 11237720Sgblack@eecs.umich.edu pc.nnpc(Tnpc); 11247720Sgblack@eecs.umich.edu PCS = pc; 11252526SN/A Tl = Tl - 1; 11265094Sgblack@eecs.umich.edu }}, checkTl=true); 11272526SN/A } 11282526SN/A } 11292469SN/A } 11302469SN/A 0x3: decode OP3 { 11312526SN/A format Load { 11323272Sgblack@eecs.umich.edu 0x00: lduw({{Rd = Mem.uw;}}); 11333272Sgblack@eecs.umich.edu 0x01: ldub({{Rd = Mem.ub;}}); 11343272Sgblack@eecs.umich.edu 0x02: lduh({{Rd = Mem.uhw;}}); 11353835Sgblack@eecs.umich.edu 0x03: ldtw({{ 11364115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 11374115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 11383272Sgblack@eecs.umich.edu }}); 11392526SN/A } 11402526SN/A format Store { 11413272Sgblack@eecs.umich.edu 0x04: stw({{Mem.uw = Rd.sw;}}); 11423272Sgblack@eecs.umich.edu 0x05: stb({{Mem.ub = Rd.sb;}}); 11433272Sgblack@eecs.umich.edu 0x06: sth({{Mem.uhw = Rd.shw;}}); 11444224Sgblack@eecs.umich.edu 0x07: sttw({{ 11457741Sgblack@eecs.umich.edu // This temporary needs to be here so that the parser 11467741Sgblack@eecs.umich.edu // will correctly identify this instruction as a store. 11477741Sgblack@eecs.umich.edu // It's probably either the parenthesis or referencing 11487741Sgblack@eecs.umich.edu // the member variable that throws confuses it. 11494256Sgblack@eecs.umich.edu Twin32_t temp; 11504256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 11514256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 11524256Sgblack@eecs.umich.edu Mem.tuw = temp; 11534224Sgblack@eecs.umich.edu }}); 11542526SN/A } 11552526SN/A format Load { 11563272Sgblack@eecs.umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 11573272Sgblack@eecs.umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 11583272Sgblack@eecs.umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 11593272Sgblack@eecs.umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 11602526SN/A } 11614040Ssaidi@eecs.umich.edu 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 11624040Ssaidi@eecs.umich.edu {{ 11634040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 11644040Ssaidi@eecs.umich.edu Rd.ub = tmp; 11654040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11663272Sgblack@eecs.umich.edu 0x0E: Store::stx({{Mem.udw = Rd}}); 11674040Ssaidi@eecs.umich.edu 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 11684040Ssaidi@eecs.umich.edu {{ 11694040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 11704040Ssaidi@eecs.umich.edu Rd.uw = tmp; 11714040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11723810Sgblack@eecs.umich.edu format LoadAlt { 11735096Sgblack@eecs.umich.edu 0x10: lduwa({{Rd = Mem.uw;}}); 11745096Sgblack@eecs.umich.edu 0x11: lduba({{Rd = Mem.ub;}}); 11755096Sgblack@eecs.umich.edu 0x12: lduha({{Rd = Mem.uhw;}}); 11763856Ssaidi@eecs.umich.edu 0x13: decode EXT_ASI { 11777741Sgblack@eecs.umich.edu // ASI_LDTD_AIUP 11783926Ssaidi@eecs.umich.edu 0x22: TwinLoad::ldtx_aiup( 11794040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11805096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11817741Sgblack@eecs.umich.edu // ASI_LDTD_AIUS 11823926Ssaidi@eecs.umich.edu 0x23: TwinLoad::ldtx_aius( 11834040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11845096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11857741Sgblack@eecs.umich.edu // ASI_QUAD_LDD 11863856Ssaidi@eecs.umich.edu 0x24: TwinLoad::ldtx_quad_ldd( 11874040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11885096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11897741Sgblack@eecs.umich.edu // ASI_LDTX_REAL 11903856Ssaidi@eecs.umich.edu 0x26: TwinLoad::ldtx_real( 11914040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11925096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11937741Sgblack@eecs.umich.edu // ASI_LDTX_N 11944040Ssaidi@eecs.umich.edu 0x27: TwinLoad::ldtx_n( 11954040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11965096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11977741Sgblack@eecs.umich.edu // ASI_LDTX_AIUP_L 11984040Ssaidi@eecs.umich.edu 0x2A: TwinLoad::ldtx_aiup_l( 11994040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12005096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12017741Sgblack@eecs.umich.edu // ASI_LDTX_AIUS_L 12024040Ssaidi@eecs.umich.edu 0x2B: TwinLoad::ldtx_aius_l( 12034040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12045096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12057741Sgblack@eecs.umich.edu // ASI_LDTX_L 12064040Ssaidi@eecs.umich.edu 0x2C: TwinLoad::ldtx_l( 12074040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12085096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12097741Sgblack@eecs.umich.edu // ASI_LDTX_REAL_L 12103856Ssaidi@eecs.umich.edu 0x2E: TwinLoad::ldtx_real_l( 12114040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12125096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12137741Sgblack@eecs.umich.edu // ASI_LDTX_N_L 12143856Ssaidi@eecs.umich.edu 0x2F: TwinLoad::ldtx_n_l( 12154040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12165096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12177741Sgblack@eecs.umich.edu // ASI_LDTX_P 12183901Ssaidi@eecs.umich.edu 0xE2: TwinLoad::ldtx_p( 12194040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12205096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12217741Sgblack@eecs.umich.edu // ASI_LDTX_S 12223926Ssaidi@eecs.umich.edu 0xE3: TwinLoad::ldtx_s( 12234040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12245096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12257741Sgblack@eecs.umich.edu // ASI_LDTX_PL 12264040Ssaidi@eecs.umich.edu 0xEA: TwinLoad::ldtx_pl( 12274040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12285096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12297741Sgblack@eecs.umich.edu // ASI_LDTX_SL 12304040Ssaidi@eecs.umich.edu 0xEB: TwinLoad::ldtx_sl( 12314040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12325096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12333856Ssaidi@eecs.umich.edu default: ldtwa({{ 12344115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 12355096Sgblack@eecs.umich.edu RdHigh = (Mem.tuw).b;}}); 12363856Ssaidi@eecs.umich.edu } 12372526SN/A } 12383810Sgblack@eecs.umich.edu format StoreAlt { 12395096Sgblack@eecs.umich.edu 0x14: stwa({{Mem.uw = Rd;}}); 12405096Sgblack@eecs.umich.edu 0x15: stba({{Mem.ub = Rd;}}); 12415096Sgblack@eecs.umich.edu 0x16: stha({{Mem.uhw = Rd;}}); 12424224Sgblack@eecs.umich.edu 0x17: sttwa({{ 12437741Sgblack@eecs.umich.edu // This temporary needs to be here so that the parser 12447741Sgblack@eecs.umich.edu // will correctly identify this instruction as a store. 12457741Sgblack@eecs.umich.edu // It's probably either the parenthesis or referencing 12467741Sgblack@eecs.umich.edu // the member variable that throws confuses it. 12474256Sgblack@eecs.umich.edu Twin32_t temp; 12484256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 12494256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 12504256Sgblack@eecs.umich.edu Mem.tuw = temp; 12515096Sgblack@eecs.umich.edu }}); 12522526SN/A } 12533810Sgblack@eecs.umich.edu format LoadAlt { 12545096Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 12555096Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 12565096Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 12575096Sgblack@eecs.umich.edu 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 12582526SN/A } 12594040Ssaidi@eecs.umich.edu 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 12604040Ssaidi@eecs.umich.edu {{ 12614040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 12624040Ssaidi@eecs.umich.edu Rd.ub = tmp; 12635096Sgblack@eecs.umich.edu }}, MEM_SWAP); 12645096Sgblack@eecs.umich.edu 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 12654040Ssaidi@eecs.umich.edu 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 12664040Ssaidi@eecs.umich.edu {{ 12674040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 12684040Ssaidi@eecs.umich.edu Rd.uw = tmp; 12695096Sgblack@eecs.umich.edu }}, MEM_SWAP); 12704040Ssaidi@eecs.umich.edu 12712526SN/A format Trap { 12723931Ssaidi@eecs.umich.edu 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 12734008Ssaidi@eecs.umich.edu 0x21: decode RD { 12744011Ssaidi@eecs.umich.edu 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 12754011Ssaidi@eecs.umich.edu if (fault) 12764011Ssaidi@eecs.umich.edu return fault; 12774011Ssaidi@eecs.umich.edu Fsr = Mem.uw | Fsr<63:32>;}}); 12784011Ssaidi@eecs.umich.edu 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 12794011Ssaidi@eecs.umich.edu if (fault) 12804011Ssaidi@eecs.umich.edu return fault; 12814011Ssaidi@eecs.umich.edu Fsr = Mem.udw;}}); 12824008Ssaidi@eecs.umich.edu default: FailUnimpl::ldfsrOther(); 12832469SN/A } 12842526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 12853272Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 12863931Ssaidi@eecs.umich.edu 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 12874008Ssaidi@eecs.umich.edu 0x25: decode RD { 12885893Sgblack@eecs.umich.edu 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 12895893Sgblack@eecs.umich.edu if (fault) 12905893Sgblack@eecs.umich.edu return fault; 12915893Sgblack@eecs.umich.edu Mem.uw = Fsr<31:0>;}}); 12925893Sgblack@eecs.umich.edu 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 12935893Sgblack@eecs.umich.edu if (fault) 12945893Sgblack@eecs.umich.edu return fault; 12955893Sgblack@eecs.umich.edu Mem.udw = Fsr;}}); 12964008Ssaidi@eecs.umich.edu default: FailUnimpl::stfsrOther(); 12972526SN/A } 12982526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 12993272Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 13002526SN/A 0x2D: Nop::prefetch({{ }}); 13015096Sgblack@eecs.umich.edu 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 13022526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 13033272Sgblack@eecs.umich.edu format LoadAlt { 13043272Sgblack@eecs.umich.edu 0x33: decode EXT_ASI { 13057741Sgblack@eecs.umich.edu // ASI_NUCLEUS 13063272Sgblack@eecs.umich.edu 0x04: FailUnimpl::lddfa_n(); 13077741Sgblack@eecs.umich.edu // ASI_NUCLEUS_LITTLE 13083272Sgblack@eecs.umich.edu 0x0C: FailUnimpl::lddfa_nl(); 13097741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY 13103272Sgblack@eecs.umich.edu 0x10: FailUnimpl::lddfa_aiup(); 13117741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY_LITTLE 13123272Sgblack@eecs.umich.edu 0x18: FailUnimpl::lddfa_aiupl(); 13137741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY 13143272Sgblack@eecs.umich.edu 0x11: FailUnimpl::lddfa_aius(); 13157741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY_LITTLE 13163272Sgblack@eecs.umich.edu 0x19: FailUnimpl::lddfa_aiusl(); 13177741Sgblack@eecs.umich.edu // ASI_REAL 13183272Sgblack@eecs.umich.edu 0x14: FailUnimpl::lddfa_real(); 13197741Sgblack@eecs.umich.edu // ASI_REAL_LITTLE 13203272Sgblack@eecs.umich.edu 0x1C: FailUnimpl::lddfa_real_l(); 13217741Sgblack@eecs.umich.edu // ASI_REAL_IO 13223272Sgblack@eecs.umich.edu 0x15: FailUnimpl::lddfa_real_io(); 13237741Sgblack@eecs.umich.edu // ASI_REAL_IO_LITTLE 13243272Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 13257741Sgblack@eecs.umich.edu // ASI_PRIMARY 13263272Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 13277741Sgblack@eecs.umich.edu // ASI_PRIMARY_LITTLE 13283272Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 13297741Sgblack@eecs.umich.edu // ASI_SECONDARY 13303272Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 13317741Sgblack@eecs.umich.edu // ASI_SECONDARY_LITTLE 13323272Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 13337741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT 13343272Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 13357741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT_LITTLE 13363272Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 13377741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT 13383272Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 13397741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT_LITTLE 13403272Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 13413272Sgblack@eecs.umich.edu 13423272Sgblack@eecs.umich.edu format BlockLoad { 13433272Sgblack@eecs.umich.edu // LDBLOCKF 13447741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY 13453272Sgblack@eecs.umich.edu 0x16: FailUnimpl::ldblockf_aiup(); 13467741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY 13473272Sgblack@eecs.umich.edu 0x17: FailUnimpl::ldblockf_aius(); 13487741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 13493272Sgblack@eecs.umich.edu 0x1E: FailUnimpl::ldblockf_aiupl(); 13507741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 13513272Sgblack@eecs.umich.edu 0x1F: FailUnimpl::ldblockf_aiusl(); 13527741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY 13535096Sgblack@eecs.umich.edu 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 13547741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY 13553272Sgblack@eecs.umich.edu 0xF1: FailUnimpl::ldblockf_s(); 13567741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY_LITTLE 13573272Sgblack@eecs.umich.edu 0xF8: FailUnimpl::ldblockf_pl(); 13587741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY_LITTLE 13593272Sgblack@eecs.umich.edu 0xF9: FailUnimpl::ldblockf_sl(); 13603272Sgblack@eecs.umich.edu } 13613272Sgblack@eecs.umich.edu 13627741Sgblack@eecs.umich.edu // LDSHORTF 13637741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY 13643272Sgblack@eecs.umich.edu 0xD0: FailUnimpl::ldshortf_8p(); 13657741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY 13663272Sgblack@eecs.umich.edu 0xD1: FailUnimpl::ldshortf_8s(); 13677741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY_LITTLE 13683272Sgblack@eecs.umich.edu 0xD8: FailUnimpl::ldshortf_8pl(); 13697741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY_LITTLE 13703272Sgblack@eecs.umich.edu 0xD9: FailUnimpl::ldshortf_8sl(); 13717741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY 13723272Sgblack@eecs.umich.edu 0xD2: FailUnimpl::ldshortf_16p(); 13737741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY 13743272Sgblack@eecs.umich.edu 0xD3: FailUnimpl::ldshortf_16s(); 13757741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY_LITTLE 13763272Sgblack@eecs.umich.edu 0xDA: FailUnimpl::ldshortf_16pl(); 13777741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY_LITTLE 13783272Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 13797741Sgblack@eecs.umich.edu // Not an ASI which is legal with lddfa 13803378Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi( 13813378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 13823272Sgblack@eecs.umich.edu } 13833272Sgblack@eecs.umich.edu } 13843931Ssaidi@eecs.umich.edu 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 13852954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 13863378Sgblack@eecs.umich.edu format StoreAlt { 13873378Sgblack@eecs.umich.edu 0x37: decode EXT_ASI { 13887741Sgblack@eecs.umich.edu // ASI_NUCLEUS 13893378Sgblack@eecs.umich.edu 0x04: FailUnimpl::stdfa_n(); 13907741Sgblack@eecs.umich.edu // ASI_NUCLEUS_LITTLE 13913378Sgblack@eecs.umich.edu 0x0C: FailUnimpl::stdfa_nl(); 13927741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY 13933378Sgblack@eecs.umich.edu 0x10: FailUnimpl::stdfa_aiup(); 13947741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY_LITTLE 13953378Sgblack@eecs.umich.edu 0x18: FailUnimpl::stdfa_aiupl(); 13967741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY 13973378Sgblack@eecs.umich.edu 0x11: FailUnimpl::stdfa_aius(); 13987741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY_LITTLE 13993378Sgblack@eecs.umich.edu 0x19: FailUnimpl::stdfa_aiusl(); 14007741Sgblack@eecs.umich.edu // ASI_REAL 14013378Sgblack@eecs.umich.edu 0x14: FailUnimpl::stdfa_real(); 14027741Sgblack@eecs.umich.edu // ASI_REAL_LITTLE 14033378Sgblack@eecs.umich.edu 0x1C: FailUnimpl::stdfa_real_l(); 14047741Sgblack@eecs.umich.edu // ASI_REAL_IO 14053378Sgblack@eecs.umich.edu 0x15: FailUnimpl::stdfa_real_io(); 14067741Sgblack@eecs.umich.edu // ASI_REAL_IO_LITTLE 14073378Sgblack@eecs.umich.edu 0x1D: FailUnimpl::stdfa_real_io_l(); 14087741Sgblack@eecs.umich.edu // ASI_PRIMARY 14093378Sgblack@eecs.umich.edu 0x80: FailUnimpl::stdfa_p(); 14107741Sgblack@eecs.umich.edu // ASI_PRIMARY_LITTLE 14113378Sgblack@eecs.umich.edu 0x88: FailUnimpl::stdfa_pl(); 14127741Sgblack@eecs.umich.edu // ASI_SECONDARY 14133378Sgblack@eecs.umich.edu 0x81: FailUnimpl::stdfa_s(); 14147741Sgblack@eecs.umich.edu // ASI_SECONDARY_LITTLE 14153378Sgblack@eecs.umich.edu 0x89: FailUnimpl::stdfa_sl(); 14167741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT 14173378Sgblack@eecs.umich.edu 0x82: FailUnimpl::stdfa_pnf(); 14187741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT_LITTLE 14193378Sgblack@eecs.umich.edu 0x8A: FailUnimpl::stdfa_pnfl(); 14207741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT 14213378Sgblack@eecs.umich.edu 0x83: FailUnimpl::stdfa_snf(); 14227741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT_LITTLE 14233378Sgblack@eecs.umich.edu 0x8B: FailUnimpl::stdfa_snfl(); 14243378Sgblack@eecs.umich.edu 14253378Sgblack@eecs.umich.edu format BlockStore { 14263378Sgblack@eecs.umich.edu // STBLOCKF 14277741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY 14283378Sgblack@eecs.umich.edu 0x16: FailUnimpl::stblockf_aiup(); 14297741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY 14303378Sgblack@eecs.umich.edu 0x17: FailUnimpl::stblockf_aius(); 14317741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 14323378Sgblack@eecs.umich.edu 0x1E: FailUnimpl::stblockf_aiupl(); 14337741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 14343378Sgblack@eecs.umich.edu 0x1F: FailUnimpl::stblockf_aiusl(); 14357741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY 14365096Sgblack@eecs.umich.edu 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 14377741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY 14383378Sgblack@eecs.umich.edu 0xF1: FailUnimpl::stblockf_s(); 14397741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY_LITTLE 14403378Sgblack@eecs.umich.edu 0xF8: FailUnimpl::stblockf_pl(); 14417741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY_LITTLE 14423378Sgblack@eecs.umich.edu 0xF9: FailUnimpl::stblockf_sl(); 14433378Sgblack@eecs.umich.edu } 14443378Sgblack@eecs.umich.edu 14457741Sgblack@eecs.umich.edu // STSHORTF 14467741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY 14473378Sgblack@eecs.umich.edu 0xD0: FailUnimpl::stshortf_8p(); 14487741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY 14493378Sgblack@eecs.umich.edu 0xD1: FailUnimpl::stshortf_8s(); 14507741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY_LITTLE 14513378Sgblack@eecs.umich.edu 0xD8: FailUnimpl::stshortf_8pl(); 14527741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY_LITTLE 14533378Sgblack@eecs.umich.edu 0xD9: FailUnimpl::stshortf_8sl(); 14547741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY 14553378Sgblack@eecs.umich.edu 0xD2: FailUnimpl::stshortf_16p(); 14567741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY 14573378Sgblack@eecs.umich.edu 0xD3: FailUnimpl::stshortf_16s(); 14587741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY_LITTLE 14593378Sgblack@eecs.umich.edu 0xDA: FailUnimpl::stshortf_16pl(); 14607741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY_LITTLE 14613378Sgblack@eecs.umich.edu 0xDB: FailUnimpl::stshortf_16sl(); 14627741Sgblack@eecs.umich.edu // Not an ASI which is legal with lddfa 14633378Sgblack@eecs.umich.edu default: Trap::stdfa_bad_asi( 14643378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 14653378Sgblack@eecs.umich.edu } 14663378Sgblack@eecs.umich.edu } 14674040Ssaidi@eecs.umich.edu 0x3C: CasAlt::casa({{ 14684040Ssaidi@eecs.umich.edu mem_data = htog(Rs2.uw); 14694040Ssaidi@eecs.umich.edu Mem.uw = Rd.uw;}}, 14704040Ssaidi@eecs.umich.edu {{ 14714040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 14724040Ssaidi@eecs.umich.edu Rd.uw = tmp; 14735096Sgblack@eecs.umich.edu }}, MEM_SWAP_COND); 14742526SN/A 0x3D: Nop::prefetcha({{ }}); 14754040Ssaidi@eecs.umich.edu 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 14764040Ssaidi@eecs.umich.edu Mem.udw = Rd.udw; }}, 14775096Sgblack@eecs.umich.edu {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); 14782526SN/A } 14792469SN/A } 14802022SN/A} 1481