decoder.isa revision 7784
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 // Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 // bpcc 45 0x1: decode COND2 46 { 47 // Branch Always 48 0x8: bpa(19, annul_code={{ 49 SparcISA::PCState pc = PCS; 50 pc.npc(pc.pc() + disp); 51 pc.nnpc(pc.npc() + 4); 52 PCS = pc; 53 }}); 54 // Branch Never 55 0x0: bpn(19, {{;}}, 56 annul_code={{ 57 SparcISA::PCState pc = PCS; 58 pc.nnpc(pc.npc() + 8); 59 pc.npc(pc.npc() + 4); 60 PCS = pc; 61 }}); 62 default: decode BPCC 63 { 64 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 65 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 66 } 67 } 68 // bicc 69 0x2: decode COND2 70 { 71 // Branch Always 72 0x8: ba(22, annul_code={{ 73 SparcISA::PCState pc = PCS; 74 pc.npc(pc.pc() + disp); 75 pc.nnpc(pc.npc() + 4); 76 PCS = pc; 77 }}); 78 // Branch Never 79 0x0: bn(22, {{;}}, 80 annul_code={{ 81 SparcISA::PCState pc = PCS; 82 pc.nnpc(pc.npc() + 8); 83 pc.npc(pc.npc() + 4); 84 PCS = pc; 85 }}); 86 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 87 } 88 } 89 0x3: decode RCOND2 90 { 91 format BranchSplit 92 { 93 0x1: bpreq(test={{Rs1.sdw == 0}}); 94 0x2: bprle(test={{Rs1.sdw <= 0}}); 95 0x3: bprl(test={{Rs1.sdw < 0}}); 96 0x5: bprne(test={{Rs1.sdw != 0}}); 97 0x6: bprg(test={{Rs1.sdw > 0}}); 98 0x7: bprge(test={{Rs1.sdw >= 0}}); 99 } 100 } 101 // SETHI (or NOP if rd == 0 and imm == 0) 102 0x4: SetHi::sethi({{Rd.udw = imm;}}); 103 // fbpfcc 104 0x5: decode COND2 { 105 format BranchN { 106 // Branch Always 107 0x8: fbpa(22, annul_code={{ 108 SparcISA::PCState pc = PCS; 109 pc.npc(pc.pc() + disp); 110 pc.nnpc(pc.npc() + 4); 111 PCS = pc; 112 }}); 113 // Branch Never 114 0x0: fbpn(22, {{;}}, 115 annul_code={{ 116 SparcISA::PCState pc = PCS; 117 pc.nnpc(pc.npc() + 8); 118 pc.npc(pc.npc() + 4); 119 PCS = pc; 120 }}); 121 default: decode BPCC { 122 0x0: fbpfcc0(19, test= 123 {{passesFpCondition(Fsr<11:10>, COND2)}}); 124 0x1: fbpfcc1(19, test= 125 {{passesFpCondition(Fsr<33:32>, COND2)}}); 126 0x2: fbpfcc2(19, test= 127 {{passesFpCondition(Fsr<35:34>, COND2)}}); 128 0x3: fbpfcc3(19, test= 129 {{passesFpCondition(Fsr<37:36>, COND2)}}); 130 } 131 } 132 } 133 // fbfcc 134 0x6: decode COND2 { 135 format BranchN { 136 // Branch Always 137 0x8: fba(22, annul_code={{ 138 SparcISA::PCState pc = PCS; 139 pc.npc(pc.pc() + disp); 140 pc.nnpc(pc.npc() + 4); 141 PCS = pc; 142 }}); 143 // Branch Never 144 0x0: fbn(22, {{;}}, 145 annul_code={{ 146 SparcISA::PCState pc = PCS; 147 pc.nnpc(pc.npc() + 8); 148 pc.npc(pc.npc() + 4); 149 PCS = pc; 150 }}); 151 default: fbfcc(22, test= 152 {{passesFpCondition(Fsr<11:10>, COND2)}}); 153 } 154 } 155 } 156 0x1: BranchN::call(30, {{ 157 SparcISA::PCState pc = PCS; 158 if (Pstate<3:>) 159 R15 = (pc.pc())<31:0>; 160 else 161 R15 = pc.pc(); 162 pc.nnpc(R15 + disp); 163 PCS = pc; 164 }}); 165 0x2: decode OP3 { 166 format IntOp { 167 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 168 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 169 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 170 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 171 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 172 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 173 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 174 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 175 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 176 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 177 0x0A: umul({{ 178 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 179 Y = Rd<63:32>; 180 }}); 181 0x0B: smul({{ 182 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 183 Y = Rd.sdw<63:32>; 184 }}); 185 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 186 0x0D: udivx({{ 187 if (Rs2_or_imm13 == 0) 188 fault = new DivisionByZero; 189 else 190 Rd.udw = Rs1.udw / Rs2_or_imm13; 191 }}); 192 0x0E: udiv({{ 193 if (Rs2_or_imm13 == 0) { 194 fault = new DivisionByZero; 195 } else { 196 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 197 if (Rd.udw >> 32 != 0) 198 Rd.udw = 0xFFFFFFFF; 199 } 200 }}); 201 0x0F: sdiv({{ 202 if (Rs2_or_imm13.sdw == 0) { 203 fault = new DivisionByZero; 204 } else { 205 Rd.udw = ((int64_t)((Y << 32) | 206 Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 207 if ((int64_t)Rd.udw >= 208 std::numeric_limits<int32_t>::max()) { 209 Rd.udw = 0x7FFFFFFF; 210 } else if ((int64_t)Rd.udw <= 211 std::numeric_limits<int32_t>::min()) { 212 Rd.udw = ULL(0xFFFFFFFF80000000); 213 } 214 } 215 }}); 216 } 217 format IntOpCc { 218 0x10: addcc({{ 219 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 220 Rd = res = op1 + op2; 221 }}); 222 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 223 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 224 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 225 0x14: subcc({{ 226 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 227 Rd = res = op1 - op2; 228 }}, sub=True); 229 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 230 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 231 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 232 0x18: addccc({{ 233 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 234 Rd = res = op1 + op2 + Ccr<0:>; 235 }}); 236 0x1A: IntOpCcRes::umulcc({{ 237 uint64_t resTemp; 238 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 239 Y = resTemp<63:32>;}}); 240 0x1B: IntOpCcRes::smulcc({{ 241 int64_t resTemp; 242 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 243 Y = resTemp<63:32>;}}); 244 0x1C: subccc({{ 245 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 246 Rd = res = op1 - op2 - Ccr<0:>; 247 }}, sub=True); 248 0x1D: IntOpCcRes::udivxcc({{ 249 if (Rs2_or_imm13.udw == 0) 250 fault = new DivisionByZero; 251 else 252 Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 253 0x1E: IntOpCcRes::udivcc({{ 254 uint64_t resTemp; 255 uint32_t val2 = Rs2_or_imm13.udw; 256 int32_t overflow = 0; 257 if (val2 == 0) { 258 fault = new DivisionByZero; 259 } else { 260 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 261 overflow = (resTemp<63:32> != 0); 262 if (overflow) 263 Rd = resTemp = 0xFFFFFFFF; 264 else 265 Rd = resTemp; 266 } 267 }}, iv={{overflow}}); 268 0x1F: IntOpCcRes::sdivcc({{ 269 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 270 bool overflow = false, underflow = false; 271 if (val2 == 0) { 272 fault = new DivisionByZero; 273 } else { 274 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 275 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 276 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 277 if (overflow) 278 Rd = 0x7FFFFFFF; 279 else if (underflow) 280 Rd = ULL(0xFFFFFFFF80000000); 281 } 282 }}, iv={{overflow || underflow}}); 283 0x20: taddcc({{ 284 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 285 Rd = res = Rs1 + op2; 286 }}, iv={{ 287 (op1 & mask(2)) || (op2 & mask(2)) || 288 findOverflow(32, res, op1, op2) 289 }}); 290 0x21: tsubcc({{ 291 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 292 Rd = res = Rs1 - op2; 293 }}, iv={{ 294 (op1 & mask(2)) || (op2 & mask(2)) || 295 findOverflow(32, res, op1, ~op2) 296 }}, sub=True); 297 0x22: taddcctv({{ 298 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 299 Rd = res = op1 + op2; 300 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 301 findOverflow(32, res, op1, op2); 302 if (overflow) 303 fault = new TagOverflow; 304 }}, iv={{overflow}}); 305 0x23: tsubcctv({{ 306 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 307 Rd = res = op1 - op2; 308 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 309 findOverflow(32, res, op1, ~op2); 310 if (overflow) 311 fault = new TagOverflow; 312 }}, iv={{overflow}}, sub=True); 313 0x24: mulscc({{ 314 int32_t savedLSB = Rs1<0:>; 315 316 // Step 1 317 int64_t multiplicand = Rs2_or_imm13; 318 // Step 2 319 int32_t partialP = Rs1<31:1> | 320 ((Ccr<3:3> ^ Ccr<1:1>) << 31); 321 // Step 3 322 int32_t added = Y<0:> ? multiplicand : 0; 323 int64_t res, op1 = partialP, op2 = added; 324 Rd = res = partialP + added; 325 // Steps 4 & 5 326 Y = Y<31:1> | (savedLSB << 31); 327 }}); 328 } 329 format IntOp 330 { 331 0x25: decode X { 332 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 333 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 334 } 335 0x26: decode X { 336 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 337 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 338 } 339 0x27: decode X { 340 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 341 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 342 } 343 0x28: decode RS1 { 344 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 345 // 1 should cause an illegal instruction exception 346 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 347 0x03: NoPriv::rdasi({{Rd = Asi;}}); 348 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 349 0x05: NoPriv::rdpc({{ 350 SparcISA::PCState pc = PCS; 351 if (Pstate<3:>) 352 Rd = (pc.pc())<31:0>; 353 else 354 Rd = pc.pc(); 355 }}); 356 0x06: NoPriv::rdfprs({{ 357 // Wait for all fpops to finish. 358 Rd = Fprs; 359 }}); 360 // 7-14 should cause an illegal instruction exception 361 0x0F: decode I { 362 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 363 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 364 } 365 0x10: Priv::rdpcr({{Rd = Pcr;}}); 366 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 367 // 0x12 should cause an illegal instruction exception 368 0x13: NoPriv::rdgsr({{ 369 fault = checkFpEnableFault(xc); 370 if (fault) 371 return fault; 372 Rd = Gsr; 373 }}); 374 // 0x14-0x15 should cause an illegal instruction exception 375 0x16: Priv::rdsoftint({{Rd = Softint;}}); 376 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 377 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 378 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 379 0x1A: Priv::rdstrand_sts_reg({{ 380 if (Pstate<2:> && !Hpstate<2:>) 381 Rd = StrandStsReg<0:>; 382 else 383 Rd = StrandStsReg; 384 }}); 385 // 0x1A is supposed to be reserved, but it reads the strand 386 // status register. 387 // 0x1B-0x1F should cause an illegal instruction exception 388 } 389 0x29: decode RS1 { 390 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 391 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 392 // 0x02 should cause an illegal instruction exception 393 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 394 // 0x04 should cause an illegal instruction exception 395 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 396 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 397 // 0x07-0x1E should cause an illegal instruction exception 398 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 399 } 400 0x2A: decode RS1 { 401 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 402 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 403 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 404 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 405 0x04: Priv::rdprtick({{Rd = Tick;}}); 406 0x05: Priv::rdprtba({{Rd = Tba;}}); 407 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 408 0x07: Priv::rdprtl({{Rd = Tl;}}); 409 0x08: Priv::rdprpil({{Rd = Pil;}}); 410 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 411 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 412 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 413 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 414 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 415 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 416 // 0x0F should cause an illegal instruction exception 417 0x10: Priv::rdprgl({{Rd = Gl;}}); 418 // 0x11-0x1F should cause an illegal instruction exception 419 } 420 0x2B: BasicOperate::flushw({{ 421 if (NWindows - 2 - Cansave != 0) { 422 if (Otherwin) 423 fault = new SpillNOther(4*Wstate<5:3>); 424 else 425 fault = new SpillNNormal(4*Wstate<2:0>); 426 } 427 }}); 428 0x2C: decode MOVCC3 429 { 430 0x0: decode CC 431 { 432 0x0: movccfcc0({{ 433 if (passesCondition(Fsr<11:10>, COND4)) 434 Rd = Rs2_or_imm11; 435 else 436 Rd = Rd; 437 }}); 438 0x1: movccfcc1({{ 439 if (passesCondition(Fsr<33:32>, COND4)) 440 Rd = Rs2_or_imm11; 441 else 442 Rd = Rd; 443 }}); 444 0x2: movccfcc2({{ 445 if (passesCondition(Fsr<35:34>, COND4)) 446 Rd = Rs2_or_imm11; 447 else 448 Rd = Rd; 449 }}); 450 0x3: movccfcc3({{ 451 if (passesCondition(Fsr<37:36>, COND4)) 452 Rd = Rs2_or_imm11; 453 else 454 Rd = Rd; 455 }}); 456 } 457 0x1: decode CC 458 { 459 0x0: movcci({{ 460 if (passesCondition(Ccr<3:0>, COND4)) 461 Rd = Rs2_or_imm11; 462 else 463 Rd = Rd; 464 }}); 465 0x2: movccx({{ 466 if (passesCondition(Ccr<7:4>, COND4)) 467 Rd = Rs2_or_imm11; 468 else 469 Rd = Rd; 470 }}); 471 } 472 } 473 0x2D: sdivx({{ 474 if (Rs2_or_imm13.sdw == 0) 475 fault = new DivisionByZero; 476 else 477 Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 478 }}); 479 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 480 0x2F: decode RCOND3 481 { 482 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 483 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 484 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 485 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 486 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 487 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 488 } 489 0x30: decode RD { 490 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 491 // 0x01 should cause an illegal instruction exception 492 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 493 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false, 494 IsSquashAfter); 495 // 0x04-0x05 should cause an illegal instruction exception 496 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 497 // 0x07-0x0E should cause an illegal instruction exception 498 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 499 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 500 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 501 // 0x12 should cause an illegal instruction exception 502 0x13: NoPriv::wrgsr({{ 503 if (Fprs<2:> == 0 || Pstate<4:> == 0) 504 return new FpDisabled; 505 Gsr = Rs1 ^ Rs2_or_imm13; 506 }}); 507 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 508 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 509 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 510 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 511 0x18: NoPriv::wrstick({{ 512 if (!Hpstate<2:>) 513 return new IllegalInstruction; 514 Stick = Rs1 ^ Rs2_or_imm13; 515 }}); 516 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 517 0x1A: Priv::wrstrand_sts_reg({{ 518 StrandStsReg = Rs1 ^ Rs2_or_imm13; 519 }}); 520 // 0x1A is supposed to be reserved, but it writes the strand 521 // status register. 522 // 0x1B-0x1F should cause an illegal instruction exception 523 } 524 0x31: decode FCN { 525 0x0: Priv::saved({{ 526 assert(Cansave < NWindows - 2); 527 assert(Otherwin || Canrestore); 528 Cansave = Cansave + 1; 529 if (Otherwin == 0) 530 Canrestore = Canrestore - 1; 531 else 532 Otherwin = Otherwin - 1; 533 }}); 534 0x1: Priv::restored({{ 535 assert(Cansave || Otherwin); 536 assert(Canrestore < NWindows - 2); 537 Canrestore = Canrestore + 1; 538 if (Otherwin == 0) 539 Cansave = Cansave - 1; 540 else 541 Otherwin = Otherwin - 1; 542 543 if (Cleanwin < NWindows - 1) 544 Cleanwin = Cleanwin + 1; 545 }}); 546 } 547 0x32: decode RD { 548 0x00: Priv::wrprtpc( 549 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 550 0x01: Priv::wrprtnpc( 551 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 552 0x02: Priv::wrprtstate( 553 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 554 0x03: Priv::wrprtt( 555 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 556 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 557 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 558 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 559 0x07: Priv::wrprtl({{ 560 if (Pstate<2:> && !Hpstate<2:>) 561 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 562 else 563 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 564 }}); 565 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 566 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 567 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 568 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 569 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 570 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 571 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 572 // 0x0F should cause an illegal instruction exception 573 0x10: Priv::wrprgl({{ 574 if (Pstate<2:> && !Hpstate<2:>) 575 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 576 else 577 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 578 }}); 579 // 0x11-0x1F should cause an illegal instruction exception 580 } 581 0x33: decode RD { 582 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 583 0x01: HPriv::wrhprhtstate( 584 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 585 // 0x02 should cause an illegal instruction exception 586 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 587 // 0x04 should cause an illegal instruction exception 588 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 589 // 0x06-0x01D should cause an illegal instruction exception 590 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 591 } 592 0x34: decode OPF{ 593 format FpBasic{ 594 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 595 0x02: fmovd({{Frd.udw = Frs2.udw;}}); 596 0x03: FpUnimpl::fmovq(); 597 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 598 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 599 0x07: FpUnimpl::fnegq(); 600 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 601 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 602 0x0B: FpUnimpl::fabsq(); 603 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 604 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 605 0x2B: FpUnimpl::fsqrtq(); 606 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 607 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 608 0x43: FpUnimpl::faddq(); 609 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 610 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 611 0x47: FpUnimpl::fsubq(); 612 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 613 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 614 0x4B: FpUnimpl::fmulq(); 615 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 616 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 617 0x4F: FpUnimpl::fdivq(); 618 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 619 0x6E: FpUnimpl::fdmulq(); 620 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 621 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 622 0x83: FpUnimpl::fqtox(); 623 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 624 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 625 0x8C: FpUnimpl::fxtoq(); 626 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 627 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 628 0xC7: FpUnimpl::fqtos(); 629 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 630 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 631 0xCB: FpUnimpl::fqtod(); 632 0xCC: FpUnimpl::fitoq(); 633 0xCD: FpUnimpl::fstoq(); 634 0xCE: FpUnimpl::fdtoq(); 635 0xD1: fstoi({{ 636 Frds.sw = static_cast<int32_t>(Frs2s.sf); 637 float t = Frds.sw; 638 if (t != Frs2s.sf) 639 Fsr = insertBits(Fsr, 4,0, 0x01); 640 }}); 641 0xD2: fdtoi({{ 642 Frds.sw = static_cast<int32_t>(Frs2.df); 643 double t = Frds.sw; 644 if (t != Frs2.df) 645 Fsr = insertBits(Fsr, 4,0, 0x01); 646 }}); 647 0xD3: FpUnimpl::fqtoi(); 648 default: FailUnimpl::fpop1(); 649 } 650 } 651 0x35: decode OPF{ 652 format FpBasic{ 653 0x01: fmovs_fcc0({{ 654 if (passesFpCondition(Fsr<11:10>, COND4)) 655 Frds = Frs2s; 656 else 657 Frds = Frds; 658 }}); 659 0x02: fmovd_fcc0({{ 660 if (passesFpCondition(Fsr<11:10>, COND4)) 661 Frd = Frs2; 662 else 663 Frd = Frd; 664 }}); 665 0x03: FpUnimpl::fmovq_fcc0(); 666 0x25: fmovrsz({{ 667 if (Rs1 == 0) 668 Frds = Frs2s; 669 else 670 Frds = Frds; 671 }}); 672 0x26: fmovrdz({{ 673 if (Rs1 == 0) 674 Frd = Frs2; 675 else 676 Frd = Frd; 677 }}); 678 0x27: FpUnimpl::fmovrqz(); 679 0x41: fmovs_fcc1({{ 680 if (passesFpCondition(Fsr<33:32>, COND4)) 681 Frds = Frs2s; 682 else 683 Frds = Frds; 684 }}); 685 0x42: fmovd_fcc1({{ 686 if (passesFpCondition(Fsr<33:32>, COND4)) 687 Frd = Frs2; 688 else 689 Frd = Frd; 690 }}); 691 0x43: FpUnimpl::fmovq_fcc1(); 692 0x45: fmovrslez({{ 693 if (Rs1 <= 0) 694 Frds = Frs2s; 695 else 696 Frds = Frds; 697 }}); 698 0x46: fmovrdlez({{ 699 if (Rs1 <= 0) 700 Frd = Frs2; 701 else 702 Frd = Frd; 703 }}); 704 0x47: FpUnimpl::fmovrqlez(); 705 0x51: fcmps({{ 706 uint8_t fcc; 707 if (isnan(Frs1s) || isnan(Frs2s)) 708 fcc = 3; 709 else if (Frs1s < Frs2s) 710 fcc = 1; 711 else if (Frs1s > Frs2s) 712 fcc = 2; 713 else 714 fcc = 0; 715 uint8_t firstbit = 10; 716 if (FCMPCC) 717 firstbit = FCMPCC * 2 + 30; 718 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 719 }}); 720 0x52: fcmpd({{ 721 uint8_t fcc; 722 if (isnan(Frs1) || isnan(Frs2)) 723 fcc = 3; 724 else if (Frs1 < Frs2) 725 fcc = 1; 726 else if (Frs1 > Frs2) 727 fcc = 2; 728 else 729 fcc = 0; 730 uint8_t firstbit = 10; 731 if (FCMPCC) 732 firstbit = FCMPCC * 2 + 30; 733 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 734 }}); 735 0x53: FpUnimpl::fcmpq(); 736 0x55: fcmpes({{ 737 uint8_t fcc = 0; 738 if (isnan(Frs1s) || isnan(Frs2s)) 739 fault = new FpExceptionIEEE754; 740 if (Frs1s < Frs2s) 741 fcc = 1; 742 else if (Frs1s > Frs2s) 743 fcc = 2; 744 uint8_t firstbit = 10; 745 if (FCMPCC) 746 firstbit = FCMPCC * 2 + 30; 747 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 748 }}); 749 0x56: fcmped({{ 750 uint8_t fcc = 0; 751 if (isnan(Frs1) || isnan(Frs2)) 752 fault = new FpExceptionIEEE754; 753 if (Frs1 < Frs2) 754 fcc = 1; 755 else if (Frs1 > Frs2) 756 fcc = 2; 757 uint8_t firstbit = 10; 758 if (FCMPCC) 759 firstbit = FCMPCC * 2 + 30; 760 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 761 }}); 762 0x57: FpUnimpl::fcmpeq(); 763 0x65: fmovrslz({{ 764 if (Rs1 < 0) 765 Frds = Frs2s; 766 else 767 Frds = Frds; 768 }}); 769 0x66: fmovrdlz({{ 770 if (Rs1 < 0) 771 Frd = Frs2; 772 else 773 Frd = Frd; 774 }}); 775 0x67: FpUnimpl::fmovrqlz(); 776 0x81: fmovs_fcc2({{ 777 if (passesFpCondition(Fsr<35:34>, COND4)) 778 Frds = Frs2s; 779 else 780 Frds = Frds; 781 }}); 782 0x82: fmovd_fcc2({{ 783 if (passesFpCondition(Fsr<35:34>, COND4)) 784 Frd = Frs2; 785 else 786 Frd = Frd; 787 }}); 788 0x83: FpUnimpl::fmovq_fcc2(); 789 0xA5: fmovrsnz({{ 790 if (Rs1 != 0) 791 Frds = Frs2s; 792 else 793 Frds = Frds; 794 }}); 795 0xA6: fmovrdnz({{ 796 if (Rs1 != 0) 797 Frd = Frs2; 798 else 799 Frd = Frd; 800 }}); 801 0xA7: FpUnimpl::fmovrqnz(); 802 0xC1: fmovs_fcc3({{ 803 if (passesFpCondition(Fsr<37:36>, COND4)) 804 Frds = Frs2s; 805 else 806 Frds = Frds; 807 }}); 808 0xC2: fmovd_fcc3({{ 809 if (passesFpCondition(Fsr<37:36>, COND4)) 810 Frd = Frs2; 811 else 812 Frd = Frd; 813 }}); 814 0xC3: FpUnimpl::fmovq_fcc3(); 815 0xC5: fmovrsgz({{ 816 if (Rs1 > 0) 817 Frds = Frs2s; 818 else 819 Frds = Frds; 820 }}); 821 0xC6: fmovrdgz({{ 822 if (Rs1 > 0) 823 Frd = Frs2; 824 else 825 Frd = Frd; 826 }}); 827 0xC7: FpUnimpl::fmovrqgz(); 828 0xE5: fmovrsgez({{ 829 if (Rs1 >= 0) 830 Frds = Frs2s; 831 else 832 Frds = Frds; 833 }}); 834 0xE6: fmovrdgez({{ 835 if (Rs1 >= 0) 836 Frd = Frs2; 837 else 838 Frd = Frd; 839 }}); 840 0xE7: FpUnimpl::fmovrqgez(); 841 0x101: fmovs_icc({{ 842 if (passesCondition(Ccr<3:0>, COND4)) 843 Frds = Frs2s; 844 else 845 Frds = Frds; 846 }}); 847 0x102: fmovd_icc({{ 848 if (passesCondition(Ccr<3:0>, COND4)) 849 Frd = Frs2; 850 else 851 Frd = Frd; 852 }}); 853 0x103: FpUnimpl::fmovq_icc(); 854 0x181: fmovs_xcc({{ 855 if (passesCondition(Ccr<7:4>, COND4)) 856 Frds = Frs2s; 857 else 858 Frds = Frds; 859 }}); 860 0x182: fmovd_xcc({{ 861 if (passesCondition(Ccr<7:4>, COND4)) 862 Frd = Frs2; 863 else 864 Frd = Frd; 865 }}); 866 0x183: FpUnimpl::fmovq_xcc(); 867 default: FailUnimpl::fpop2(); 868 } 869 } 870 // This used to be just impdep1, but now it's a whole bunch 871 // of instructions 872 0x36: decode OPF{ 873 0x00: FailUnimpl::edge8(); 874 0x01: FailUnimpl::edge8n(); 875 0x02: FailUnimpl::edge8l(); 876 0x03: FailUnimpl::edge8ln(); 877 0x04: FailUnimpl::edge16(); 878 0x05: FailUnimpl::edge16n(); 879 0x06: FailUnimpl::edge16l(); 880 0x07: FailUnimpl::edge16ln(); 881 0x08: FailUnimpl::edge32(); 882 0x09: FailUnimpl::edge32n(); 883 0x0A: FailUnimpl::edge32l(); 884 0x0B: FailUnimpl::edge32ln(); 885 0x10: FailUnimpl::array8(); 886 0x12: FailUnimpl::array16(); 887 0x14: FailUnimpl::array32(); 888 0x18: BasicOperate::alignaddr({{ 889 uint64_t sum = Rs1 + Rs2; 890 Rd = sum & ~7; 891 Gsr = (Gsr & ~7) | (sum & 7); 892 }}); 893 0x19: FailUnimpl::bmask(); 894 0x1A: BasicOperate::alignaddresslittle({{ 895 uint64_t sum = Rs1 + Rs2; 896 Rd = sum & ~7; 897 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 898 }}); 899 0x20: FailUnimpl::fcmple16(); 900 0x22: FailUnimpl::fcmpne16(); 901 0x24: FailUnimpl::fcmple32(); 902 0x26: FailUnimpl::fcmpne32(); 903 0x28: FailUnimpl::fcmpgt16(); 904 0x2A: FailUnimpl::fcmpeq16(); 905 0x2C: FailUnimpl::fcmpgt32(); 906 0x2E: FailUnimpl::fcmpeq32(); 907 0x31: FailUnimpl::fmul8x16(); 908 0x33: FailUnimpl::fmul8x16au(); 909 0x35: FailUnimpl::fmul8x16al(); 910 0x36: FailUnimpl::fmul8sux16(); 911 0x37: FailUnimpl::fmul8ulx16(); 912 0x38: FailUnimpl::fmuld8sux16(); 913 0x39: FailUnimpl::fmuld8ulx16(); 914 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 915 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 916 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 917 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 918 0x48: BasicOperate::faligndata({{ 919 uint64_t msbX = Frs1.udw; 920 uint64_t lsbX = Frs2.udw; 921 // Some special cases need to be split out, first 922 // because they're the most likely to be used, and 923 // second because otherwise, we end up shifting by 924 // greater than the width of the type being shifted, 925 // namely 64, which produces undefined results 926 // according to the C standard. 927 switch (Gsr<2:0>) { 928 case 0: 929 Frd.udw = msbX; 930 break; 931 case 8: 932 Frd.udw = lsbX; 933 break; 934 default: 935 uint64_t msbShift = Gsr<2:0> * 8; 936 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 937 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 938 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 939 Frd.udw = ((msbX & msbMask) << msbShift) | 940 ((lsbX & lsbMask) >> lsbShift); 941 } 942 }}); 943 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 944 0x4C: FailUnimpl::bshuffle(); 945 0x4D: FailUnimpl::fexpand(); 946 0x50: FailUnimpl::fpadd16(); 947 0x51: FailUnimpl::fpadd16s(); 948 0x52: FailUnimpl::fpadd32(); 949 0x53: FailUnimpl::fpadd32s(); 950 0x54: FailUnimpl::fpsub16(); 951 0x55: FailUnimpl::fpsub16s(); 952 0x56: FailUnimpl::fpsub32(); 953 0x57: FailUnimpl::fpsub32s(); 954 0x60: FpBasic::fzero({{Frd.df = 0;}}); 955 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 956 0x62: FailUnimpl::fnor(); 957 0x63: FailUnimpl::fnors(); 958 0x64: FailUnimpl::fandnot2(); 959 0x65: FailUnimpl::fandnot2s(); 960 0x66: FpBasic::fnot2({{ 961 Frd.df = (double)(~((uint64_t)Frs2.df)); 962 }}); 963 0x67: FpBasic::fnot2s({{ 964 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 965 }}); 966 0x68: FailUnimpl::fandnot1(); 967 0x69: FailUnimpl::fandnot1s(); 968 0x6A: FpBasic::fnot1({{ 969 Frd.df = (double)(~((uint64_t)Frs1.df)); 970 }}); 971 0x6B: FpBasic::fnot1s({{ 972 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 973 }}); 974 0x6C: FailUnimpl::fxor(); 975 0x6D: FailUnimpl::fxors(); 976 0x6E: FailUnimpl::fnand(); 977 0x6F: FailUnimpl::fnands(); 978 0x70: FailUnimpl::fand(); 979 0x71: FailUnimpl::fands(); 980 0x72: FailUnimpl::fxnor(); 981 0x73: FailUnimpl::fxnors(); 982 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 983 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 984 0x76: FailUnimpl::fornot2(); 985 0x77: FailUnimpl::fornot2s(); 986 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 987 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 988 0x7A: FailUnimpl::fornot1(); 989 0x7B: FailUnimpl::fornot1s(); 990 0x7C: FailUnimpl::for(); 991 0x7D: FailUnimpl::fors(); 992 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 993 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 994 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 995 0x81: FailUnimpl::siam(); 996 } 997 // M5 special opcodes use the reserved IMPDEP2A opcode space 998 0x37: decode M5FUNC { 999#if FULL_SYSTEM 1000 format BasicOperate { 1001 // we have 7 bits of space here to play with... 1002 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 1003 }}, No_OpClass, IsNonSpeculative); 1004 0x50: m5readfile({{ 1005 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 1006 }}, IsNonSpeculative); 1007 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 1008 }}, IsNonSpeculative); 1009 0x54: m5panic({{ 1010 SparcISA::PCState pc = PCS; 1011 panic("M5 panic instruction called at pc=%#x.", pc.pc()); 1012 }}, No_OpClass, IsNonSpeculative); 1013 } 1014#endif 1015 default: Trap::impdep2({{fault = new IllegalInstruction;}}); 1016 } 1017 0x38: Branch::jmpl({{ 1018 Addr target = Rs1 + Rs2_or_imm13; 1019 if (target & 0x3) { 1020 fault = new MemAddressNotAligned; 1021 } else { 1022 SparcISA::PCState pc = PCS; 1023 if (Pstate<3:>) 1024 Rd = (pc.pc())<31:0>; 1025 else 1026 Rd = pc.pc(); 1027 pc.nnpc(target); 1028 PCS = pc; 1029 } 1030 }}); 1031 0x39: Branch::return({{ 1032 Addr target = Rs1 + Rs2_or_imm13; 1033 if (fault == NoFault) { 1034 // Check for fills which are higher priority than alignment 1035 // faults. 1036 if (Canrestore == 0) { 1037 if (Otherwin) 1038 fault = new FillNOther(4*Wstate<5:3>); 1039 else 1040 fault = new FillNNormal(4*Wstate<2:0>); 1041 } else if (target & 0x3) { // Check for alignment faults 1042 fault = new MemAddressNotAligned; 1043 } else { 1044 SparcISA::PCState pc = PCS; 1045 pc.nnpc(target); 1046 PCS = pc; 1047 Cwp = (Cwp - 1 + NWindows) % NWindows; 1048 Cansave = Cansave + 1; 1049 Canrestore = Canrestore - 1; 1050 } 1051 } 1052 }}); 1053 0x3A: decode CC 1054 { 1055 0x0: Trap::tcci({{ 1056 if (passesCondition(Ccr<3:0>, COND2)) { 1057 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1058 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1059 fault = new TrapInstruction(lTrapNum); 1060 } 1061 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1062 0x2: Trap::tccx({{ 1063 if (passesCondition(Ccr<7:4>, COND2)) { 1064 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1065 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1066 fault = new TrapInstruction(lTrapNum); 1067 } 1068 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1069 } 1070 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 1071 MemWriteOp); 1072 0x3C: save({{ 1073 if (Cansave == 0) { 1074 if (Otherwin) 1075 fault = new SpillNOther(4*Wstate<5:3>); 1076 else 1077 fault = new SpillNNormal(4*Wstate<2:0>); 1078 } else if (Cleanwin - Canrestore == 0) { 1079 fault = new CleanWindow; 1080 } else { 1081 Cwp = (Cwp + 1) % NWindows; 1082 Rd_next = Rs1 + Rs2_or_imm13; 1083 Cansave = Cansave - 1; 1084 Canrestore = Canrestore + 1; 1085 } 1086 }}); 1087 0x3D: restore({{ 1088 if (Canrestore == 0) { 1089 if (Otherwin) 1090 fault = new FillNOther(4*Wstate<5:3>); 1091 else 1092 fault = new FillNNormal(4*Wstate<2:0>); 1093 } else { 1094 Cwp = (Cwp - 1 + NWindows) % NWindows; 1095 Rd_prev = Rs1 + Rs2_or_imm13; 1096 Cansave = Cansave + 1; 1097 Canrestore = Canrestore - 1; 1098 } 1099 }}); 1100 0x3E: decode FCN { 1101 0x0: Priv::done({{ 1102 Cwp = Tstate<4:0>; 1103 Pstate = Tstate<20:8>; 1104 Asi = Tstate<31:24>; 1105 Ccr = Tstate<39:32>; 1106 Gl = Tstate<42:40>; 1107 Hpstate = Htstate; 1108 SparcISA::PCState pc = PCS; 1109 pc.npc(Tnpc); 1110 pc.nnpc(Tnpc + 4); 1111 PCS = pc; 1112 Tl = Tl - 1; 1113 }}, checkTl=true); 1114 0x1: Priv::retry({{ 1115 Cwp = Tstate<4:0>; 1116 Pstate = Tstate<20:8>; 1117 Asi = Tstate<31:24>; 1118 Ccr = Tstate<39:32>; 1119 Gl = Tstate<42:40>; 1120 Hpstate = Htstate; 1121 SparcISA::PCState pc = PCS; 1122 pc.npc(Tpc); 1123 pc.nnpc(Tnpc); 1124 PCS = pc; 1125 Tl = Tl - 1; 1126 }}, checkTl=true); 1127 } 1128 } 1129 } 1130 0x3: decode OP3 { 1131 format Load { 1132 0x00: lduw({{Rd = Mem.uw;}}); 1133 0x01: ldub({{Rd = Mem.ub;}}); 1134 0x02: lduh({{Rd = Mem.uhw;}}); 1135 0x03: ldtw({{ 1136 RdLow = (Mem.tuw).a; 1137 RdHigh = (Mem.tuw).b; 1138 }}); 1139 } 1140 format Store { 1141 0x04: stw({{Mem.uw = Rd.sw;}}); 1142 0x05: stb({{Mem.ub = Rd.sb;}}); 1143 0x06: sth({{Mem.uhw = Rd.shw;}}); 1144 0x07: sttw({{ 1145 // This temporary needs to be here so that the parser 1146 // will correctly identify this instruction as a store. 1147 // It's probably either the parenthesis or referencing 1148 // the member variable that throws confuses it. 1149 Twin32_t temp; 1150 temp.a = RdLow<31:0>; 1151 temp.b = RdHigh<31:0>; 1152 Mem.tuw = temp; 1153 }}); 1154 } 1155 format Load { 1156 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1157 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1158 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1159 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1160 } 1161 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 1162 {{ 1163 uint8_t tmp = mem_data; 1164 Rd.ub = tmp; 1165 }}, MEM_SWAP); 1166 0x0E: Store::stx({{Mem.udw = Rd}}); 1167 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 1168 {{ 1169 uint32_t tmp = mem_data; 1170 Rd.uw = tmp; 1171 }}, MEM_SWAP); 1172 format LoadAlt { 1173 0x10: lduwa({{Rd = Mem.uw;}}); 1174 0x11: lduba({{Rd = Mem.ub;}}); 1175 0x12: lduha({{Rd = Mem.uhw;}}); 1176 0x13: decode EXT_ASI { 1177 // ASI_LDTD_AIUP 1178 0x22: TwinLoad::ldtx_aiup( 1179 {{RdLow.udw = (Mem.tudw).a; 1180 RdHigh.udw = (Mem.tudw).b;}}); 1181 // ASI_LDTD_AIUS 1182 0x23: TwinLoad::ldtx_aius( 1183 {{RdLow.udw = (Mem.tudw).a; 1184 RdHigh.udw = (Mem.tudw).b;}}); 1185 // ASI_QUAD_LDD 1186 0x24: TwinLoad::ldtx_quad_ldd( 1187 {{RdLow.udw = (Mem.tudw).a; 1188 RdHigh.udw = (Mem.tudw).b;}}); 1189 // ASI_LDTX_REAL 1190 0x26: TwinLoad::ldtx_real( 1191 {{RdLow.udw = (Mem.tudw).a; 1192 RdHigh.udw = (Mem.tudw).b;}}); 1193 // ASI_LDTX_N 1194 0x27: TwinLoad::ldtx_n( 1195 {{RdLow.udw = (Mem.tudw).a; 1196 RdHigh.udw = (Mem.tudw).b;}}); 1197 // ASI_LDTX_AIUP_L 1198 0x2A: TwinLoad::ldtx_aiup_l( 1199 {{RdLow.udw = (Mem.tudw).a; 1200 RdHigh.udw = (Mem.tudw).b;}}); 1201 // ASI_LDTX_AIUS_L 1202 0x2B: TwinLoad::ldtx_aius_l( 1203 {{RdLow.udw = (Mem.tudw).a; 1204 RdHigh.udw = (Mem.tudw).b;}}); 1205 // ASI_LDTX_L 1206 0x2C: TwinLoad::ldtx_l( 1207 {{RdLow.udw = (Mem.tudw).a; 1208 RdHigh.udw = (Mem.tudw).b;}}); 1209 // ASI_LDTX_REAL_L 1210 0x2E: TwinLoad::ldtx_real_l( 1211 {{RdLow.udw = (Mem.tudw).a; 1212 RdHigh.udw = (Mem.tudw).b;}}); 1213 // ASI_LDTX_N_L 1214 0x2F: TwinLoad::ldtx_n_l( 1215 {{RdLow.udw = (Mem.tudw).a; 1216 RdHigh.udw = (Mem.tudw).b;}}); 1217 // ASI_LDTX_P 1218 0xE2: TwinLoad::ldtx_p( 1219 {{RdLow.udw = (Mem.tudw).a; 1220 RdHigh.udw = (Mem.tudw).b;}}); 1221 // ASI_LDTX_S 1222 0xE3: TwinLoad::ldtx_s( 1223 {{RdLow.udw = (Mem.tudw).a; 1224 RdHigh.udw = (Mem.tudw).b;}}); 1225 // ASI_LDTX_PL 1226 0xEA: TwinLoad::ldtx_pl( 1227 {{RdLow.udw = (Mem.tudw).a; 1228 RdHigh.udw = (Mem.tudw).b;}}); 1229 // ASI_LDTX_SL 1230 0xEB: TwinLoad::ldtx_sl( 1231 {{RdLow.udw = (Mem.tudw).a; 1232 RdHigh.udw = (Mem.tudw).b;}}); 1233 default: ldtwa({{ 1234 RdLow = (Mem.tuw).a; 1235 RdHigh = (Mem.tuw).b;}}); 1236 } 1237 } 1238 format StoreAlt { 1239 0x14: stwa({{Mem.uw = Rd;}}); 1240 0x15: stba({{Mem.ub = Rd;}}); 1241 0x16: stha({{Mem.uhw = Rd;}}); 1242 0x17: sttwa({{ 1243 // This temporary needs to be here so that the parser 1244 // will correctly identify this instruction as a store. 1245 // It's probably either the parenthesis or referencing 1246 // the member variable that throws confuses it. 1247 Twin32_t temp; 1248 temp.a = RdLow<31:0>; 1249 temp.b = RdHigh<31:0>; 1250 Mem.tuw = temp; 1251 }}); 1252 } 1253 format LoadAlt { 1254 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 1255 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 1256 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 1257 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 1258 } 1259 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 1260 {{ 1261 uint8_t tmp = mem_data; 1262 Rd.ub = tmp; 1263 }}, MEM_SWAP); 1264 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 1265 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 1266 {{ 1267 uint32_t tmp = mem_data; 1268 Rd.uw = tmp; 1269 }}, MEM_SWAP); 1270 1271 format Trap { 1272 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1273 0x21: decode RD { 1274 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1275 if (fault) 1276 return fault; 1277 Fsr = Mem.uw | Fsr<63:32>;}}); 1278 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1279 if (fault) 1280 return fault; 1281 Fsr = Mem.udw;}}); 1282 default: FailUnimpl::ldfsrOther(); 1283 } 1284 0x22: ldqf({{fault = new FpDisabled;}}); 1285 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1286 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1287 0x25: decode RD { 1288 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 1289 if (fault) 1290 return fault; 1291 Mem.uw = Fsr<31:0>;}}); 1292 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 1293 if (fault) 1294 return fault; 1295 Mem.udw = Fsr;}}); 1296 default: FailUnimpl::stfsrOther(); 1297 } 1298 0x26: stqf({{fault = new FpDisabled;}}); 1299 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1300 0x2D: Nop::prefetch({{ }}); 1301 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 1302 0x32: ldqfa({{fault = new FpDisabled;}}); 1303 format LoadAlt { 1304 0x33: decode EXT_ASI { 1305 // ASI_NUCLEUS 1306 0x04: FailUnimpl::lddfa_n(); 1307 // ASI_NUCLEUS_LITTLE 1308 0x0C: FailUnimpl::lddfa_nl(); 1309 // ASI_AS_IF_USER_PRIMARY 1310 0x10: FailUnimpl::lddfa_aiup(); 1311 // ASI_AS_IF_USER_PRIMARY_LITTLE 1312 0x18: FailUnimpl::lddfa_aiupl(); 1313 // ASI_AS_IF_USER_SECONDARY 1314 0x11: FailUnimpl::lddfa_aius(); 1315 // ASI_AS_IF_USER_SECONDARY_LITTLE 1316 0x19: FailUnimpl::lddfa_aiusl(); 1317 // ASI_REAL 1318 0x14: FailUnimpl::lddfa_real(); 1319 // ASI_REAL_LITTLE 1320 0x1C: FailUnimpl::lddfa_real_l(); 1321 // ASI_REAL_IO 1322 0x15: FailUnimpl::lddfa_real_io(); 1323 // ASI_REAL_IO_LITTLE 1324 0x1D: FailUnimpl::lddfa_real_io_l(); 1325 // ASI_PRIMARY 1326 0x80: FailUnimpl::lddfa_p(); 1327 // ASI_PRIMARY_LITTLE 1328 0x88: FailUnimpl::lddfa_pl(); 1329 // ASI_SECONDARY 1330 0x81: FailUnimpl::lddfa_s(); 1331 // ASI_SECONDARY_LITTLE 1332 0x89: FailUnimpl::lddfa_sl(); 1333 // ASI_PRIMARY_NO_FAULT 1334 0x82: FailUnimpl::lddfa_pnf(); 1335 // ASI_PRIMARY_NO_FAULT_LITTLE 1336 0x8A: FailUnimpl::lddfa_pnfl(); 1337 // ASI_SECONDARY_NO_FAULT 1338 0x83: FailUnimpl::lddfa_snf(); 1339 // ASI_SECONDARY_NO_FAULT_LITTLE 1340 0x8B: FailUnimpl::lddfa_snfl(); 1341 1342 format BlockLoad { 1343 // LDBLOCKF 1344 // ASI_BLOCK_AS_IF_USER_PRIMARY 1345 0x16: FailUnimpl::ldblockf_aiup(); 1346 // ASI_BLOCK_AS_IF_USER_SECONDARY 1347 0x17: FailUnimpl::ldblockf_aius(); 1348 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1349 0x1E: FailUnimpl::ldblockf_aiupl(); 1350 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1351 0x1F: FailUnimpl::ldblockf_aiusl(); 1352 // ASI_BLOCK_PRIMARY 1353 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 1354 // ASI_BLOCK_SECONDARY 1355 0xF1: FailUnimpl::ldblockf_s(); 1356 // ASI_BLOCK_PRIMARY_LITTLE 1357 0xF8: FailUnimpl::ldblockf_pl(); 1358 // ASI_BLOCK_SECONDARY_LITTLE 1359 0xF9: FailUnimpl::ldblockf_sl(); 1360 } 1361 1362 // LDSHORTF 1363 // ASI_FL8_PRIMARY 1364 0xD0: FailUnimpl::ldshortf_8p(); 1365 // ASI_FL8_SECONDARY 1366 0xD1: FailUnimpl::ldshortf_8s(); 1367 // ASI_FL8_PRIMARY_LITTLE 1368 0xD8: FailUnimpl::ldshortf_8pl(); 1369 // ASI_FL8_SECONDARY_LITTLE 1370 0xD9: FailUnimpl::ldshortf_8sl(); 1371 // ASI_FL16_PRIMARY 1372 0xD2: FailUnimpl::ldshortf_16p(); 1373 // ASI_FL16_SECONDARY 1374 0xD3: FailUnimpl::ldshortf_16s(); 1375 // ASI_FL16_PRIMARY_LITTLE 1376 0xDA: FailUnimpl::ldshortf_16pl(); 1377 // ASI_FL16_SECONDARY_LITTLE 1378 0xDB: FailUnimpl::ldshortf_16sl(); 1379 // Not an ASI which is legal with lddfa 1380 default: Trap::lddfa_bad_asi( 1381 {{fault = new DataAccessException;}}); 1382 } 1383 } 1384 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1385 0x36: stqfa({{fault = new FpDisabled;}}); 1386 format StoreAlt { 1387 0x37: decode EXT_ASI { 1388 // ASI_NUCLEUS 1389 0x04: FailUnimpl::stdfa_n(); 1390 // ASI_NUCLEUS_LITTLE 1391 0x0C: FailUnimpl::stdfa_nl(); 1392 // ASI_AS_IF_USER_PRIMARY 1393 0x10: FailUnimpl::stdfa_aiup(); 1394 // ASI_AS_IF_USER_PRIMARY_LITTLE 1395 0x18: FailUnimpl::stdfa_aiupl(); 1396 // ASI_AS_IF_USER_SECONDARY 1397 0x11: FailUnimpl::stdfa_aius(); 1398 // ASI_AS_IF_USER_SECONDARY_LITTLE 1399 0x19: FailUnimpl::stdfa_aiusl(); 1400 // ASI_REAL 1401 0x14: FailUnimpl::stdfa_real(); 1402 // ASI_REAL_LITTLE 1403 0x1C: FailUnimpl::stdfa_real_l(); 1404 // ASI_REAL_IO 1405 0x15: FailUnimpl::stdfa_real_io(); 1406 // ASI_REAL_IO_LITTLE 1407 0x1D: FailUnimpl::stdfa_real_io_l(); 1408 // ASI_PRIMARY 1409 0x80: FailUnimpl::stdfa_p(); 1410 // ASI_PRIMARY_LITTLE 1411 0x88: FailUnimpl::stdfa_pl(); 1412 // ASI_SECONDARY 1413 0x81: FailUnimpl::stdfa_s(); 1414 // ASI_SECONDARY_LITTLE 1415 0x89: FailUnimpl::stdfa_sl(); 1416 // ASI_PRIMARY_NO_FAULT 1417 0x82: FailUnimpl::stdfa_pnf(); 1418 // ASI_PRIMARY_NO_FAULT_LITTLE 1419 0x8A: FailUnimpl::stdfa_pnfl(); 1420 // ASI_SECONDARY_NO_FAULT 1421 0x83: FailUnimpl::stdfa_snf(); 1422 // ASI_SECONDARY_NO_FAULT_LITTLE 1423 0x8B: FailUnimpl::stdfa_snfl(); 1424 1425 format BlockStore { 1426 // STBLOCKF 1427 // ASI_BLOCK_AS_IF_USER_PRIMARY 1428 0x16: FailUnimpl::stblockf_aiup(); 1429 // ASI_BLOCK_AS_IF_USER_SECONDARY 1430 0x17: FailUnimpl::stblockf_aius(); 1431 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1432 0x1E: FailUnimpl::stblockf_aiupl(); 1433 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1434 0x1F: FailUnimpl::stblockf_aiusl(); 1435 // ASI_BLOCK_PRIMARY 1436 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 1437 // ASI_BLOCK_SECONDARY 1438 0xF1: FailUnimpl::stblockf_s(); 1439 // ASI_BLOCK_PRIMARY_LITTLE 1440 0xF8: FailUnimpl::stblockf_pl(); 1441 // ASI_BLOCK_SECONDARY_LITTLE 1442 0xF9: FailUnimpl::stblockf_sl(); 1443 } 1444 1445 // STSHORTF 1446 // ASI_FL8_PRIMARY 1447 0xD0: FailUnimpl::stshortf_8p(); 1448 // ASI_FL8_SECONDARY 1449 0xD1: FailUnimpl::stshortf_8s(); 1450 // ASI_FL8_PRIMARY_LITTLE 1451 0xD8: FailUnimpl::stshortf_8pl(); 1452 // ASI_FL8_SECONDARY_LITTLE 1453 0xD9: FailUnimpl::stshortf_8sl(); 1454 // ASI_FL16_PRIMARY 1455 0xD2: FailUnimpl::stshortf_16p(); 1456 // ASI_FL16_SECONDARY 1457 0xD3: FailUnimpl::stshortf_16s(); 1458 // ASI_FL16_PRIMARY_LITTLE 1459 0xDA: FailUnimpl::stshortf_16pl(); 1460 // ASI_FL16_SECONDARY_LITTLE 1461 0xDB: FailUnimpl::stshortf_16sl(); 1462 // Not an ASI which is legal with lddfa 1463 default: Trap::stdfa_bad_asi( 1464 {{fault = new DataAccessException;}}); 1465 } 1466 } 1467 0x3C: CasAlt::casa({{ 1468 mem_data = htog(Rs2.uw); 1469 Mem.uw = Rd.uw;}}, 1470 {{ 1471 uint32_t tmp = mem_data; 1472 Rd.uw = tmp; 1473 }}, MEM_SWAP_COND); 1474 0x3D: Nop::prefetcha({{ }}); 1475 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 1476 Mem.udw = Rd.udw; }}, 1477 {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); 1478 } 1479 } 1480} 1481